WO2008028853A1

WO2008028853A1 - Circuit configuration, and method for the operation of a circuit configuration

Info

Publication number: WO2008028853A1
Application number: PCT/EP2007/059012
Authority: WO
Inventors: Peter Bösmüller; Johannes Fellner
Original assignee: Austriamicrosystems Ag
Priority date: 2006-09-07
Filing date: 2007-08-29
Publication date: 2008-03-13
Also published as: DE102006042115A1; DE102006042115B4

Abstract

Disclosed is a circuit configuration comprising a control circuit (400) and a memory chain (500). The memory chain (500) encompasses a first plurality n of memory circuits (501, 511, 521, 531), at least one of which is provided with a non-volatile memory cell (502, 512, 522, 532) and a first output (505, 515, 525, 535) for supplying an output signal (DATAOUT1, DATAOUT2, DATAOUT3, DATAOUT4). An output (413) of the control circuit (400) is coupled to an input (503) of the first memory circuit (501).

Description

description

Circuit arrangement and method for operating a circuit arrangement

The present invention relates to a circuit arrangement having a control circuit and a memory chain, a use of the circuit arrangement and a method for operating a circuit arrangement.

A memory may include nonvolatile memory cells and store data such as serial numbers or trim settings of analog circuits in a semiconductor body.

Document US 5,384,746 shows a circuit and method for storing and retrieving data. The circuit uses a fuse, English fuse, to store.

The object of the present invention is to provide a circuit arrangement and a method for operating a circuit arrangement which can store more than one bit and can be used flexibly.

This object is achieved with the subject of claim 1 and the method according to claim 14. Further developments and refinements are the subject matter of the dependent claims.

According to the invention, a circuit arrangement comprises a control circuit and a memory chain which is coupled to the control circuit. The memory chain comprises a first plurality n of memory circuits. At least one memory circuit of the first plurality n of memory circuits comprises a non-volatile memory cell, an input and a first output. The control circuit is connected to the input of the first memory circuit.

The control circuit provides information on the output side, which are supplied to the memory chain. The information provided is supplied to the memory circuits. At least one memory circuit provides an output signal at the respective first output.

It is an advantage of the circuit arrangement that a plurality n of nonvolatile memory cells can be operated with the plurality n of memory circuits and thus a larger amount of data than 1 bit can be stored. The first plurality n is flexibly adaptable to the amount of data to be stored. It is an advantage of the circuit arrangement that the necessary functions for the memory circuits are combined in a control circuit.

In one embodiment, the circuit arrangement comprises a data bus which is coupled to the first outputs of the memory circuits for outputting the output signals to the data bus and is realized as a parallel bus with the first plurality n of lines. Advantageously, the output signals can be output independently of the clock via the data bus. The output signals may advantageously be provided immediately after the switching on of the circuit arrangement.

In one embodiment, the information provided may be supplied to the memory circuits in serial form. Alternatively, these may be supplied in parallel form to the memory circuits. Preferably, the information in some cases in serial form and partly in parallel form to the memory circuits.

The input of at least one memory circuit of the first plurality n of memory circuits comprises a data input, a clock input and a control input. The control circuit is connected to the data input of the input of the first memory circuit.

The data input can have multiple lines. Preferably, the data input comprises a line.

The clock input may preferably have a line. The clock input is supplied with a clock signal.

The control input can have a line. The control input preferably comprises a plurality of lines. A control signal is supplied to the control input. Preferably, the control signal comprises a plurality of signals.

At least one memory circuit of the first plurality n of memory circuits comprises the non-volatile memory cell, the data input, the clock input and the control input and the first output. At least one memory circuit may mean that exactly one memory circuit of the first plurality n of memory circuits comprises this or, alternatively, that a plurality of memory circuits of the first plurality n of memory circuits each comprise this. This preferably means that each memory circuit of the first plurality of memory circuits comprises this.

In one embodiment, the memory circuits are connected in series. The data input of the first memory connected to an output of the control circuit. The data input of a further memory circuit is connected to a second output of the respective upstream memory circuit. The control signal or the plurality of signals of the control signal are given by the control circuit in parallel to the plurality n of the memory circuits. It is an advantage of the serial arrangement of the memory circuit that only a small number of control and data lines are required, which are independent of the first multiple number n of the memory circuits.

In one embodiment, the clock signal is supplied to the clock input of the first memory circuit. In a development of the embodiment, the clock signal is fed to at least one further memory circuit. Preferably, the clock signal is supplied to each memory circuit. The clock signal may be provided by the control circuit.

In one embodiment, the control circuit provides a first data signal which is supplied to the data input of the first memory circuit. The first memory circuit outputs a second data signal at the second output of the first memory circuit. In this case, the first memory circuit generates the second data signal as a function of the clock signal and of the first data signal and the control signals applied in parallel to all the memory circuits. The second and one further memory circuit emit at the second output a third or further data signal, which is provided as a function of a data signal, the control signals and the clock signal, which is supplied to the data input of the second or further memory circuit. Advantageously, thus, a data signal from the first Memory circuit are looped through to the last memory circuit.

The clock signal may be used to trigger the propagation of the data signal from one memory circuit to the next memory circuit.

In a further development, one of the last memory circuits has a signal output. At this a processing signal is provided. The signal output is with the

Control circuit connected to which the processing signal is supplied. It is an advantage of this embodiment that the control circuit can be realized independently of the number of memory circuits to be driven by it. The circuit arrangement is thus very flexible adaptable to the amount of data to be stored with advantage.

In one embodiment, the control circuit comprises a flow control. The scheduler may include a microprocessor. Alternatively, the sequence control can be realized as a logic circuit. Preferably, the sequence control is implemented as a finite state machine, so that the outlay and area required for the control circuit are kept low.

An oscillator for outputting an internal clock signal may be coupled to the scheduler via a multiplexer. The internal clock signal may alternatively be provided by an external clock source.

In a further development, the circuit arrangement comprises a circuit arrangement connection, which is connected to a first terminal of the non-volatile memory cell of the first memory circuit. A second connection of non-volatile Memory cell of the first memory circuit may be connected to a reference potential terminal. Preferably, the circuit arrangement terminal comprises a pad, English ped. The circuit assembly terminal may be for contacting the non-volatile memory cell from outside the circuitry. An analog signal may be tapped at the circuit assembly terminal corresponding to a voltage drop between the first and second terminals of the nonvolatile memory cell. Advantageously, the first and the second terminal of the nonvolatile memory cell can be contacted with low resistance by means of the circuit arrangement connection and the reference potential terminal.

In an embodiment, the circuit arrangement terminal may be implemented as a bidirectional terminal. The bidirectional terminal may be connected to the sequencer and / or to the last memory circuit and / or to the first memory circuit. Preferably, the bidirectional terminal is connected to all memory cells.

In one embodiment, the bidirectional terminal is connected via a second switch to the first terminal of the nonvolatile memory cell of the first memory circuit. Depending on the control and data signals, the connection can be activated effectively. The compound is preferably designed low impedance. The second terminal of the nonvolatile memory cell of the first memory circuit may be connected to the reference potential terminal via a programming transistor. It is an advantage of this arrangement that essentially only the non-volatile memory cell of the first memory circuit is connected between the bidirectional connection and the reference potential connection, so that by means of a measuring device which is connected externally to the bidirectional connection. len connection can be connected, a resistance value of the non-volatile memory cell can be determined. Alternatively, the resistance value at the bidirectional connection can also be determined by a measuring circuit on a semiconductor body comprising the circuit arrangement. It is a further advantage that the non-volatile memory cell can be programmed via this low-resistance access to the non-volatile memory cell of the first memory circuit. The programming can be carried out by means of a programming current, which is supplied to the bidirectional connection.

In a development, the first terminals of the nonvolatile memory cells are connected to one another and connected via the second switch to the bidirectional terminal. The respective second terminal of the non-volatile memory cell is in each case connected to the reference potential terminal via its own programming transistor. Thus, it can be selected via the respective programming transistor, which of the non-volatile memory cells is directly connected to the bidirectional terminal, so that a resistance value of this non-volatile memory cell can be determined or the respective non-volatile memory cell can be programmed by means of a programming current.

The non-volatile memory cell may be a mask-programmed memory cell. Alternatively, the nonvolatile memory cell may comprise a reversibly programmable memory cell. In a further alternative embodiment, the non-volatile memory cell can be realized as an irreversibly programmable memory cell. The non-volatile memory cell may advantageously be electrically programmable. The non-volatile memory cell may be realized as a resistor, wherein a programming current irreversibly increases the resistance value of the non-volatile memory cell. Alternatively, the non-volatile memory cell may be a fuse, in other words fuse, which is programmed by means of a laser beam. Preferably, the non-volatile memory cell is realized as a fuse comprising a resistor which can be fused by means of a programming current. The non-volatile memory cell may comprise a metal resistor, a polysilicon resistor or a combined polysilicon / silicide resistor.

In an alternative embodiment, the non-volatile memory cell can be realized as an antifuse element, wherein the resistance value can be reduced irreversibly by means of a programming current. In one embodiment, the antifuse element can be realized as a diode, in particular as a Zener diode.

The circuit arrangement can be formed on a semiconductor body. It can be implemented in a bipolar integration technique. Preferably, it can be produced by means of complementary metal-semiconductor-semiconductor integration technology, abbreviated CMOS integration technology, and can have switches and transistors realized as field effect transistors.

The circuitry can be used for permanent storage of data. The data may include a serial number or an identification number for the semiconductor body. Alternatively, the circuit arrangement for storing a trim setting of an analog circuit, in particular an analog / digital or a digital / analog converter, may be provided. It can be used to repair a dorn Access Memory, abbreviated RAM, by accessing redundant cells or columns instead of defective rows or columns.

According to the invention, a method for operating a circuit arrangement provides the following steps: A first data signal is supplied to a first memory circuit of a first plurality n of series-connected memory circuits. The first memory circuit comprises a non-volatile memory cell. A control signal is provided in parallel with the first plurality n of the memory cells. A second data signal is provided by the first memory circuit on the output side. The second data signal is generated in response to the control signal and from the first data signal. The second data signal is supplied to the second memory circuit. Accordingly, the second memory circuit provides a further data signal, which is supplied to a downstream memory circuit. The further data signal is generated as a function of the supplied control signal and the previous data signal. Advantageously, the data signals are thus looped through from one memory circuit to the next memory circuit.

In one embodiment, the method comprises reading data from the memory circuits in parallel by providing the first plurality n of output signals on an internal bus, which is realized as a parallel bus with the first plurality n of lines. Advantageously, the output signals output by the first plurality n of memory circuits can be fed directly and clock-independent to a circuit part of the circuit arrangement. This can advantageously be carried out immediately after switching on a power supply of the circuit arrangement. In a development, a clock signal is supplied to the first memory circuit. Preferably, the clock signal is supplied in parallel to all the memory circuits. The second data signal is generated in response to the control signal, the first data signal and the clock signal.

In one embodiment, the control signal and the first data signal are provided by a control circuit. The control signal may comprise a plurality of signals. The clock signal may be supplied externally to the circuitry. Alternatively, the clock signal may be provided as an internal clock signal from the control circuit.

In a development, the method comprises supplying data signals to the first plurality n of memory circuits, providing the first plurality n of output signals to a circuit part and checking the output signals by means of the circuit part. Furthermore, the method comprises programming the non-volatile memory cells as a function of the data signals. Advantageously, the data are thus first tested before they are written firmly into the non-volatile memory cells.

In the following, the invention will be explained in more detail by means of the figures with reference to several exemplary embodiments. Functionally or functionally identical components carry the same reference numerals. Insofar as circuit parts or components correspond in their function, their description is not repeated in each of the following figures.

FIG. 1 shows an exemplary embodiment of a

Circuit arrangement with a control circuit and a memory chain, Figure 2 shows an exemplary embodiment of the circuit arrangement and

FIG. 3 shows an exemplary embodiment of a memory circuit with a non-volatile memory cell.

FIG. 1 shows an exemplary embodiment of a circuit arrangement having a control circuit 400 and a memory chain 500. The control circuit 400 has a sequence controller 440. The sequence control 440 is implemented as a finite state machine, abbreviated FSM. The memory chain 500 comprises a first plurality n of series-connected memory circuits 501, 511, 521, 531. In the exemplary embodiment of FIG. 1, the first plurality n is equal to 4. The sequencer 440 is connected via an output 413 of the control circuit 400 is connected to a data input 503 of an input of the first memory circuit 501. The sequence control is connected via a further output 417 in parallel with the control inputs 507, 517, 527, 537 of the inputs of the memory circuits 501, 511, 521, 531. The connection of the further output 417 to the control inputs 507, 517, 527, 537 comprises a plurality of lines. The memory circuits 501, 511, 521, 531 each have a non-volatile memory cell

502, 512, 522, 532. The input of the first memory circuit 501 comprises a clock input 504 and the control input 507. The first memory circuit 501 has a first output 505 and a second output 506, which is connected to a data input 513 of the second memory circuit 511. Furthermore, the input of the second memory circuit 511 comprises a clock input 514 and the control input 517. The second memory circuit 511 comprises a first output 515 and a second output 516 connected to a data input 523 of the next memory circuit 521. Furthermore, the input of the third memory circuit 521 comprises a clock input 524 and the control input 527. The third memory circuit 521 comprises a first output 525 and a second output 526 which is connected to a data input 533 of the fourth memory circuit 531, ie the last memory circuit. Furthermore, the input of the fourth memory circuit 531 comprises a clock input 534 and the control input 537. The fourth memory circuit 531 comprises a first output 535, a signal output 599 which is coupled to the flow control 440 of the control circuit 400, and a serial data output 598.

The sequencer 440 provides at the output 413 a first data signal Sl, which is fed to the data input 503 of the input of the first memory circuit 501. The sequencer 440 provides at the output 417 a control signal Fl, which is supplied in parallel to the control inputs 507, 517, 527, 537 of the memory circuits 501, 511, 521, 531. The clock inputs 504, 514, 524, 534 of the memory circuits 501, 511, 521, 531, a clock signal SCLK is fed. At the first output 505 of the first memory circuit 501, a first output signal DATA OUTl can be tapped off. The first memory circuit 501 generates a second data signal S2, which is supplied via the second output 506 of the first memory circuit 501 to the data input 513 of the second memory circuit 511 in response to the control signal 507, the first data signal Sl and the clock signal SCLK. At the first output 515 of the second memory circuit 511, a second output signal DATAOUT2 can be tapped off. The second memory circuit 511 provides a third data signal S3 at the second output 516 of the second memory circuit 511. The third Data signal S3 is generated in response to the control signal Fl, the second data signal S2 and the clock signal SCLK. Analogously, the third and fourth memory circuits 521, 531 at their respective first outputs 525, 535 provide a third and fourth output, respectively

DATAOUT3, DATAOUT4 ready. The fourth memory circuit 531 provides at the signal output 599 a processing signal REGLAST, which is supplied to the sequencer 440 in the control circuit 400. Signal REGLAST indicates that an instruction or data information has been supplied to the last memory circuit 531. By supplying the processing signal REGLAST from the last memory circuit 531 to the control circuit 400, the control circuit 400 receives the information as to whether data or a command is looped through the memory chain 500. The fourth memory circuit 531 further provides at the serial data output 598 a serial data signal REGOUT comprising the data of the first through the fourth output signals DATAOUT1, DATAOUT2, DATAOUT3, DATAOUT4. The first to the fourth output signal DATAOUT1, DATAOUT2, DATAOUT3, DATAOUT4 can be tapped in series at the serial data output 598.

It is an advantage of the circuit arrangement according to FIG. 1 that the control circuit 400 and the storage chain 500 can be designed independently of each other. The control circuit 400 is independent of the first plurality n of memory elements in the memory chain 500.

In an alternative embodiment, the penultimate memory circuit, that is to say according to FIG. 1, the third memory circuit 521 has the signal output 599 for providing the execution signal REGLAST. Figure 2 shows an exemplary embodiment of the circuit arrangement, which is a development of Figure 1. The circuit arrangement may comprise the control circuit 400 and the memory chain 500 according to FIG. The four memory circuits 501, 511, 521, 531 may be referred to as four bit cells. The control circuit 400 has a detection circuit 410 and an oscillator 430 in addition to the process control 440. The detection circuit 410 is connected to the flow controller 440. The oscillator 430 is connected to an input of a signal switch 420, called in sequence MUX gate. The signal converter 420 is implemented as a multiplexer. An output of the MUX gate 420 is connected to the sequencer 440 and to the clock inputs 504, 514, 524, 534 of the memory circuits 501, 511, 521, 531. The circuit arrangement 700 has a first input 701, which is connected to the detection circuit 410. In addition, the circuit arrangement has a second input 702, which is connected to a further input of the MUX gate 420 and to an input of the detection circuit 410. The first and the second input 701, 707 each comprise a pad, English ped. The first and second inputs 701, 702 each have a buffer for signal matching. This buffer can be implemented as an in-circuit buffer or as a peripheral cell.

The circuit arrangement 700 further comprises a bidirectional terminal 300, which is connected at an output 301 to an input 403 of the sequencer 440 and to the recognition circuit 410. The bidirectional terminal 300 comprises a pad, English ped. The bidirectional terminal 300 may also be referred to as a circuit arrangement terminal. The serial data output 598 of the fourth memory circuit 531 is connected to an input 302 of the bidirectional len connection 300 connected. The bidirectional terminal 300 has a buffer 304, which is connected upstream of the output 301, and a further buffer 305, which is connected downstream of the input 302. A control input 303 of the bidirectional terminal 300 is connected to an output 411 of the sequencer 440. A connection 601, which is realized as a good conducting path, couples the bidirectional connection 300 via a second switch 600 to the analog connections 508 of the storage circuits 501, 511, 521, 531. The connection 601 is directly accessible externally without the interposition of a buffer. A control output 402 of the sequencer 440 is connected to a control input of the second switch 600. A circuit part, not shown, of the circuit arrangement is connected to the drain control 440 via an internal connection 401. The sequencer 440 is connected via an output 412 to a circuit part (not shown) of the circuit arrangement. The first outputs 505, 515, 525, 535 of the memory circuits 501, 511, 521, 531 are connected via an internal data bus 597 to a circuit part, not shown, of the circuit arrangement. The internal data bus 597 is realized as a parallel bus with the first plurality n of lines.

The detection circuit 410 is supplied via the first input 701, a mode signal SMODE, via the second input 702, a clock signal CLK and the third input 703, a signal SDATA. The detection circuit 410 detects the mode to be set from these signals. An operating mode may mean, for example, the parallel readout of the non-volatile memory cells 502, 512, 522, 532 of the four memory circuits 501, 511, 521, 531. Another mode, for example, the serial readout of the non-volatile memory cells 502, 512, 522, 532 in the form of the serial data signal REGOUT at the serial data output 598. Another mode of operation may include, for example, programming the nonvolatile memory cells 502, 512, 522, 532 via the connection 601, the second switch 600, and the bidirectional terminal 300. Another mode of operation may be, for example, connecting one of the non-volatile memory cells 502, 512, 522, 532 also via the connection 601 and the second switch 600 to the bidirectional terminal 300 for the purpose of determining the analog resistance value of the non-volatile memory cells 502, 512, 522, 532.

The clock signal CLK is fed via the second input 702 to an input of the MUX gate 420. The oscillator 430 provides on the output side an internal clock signal ICLK, which is fed to a further input of the MUX gate 420. A clock signal SCLK provided by the MUX gate 420 is supplied to the sequencer 440 and the clock inputs 504, 514, 524, 534 of the memory circuits 501, 511, 521, 531. The circuit can thus either with the external

Clock signal CLK or be operated with the generated by the internal integrated oscillator 430 clock signal ICLK.

The oscillator 430 may be switched via the multiplexer 420. The internal clock signal SCLK may be provided by the oscillator 430 or externally via the input 702.

The sequencer 440 may adjust the bidirectional port 300 according to the mode via a set signal ES provided by the sequencer 440 at the output 411. In the serial readout mode, the serial data signal REGOUT is provided to the serial data output 598 of the fourth memory circuit 531 and transmitted via the bidirectional port 300 is provided externally as a signal SDATA. Data, for example for programming the non-volatile memory cells 502, 512, 522, 532, are supplied as the signal SDATA via the bidirectional terminal 300 to the input 403 of the sequencer 440, which transfers the data via the output 413 by means of the first data signal Sl to the Data input 503 of the first memory cell 501 can forward. Via the connection 601, the bidirectional connection 300 can be connected to the analog connection 508 of the memory circuits 501, 511, 521, 531 and in this connection to the corresponding memory cell 502, 512, 522, 532. Thus, by means of this connection 601, a resistance value of the non-volatile memory cells 502, 512, 522, 532 can be measured in series or programmed. At the connection 601, an analog signal SANALOG can be tapped.

The four output signals DATAOUT1, DATAOUT2, DATAOUT3, DATA-OUT4 are supplied via the internal bus 597 in parallel to a further circuit part of the circuit arrangement, which is not shown. A signal POR is supplied to the sequencer 440 via the internal port 401. The POR signal allows the data to be read out of the non-volatile memory cells 502, 512, 522, 532 when the circuit is turned on and to be available on the internal bus 597. The drain controller 440 provides a ready signal SBUSY at the output 412, which includes information about the standby state of the control circuit 400 and the memory chain 500.

FIG. 3 shows an exemplary embodiment of a memory circuit as can be used in the circuit arrangements according to FIG. 1 and FIG. As an example, in FIG. 3, the first memory is stored for the plurality n of memory circuits. circuit 501. Embodiments of memory circuits other than those shown in FIG. 3 are also suitable for use in a memory chain, as shown in FIG. 1 or FIG.

The memory circuit 501 has a differential current path with a first branch 35 and a second branch 55, which are connected between a supply voltage terminal 9 and a reference potential terminal 8. The first and the second branch 35, 55 together form a differential current path of a comparator 3. The comparator 3 has a first amplifier 11 and a second amplifier 21. The first amplifier 11 is connected between a supply terminal 12 of the first amplifier 11 and the Bezugspotenzi- alanschluss 8 and has a first transistor 30 and a second transistor 40, which are connected to each other in series. The transistors 30, 40 are connected on the input side to an input 14 of the first amplifier 11. A node 31 between the first and second transistors 30, 40 of the first amplifier 11 forms an output 15 of the first amplifier 11. Accordingly, the second amplifier 21 has a first transistor 50 and a second transistor 60 connected between a supply terminal 22 of the second Amplifier 21 and the reference potential terminal 8 are connected. The two transistors 50, 60 of the second amplifier 21 are connected on the input side to an input 24 of the second amplifier 21. A node 51 between the first and second transistors 50, 60 of the second amplifier 21 serves as the output 25 of the second amplifier 21. The first amplifier 11 thus comprises an inverter and the second amplifier 21 also comprises an inverter. The two amplifiers 11, 21 are thus constructed symmetrically. The output 15 of the first amplifier 11 is connected to the input 24 of the second amplifier 11. th amplifier 21 and the output 25 of the second amplifier 21 is connected to the input 14 of the first amplifier 11. The output 15 of the first amplifier 11 is coupled via a first charging transistor 70 and the output 25 of the second amplifier 21 is coupled to the reference potential terminal 8 via a second charging transistor 80.

The first branch 35 comprises the non-volatile memory cell 502, which is connected between the supply terminal 12 of the first amplifier 11 and a connection node 2. The second branch 55 comprises a reference element 20, which is connected between the supply terminal 22 of the second amplifier 21 and the connection node 2. The connection node 2 is coupled to the supply connection 9 via a switch 160. A control input of the switch 160 is connected to a control output of a logic circuit 509 of the memory circuit 501. The connection node 2 is connected directly to the analog connection 508. The first and second charging transistors 70, 80 are connected to one another on the input side and to an output of the logic circuit 509.

The memory circuit 501 in FIG. 3 has a programming transistor 150, which connects the supply terminal 12 of the first amplifier 11 to the reference potential terminal 8. The programming transistor 150 is connected at a control input to an output of the logic circuit 509 of the memory circuit 501. In addition, a capacitive compensation element 151 is connected to the supply terminal 22 of the second amplifier 21. The compensation element 151 is designed as a transistor.

To the output 15 of the first amplifier 11 is a first buffer 106 and to the output 25 of the second amplifier 21st a second buffer 104 is connected. The first buffer 106 has an inverter, comprising two transistors 130, 140, which is connected between the supply voltage terminal 9 and the reference potential terminal 8. Accordingly, the second buffer 104 has a further inverter, comprising two transistors 110, 120, which is connected between the reference potential terminal 8 and the supply voltage terminal 9. The inputs of the two transistors 130, 140 of the first buffer 106 are connected to the output 15 of the first amplifier 11 and the inputs of the two transistors 110, 120 of the second buffer 104 to the output 25 of the second amplifier 21. A node 102 between the two transistors 110, 120 of the second buffer 104 forms an output of the second buffer 104, which is connected to the first output 505 of the first memory circuit 501.

The output 15 of the first amplifier 11 is connected via a first switch 100 of a writing arrangement 89 to a terminal of the logic circuit 509. Likewise, the output 25 of the second amplifier 21 is connected via a second switch 90 of the writing arrangement 89 to a further terminal of the logic circuit 509. The control terminals of the first and second switches 90, 100 are connected to one another and to a control input 92 of the write arrangement 89, which in turn is connected to a control output of the logic circuit 509.

The transistors 30, 40, 50, 60, 70, 80, 90, 100, 110, 120, 130, 140, 150, 151 and the switch 160 can be used as field effect transistors, in particular as metal oxide semiconductors

Field effect transistors, abbreviated MOSFETs, be realized. The logic circuit 509 is connected on the input side to the data input 503, the clock input 504 and the control input 507 of the first memory circuit 501 and the output side to the second output 506 of the first memory circuit 501. The logic circuit 509 comprises a flip-flop 510 and logic gates.

At the supply voltage terminal 9, a supply voltage VDD is connected. The control terminals of the first and the second charging transistor 70, 80, a charging signal SLOAD can be fed. The first and the second charging transistor 70, 80 and the switch 160 are turned on in a first operating state. Thus, the first transistor 30 and the first transistor 50 of the first and second amplifiers 11, 21 are conductive and the second transistor 40 and the second transistor 60 of the first and second amplifiers 11, 21 are turned off. Due to the different resistances of the non-volatile memory cell 502 and of the reference element 20, different currents II, 12 occur in the two branches of the differential current path 35, 55, which produce different voltage potentials at the supply terminals 12 and 22. When the two charging transistors 70 and 80 are turned off, the comparator 3 detects the voltage difference between the supply terminals 12 and 22 and stores the result in the two amplifiers 11 and 21 in a self-sustaining manner.

At the output 15 of the first amplifier 11 is an inverted output voltage NVOUT and at the output 25 of the second amplifier 21, an output voltage VOUT can be tapped. If the non-volatile memory cell 502 has a smaller resistance than the reference element 20, the inverted output voltage NVOUT rises faster than the output voltage VOUT, so that due to the feedback of the first th and the second amplifier 11, 21 of the second transistor 60 of the second amplifier 21 and the first transistor 30 of the first amplifier 11 are conductive and the other two transistors 50, 40 are connected as a barrier.

The programming transistor 150 serves to provide a first current Il having a high current value flowing through the non-volatile memory cell 502 to perform a program operation. Due to its size, the programming transistor 150 represents a capacitive load at the supply terminal 12. In the read-out operation described above, the two branches 35, 55 of the differential current path are advantageously capacitively charged in the same way in order to provide a symmetrical design of the comparator 3 guarantee. For this purpose, the supply connection 22 of the second amplifier 21 is connected to the compensation element 151. This compensation element 151 is designed as a transistor and represents for the second branch 55 of the differential current path the same capacitive load as the programming transistor 150 represents for the first branch 35. The analog signal SANALOG can be tapped off at a first connection of the non-volatile memory cell 502.

The logic circuit 509 is supplied with the first data signal Sl, the clock signal SCLK and the control signal Fl via the data input 503, the clock input 504 and the control input 507. In response to the clock signal SCLK, the control signal Fl and the data signal Sl, the logic circuit 509, using the flip-flop 510, sets the second data signal S2 as well as the signals for operating the memory circuit 501

Programming signal SBURN, the load signal SLOAD and the write signal WRITE ready. A data signal DATAIN and a data signal NDATAIN, which is inverted to that end, depends on the operating mode of provided to the logic circuit 509 or received by the logic circuit 509. The flip-flop 510 can be realized in a clock-controlled manner by means of the clock signal SCLK.

Advantageously, the comparator 3 is constructed symmetrically and comprises a self-holding function, which is achieved by the feedback of the two amplifiers 11, 21.

Advantageously, at the two outputs 15, 25 of the first and the second amplifier 11, 21 each have a buffer 104, 106 connected downstream, so that a capacitive load at the output 15 of the first amplifier 11 and a capacitive load at the output 25 of the second amplifier 21 are the same. Thus, downstream circuit parts do not affect the setting and switching operation of the first and second amplifiers

11, 21. Advantageously, by means of the write arrangement 89, the output voltage VOUT with the value of the data signal DATAIN and the inverted output voltage NVOUT with the value of the inverted data signal NDATAIN can be provided, then the two by means of a write control signal WRITE

Switch 90, 100 are turned on. Advantageously, it is therefore possible to store data in a second manner in the two amplifiers 11 and 21, provided that the nonvolatile memory cell 502 has a low impedance. Thus, for test purposes, data can be stored independently of the non-volatile memory cell 502.

In one embodiment, the non-volatile memory cell 502 is implemented as a one-time programmable memory element, abbreviated OTP element.

In an alternative embodiment, another memory circuit 511, 521, 531 has no clock input for feeding of the clock signal SCLK. In an alternative embodiment, the control signal Fl or the further data signals S2, S3, S4 comprise the clock signal SCLK or a signal derived from the clock signal SCLK.

LIST OF REFERENCE NUMBERS

2 connection nodes

3 comparator

8 Reference potential connection

9 supply connection

11 first amplifier

12 supply connection

14 entrance

15 output

20 reference element

21 second amplifier

22 supply connection

24 entrance

25 output

30 first transistor

31 knots

35 first branch

40 second transistor

50 first transistor

51 knots

55 second branch

60 second transistor

70 first charging transistor

80 second charging transistor

89 writing arrangement

90 second switch

91 second entrance

92 control input

100 first switch

101 first entrance

102, 103 knots

104 second buffer 106 first buffer

110, 120, 130, 140 transistor

150 programming transistor

151 compensation element 160 switches

300 bidirectional connection

301 output

302 entrance

303 control input 304, 305 buffers

400 control circuit

401 internal connection

402 control output

403 input 410 detection circuit

411, 412, 413, 417 Output 420 MUX gate

430 oscillator

440 Sequence control 500 memory chain

501 first memory circuit

511 second memory circuit

521 third memory circuit

531 fourth memory circuit 502, 512, 522, 532 non-volatile memory cell

503, 513, 523, 533 data input

504, 514, 524, 534 clock input

505, 515, 525, 535 first exit

506, 516, 526 second output 507, 517, 527, 537 control input

508 analog connection

509 logic circuit

510 flip-flop 597 internal bus

598 serial data output

599 signal output

600 second switch

601 connection

700 circuit arrangement

701 first entrance

702 second entrance

CLK clock signal

DATAIN data signal to be read

DATAOUTl first output signal

DATAOUT2 second output signal

DATAOUT3 third output signal

DATAOUT4 fourth output signal

ES tuning signal

Fl control signal

ICLK internal clock signal

Il first stream

12 second stream

NDATAIN inverted data signal

NDATAOUT inverted first data signal

NVOUT inverted output voltage

POR internal control signal

REGLAST processing signal

REGOUT serial data signal

SANALOG analog signal

SBURN programming signal

SBUSY ready signal

SCLK internal clock signal

SDATA signal

SLOAD charging signal

SMODE mode signal

SWRITE write control signal 51 first data signal

52 second data signal

53 third data signal

54 fourth data signal VDD Supply voltage VOUT Output voltage VSS Reference potential

Claims

claims

A circuit arrangement comprising a control circuit (400), a memory chain (500) comprising a first plurality n of memory circuits (501, 511, 521, 531) in which at least one of the memory circuits (501, 511, 521, 531)

a non-volatile memory cell (502, 512, 522, 532),

an input (503, 504, 507, 513, 514, 517, 523, 524, 527, 533, 534, 537) and a first output (505, 515, 525, 535) for outputting an output signal (DATAOUT1, DATAOUT2, DATAOUT3, DATAOUT4) and the input (503) of the first memory circuit (501) is coupled to an output (413) of the control circuit (400), and a data bus (597) connected to the first outputs (505, 515, 525, 535) of the memory circuits (501, 511, 521, 531) for outputting the output signals (DATAOUT1, DATAOUT2, DATAOUT3, DATAOUT4) is coupled to the data bus (597) and realized as a parallel bus with the first plurality n of lines.

2. Circuit arrangement according to claim 1, wherein the input of at least one of the memory circuits (501, 511, 521, 531) has a data input (503, 513, 523, 533), - a clock input (504, 514, 524, 534) and a control input (507, 517, 527, 537).

3. Circuit arrangement according to claim 2, wherein at least two memory circuits (501, 511, 521, 531) are connected in series and in each case the data input (513, 523, 533) of a further memory circuit (511, 521, 531) is coupled to a second output (506, 516, 526) of the respective upstream memory circuit (501, 511, 521).

4. Circuit arrangement according to claim 3, wherein the data input (503) of the first memory circuit (501), a first data signal (Sl) is fed to the clock input (504) of the first memory circuit (501) is fed to a clock signal (SCLK), the control input ( 507) of the first memory circuit (501) a control signal (Fl) is fed to the second output (506) of the first memory circuit (501) a second data signal (S2) in response to the control signal (Fl), the first data signal (Sl) and the clock signal (SCLK) is provided and in each case at the second output (516, 526) of the further memory circuit (511, 521), a further data signal (S3, S4) in response to the control signal (Fl), the clock signal (SCLK ) and a further data signal (S2, S3), which is the data input (513, 523) of the further memory circuit (511, 521) is supplied is provided.

5. Circuit arrangement according to one of claims 1 to 4, wherein a penultimate or a last of the plurality n of

Memory circuits (521, 531) having a signal output (599) which is coupled to the control circuit (400) for supplying a processing signal (REGLAST) to the control circuit (400).

6. Circuit arrangement according to one of claims 1 to 5, wherein at least one of the memory circuits (501, 511, 521, 531) comprises: a first amplifier (11) having an input (14) and an output (15) and connected between a supply terminal (12) of the first amplifier (11) and a reference potential terminal (8), and - a second Amplifier (21) having an input (24) connected to the output (15) of the first amplifier (11) and an output (25) connected to the input (14) of the first amplifier (11) , and is connected between a supply terminal (22) of the second amplifier (21) and the reference potential terminal (8),

- The non-volatile memory cell (502, 512, 522, 532), which is connected between the supply terminal (12) of the first amplifier (11) and a connection node (2), which is coupled to the supply terminal (9), and a Reference element (20) connected between the supply terminal (22) of the second amplifier (21) and the connection node (2).

7. Circuit arrangement according to claim 6, wherein the first amplifier (11) as an inverter and the second amplifier (21) are designed as inverters.

8. Circuit arrangement according to claim 6 or 7, wherein at least one memory circuit (501, 511, 521, 531) comprises: a first buffer (106), which is connected downstream of the output (15) of the first amplifier (11), and a second Buffer (104) which is connected downstream of the output (25) of the second amplifier (21) and on the output side of which the output signal (DATAOUT1, DATAOUT2, DATAOUT3, DATAOUT4) can be tapped off.

9. Circuit arrangement according to one of claims 2 to 8, wherein at least one memory circuit (501, 511, 521, 531) comprises a logic circuit (509) connected to the data input

(503, 513, 523, 533), the clock input (504, 514, 524, 534), the control input (507, 517, 527, 537) and the second output (506, 516, 526) is coupled.

10. Circuit arrangement according to one of claims 1 to 9, wherein the control circuit (400) comprises: - a flow control (440), an oscillator (430) which is coupled to the flow control (440) for outputting an internal clock signal (ICLK), and a detection circuit (410) coupled to the sequence controller (440) and configured to set an operating mode of the circuitry (700).

11. Circuit arrangement according to claim 10, comprising a first input (701), which is coupled to the detection circuit (410), a second input (702), which is provided for supplying a clock signal (CLK) and with the flow control (440 ), the memory circuits (501, 511, 521, 531) and the detection circuit (410), and - a bidirectional terminal (300) connected to the sequencer (440), the detection circuit (410) and a switch (600 ) is coupled to the memory circuits (501, 511, 521, 531).

12. Circuit arrangement according to claim 11, comprising a connection (601) of the bidirectional connection (300) via a second switch (600) which is coupled to the control circuit (400) at a control connection, to a terminal of the non-volatile memory cells (502, 512, 522, 532) of the memory circuits (501, 511, 521, 531).

13. Use of the circuit arrangement according to one of claims 1 to 12 for the permanent storage of data, in particular a serial number, a semiconductor body number or a trim setting of an analog circuit on a semiconductor body, which comprises the circuit arrangement.

14. A method for operating a circuit arrangement, comprising the following steps:

Supplying a control signal (Fl) and a first data signal (S1) to a first memory circuit (501) comprising a non-volatile memory cell (502), a first plurality n of serially connected memory circuits (501, 511, 521, 531),

Providing a second data signal (S2) as a function of the control signal (Fl) and the first data signal (S1) on the output side of the first memory circuit (501), respectively supplying a data signal (S2, S3, S4) to a further memory circuit (511, 521 , 531) and providing the respective data signal (S3, S4) to a downstream memory circuit (521, 531) in dependence on the supplied control signal (Fl) and the supplied data signal (S2, S3) and parallel reading out of data of the memory circuits ( 501, 511, 521, 531) by providing the first plurality n of output signals (DATAOUT1, DATAOUT2, DATAOUT3, DATAOUT4) on an internal bus (597) implemented as a parallel bus with the first plurality n of lines.

15. The method according to claim 14, wherein a clock signal (SCLK) is supplied to at least the first one of the memory circuits (501, 511, 521, 531) and the second data signal (S2) is provided in response to the clock signal (SCLK).

16. The method according to claim 14 or 15, comprising providing a processing signal (REGLAST) by the penultimate or last memory circuit (521, 531) after the control signal (Fl) and the associated data signal (S3, S4) of the penultimate and the last memory circuit ( 521, 531).

17. The method according to any one of claims 14 to 16, comprising serially reading out data from the memory circuits (501, 511, 521, 531) by serially providing the first plurality n of output signals (DATAOUT1, DATAOUT2, DATAOUT3, DATAOUT4) on a serial basis Data output (598).

18. The method according to claim 14, comprising providing a connection between an external connection (300) and a connection of one of the non-volatile memory cells (502, 512, 522, 532) and a connection between a reference potential connection (8) and another connection of the non-volatile memory cell (502, 512, 522, 532) for an analog measurement of a resistance value of the non-volatile memory cell (502, 512, 522, 532) or for programming the non-volatile memory cell (502, 512, 522 , 532) by means of a programming stream.

A method according to any one of claims 14 to 18, comprising providing a connection between a supply voltage terminal (9) and a terminal of one of the non-volatile memory cells (502, 512, 522, 532) and a connection between a reference potential terminal (8) and another terminal of the non-volatile memory cell (502, 512 , 522, 532) for programming the non-volatile memory cell (502, 512, 522, 532) by means of a programming current.

20. The method of claim 18, wherein a level of the programming current is set such that the non-volatile memory cell is burned through.