WO2008020368A2

WO2008020368A2 - Rf transmitter with controlable rf power amplifier

Info

Publication number: WO2008020368A2
Application number: PCT/IB2007/053140
Authority: WO
Inventors: Mihai A.T. Sanduleanu; Ram P. Aditham
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2006-08-15
Filing date: 2007-08-08
Publication date: 2008-02-21
Also published as: WO2008020368A3

Abstract

The invention provides a mult i- standard RF transmitter including a power amplifier (6) for amplifying an RF signal prior to generating an output RF signal (7). A mode of operation of the power amplifier can be controlled, e.g. between class AB and class D operation, by a control circuit (4) operationally connected (5) to the power amplifier (6). Preferably, the control circuit (4) operates as a common-mode control. The mode of operation of the power amplifier (6) is controlled in response to a control parameter, e.g. a level of the input signal (1), a required power, a required efficiency, a desired type of modulation, or a desired degree of linearity. Thus, with this capability to adjust a mode of operation of the power amplifier, the RF transmitter can comply with many communication standards with different requirements, e.g. class AB mode for high linearity and class D mode for high efficiency. The RF transmitter is suited for on-chip implementation. In preferred embodiments, the control circuit (4) generates an amplitude modulated signal (5) to the power amplifier (6) to control its mode of operation. Preferably, the power amplifier (6) includes separated paths for amplitude modulation signals and phase modulation signals, e.g. implemented as a differential cascode coupling with a mixer stage. Preferred embodiments are based on NPWM modulation of phase and amplitude signals, either in analog or digital domain.

Description

RF transmitter with controlable RF power amplifier

FIELD OF THE INVENTION

The present invention relates to a transmitter for Radio Frequency (RF) signals. More specifically, the invention relates to an RF transmitter capable of a handling a variety of transmission standards. In addition, the invention provides an integrated circuit including such RF transmitter and a device including the RF transmitter.

BACKGROUND OF THE INVENTION

Many modern wireless devices are required to be compatible with a large variety of wireless transmission standards. Thus, design of low cost multi-standard RF transmitters for such devices that can be integrated on-chip, preferably in one single chip, has become challenging. Standards such as WLAN 802.11 a/b/g (up to 6 GHz), GSM (from 900 Mhz), Bluetooth, GPS and CDMA are examples of widespread standards that put different contradictory requirements on the RF transmitter.

For example requirements to the RF Power Amplifier (PA) for generating the output antenna are very strict to be able to fulfill requirements in different standards. Signal linearity and power efficiency are contradictory parameters for RF power amplifiers which becomes a problem for wireless standards with amplitude and phase /frequency modulation.

In e.g. the OFDM standard peak to average rations of 10 dB in some cases are seen, and here precision class A or AB PAs can used to fulfill this requirements resulting, however, with a poor efficiency as the result. E.g. WLAN power amplifiers on the market provide power levels in the order of 19-21 dBm fulfilling the EVM requirements resulting in a PAE of 25%.

In classical approaches the PA driver is implemented with discrete components with resonant loads for efficiency improvements. Such solutions are possible to integrate on-chip, but a large chip area is required to implement resonant loads with integrated inductors and capacitors. Thus, such design is not suited for integrated broadband solutions with integrated PA adapted for low cost production. SUMMARY OF THE INVENTION

Hence, it is an object to provide a multi-standard RF transmitter suited for on-chip implementation. This object and several other objects are obtained in a first aspect of the invention by providing an RF transmitter arranged to receive an input signal and generate an output RF signal representing the input signal, the RF transmitter comprising: a power amplifier arranged to amplify an RF signal and generate the output

RF signal in response, wherein a mode of operation of the power amplifier can be controlled, and a control circuit operationally connected to the power amplifier to control the mode of operation of the power amplifier in response to a control parameter. An RF transmitter according to the first aspect complies with the mentioned object since the controllable mode of operation of the RF power amplifier enables the RF transmitter to function according to a variety of wireless standards, e.g.

WLAN 802.11 a/b/g (up to 6 GHz), GSM (from 900 Mhz), Bluetooth, GPS and CDMA, since the controllable mode of operation provides a flexible power amplifier that can meet contradicting requirements by different standards which is not possible by an amplifier in a fixed mode of operation. Still the RF transmitter is possible to integrate on-chip, e.g. in a single chip since the power amplifier can implemented without space consuming components, and heat dissipation is minimized since the power amplifier can be driven in a high efficient mode at large signal levels.

In preferred embodiments, the control circuit can control a class of operation of the power amplifier. Especially, the control circuit is capable of switching between two or more of class A, class AB, class C and class D operation of the power amplifier. Thus, in these embodiments, the mode of operation of the power amplifier can be adjusted to fit high power efficiency requirements in case of large signal levels, e.g. class D operation, while another mode of operation can be selected to meet high linearity requirements at lower signal levels, e.g. class A or class AB operation. In preferred embodiments the control circuit operates as a common-mode control. This embodiment is suited e.g. for controlling power amplifiers based on a differential cascode coupling. Preferably, the control circuit can control the mode of operation of the power amplifier in response to at least one of: 1) a level of the input signal (1), 2) a required power, 3) a required efficiency, 4) a desired type of modulation, or 5) a desired degree of linearity. In general, the mode of operation of the power amplifier can be determined by properties of the baseband input signal, e.g. its level, and/or the mode of operation of the power amplifier can be determined by requirements of a selected wireless standard.

The power amplifier may have a differential configuration. Especially the power amplifier may be implemented with a set of cascode coupled transistors. These cascode coupled transistors may be used to control an output power of the power amplifier.

Preferably, the power amplifier includes separated paths for amplitude modulation signals and phase modulation signals, preferably implemented as a differential cascode coupled power amplifier. The control circuit may function as a soft limiter upon controlling the power amplifier to operate in class AB mode, and/or function as a hard limiter upon controlling the power amplifier to operate in class D mode.

In preferred embodiments, the control circuit is capable of generating an amplitude modulated signal to the power amplifier to control its mode of operation. In some embodiments, the power amplifier includes a mixer stage with first and second inputs arranged to receive the amplitude modulated signal at the first input and a phase modulated signal at the second input. An envelope pre-distorter for compensating non- linearity of the first input of the mixer stage may be included.

Preferably, the RF transmitter includes a digital processor arranged to generate amplitude and phase information of the input signal, and wherein the phase information is applied to an amplitude modulator that applies an RF carrier signal to the input signal. The RF transmitter may further include a sigma-delta frequency based synthesizer (ΣΔ-PLL) arranged to generate the RF carrier signal.

It is appreciated that any two or more of the above-mentioned embodiments or sub aspects of the first aspect may be combined in any way and may provide further advantageous effects.

In a second aspect the invention provides an integrated circuit (10) comprising an RF transmitter according to claim 1. In a third aspect, the invention provides a device comprising an RF transmitter according to the first aspect. The RF transmitter is advantageous for application, e.g. integration, into many types of devices for wireless transmission of data and/or audio and/or video signals. The device may be a mobile phone, a Wireless Local Area Network (LAN) device (such as a plug in card for a computer), an audio device, a video device or a Wireless Personal Area Network (WPAN) device that should operate in a high efficiency mode for saving battery power. Other relevant applications are base stations power amplifiers for which efficiency is important to save energy and reduce therefore the size of the transmit unit together with its power generator. The RF transmitter is advantageous for devices that can profit of access to different types of wireless connections, e.g. the GSM net and a WLAN. E.g. the device may be integrated into a net card for a computer, wherein the net card is capable of getting data access to the GSM net, a WLAN and a Bluetooth device (e.g. a headset).

It is appreciated that the same advantages and the same type of embodiments described for the first aspects apply also for the second and third aspects.

It is appreciated that advantages and embodiments mentioned for the first aspect also apply for the second and third aspects of the invention. It is also appreciated that any one aspect of the present invention may each be combined with any of the other aspects.

BRIEF DESCRIPTION OF THE FIGURES

The present invention will now be explained, by way of example only, with reference to the accompanying Figures, where

Fig.l illustrates a block diagram of an integrated circuit with a preferred RF transmitter embodiment,

Figs.2 and 3 illustrate block diagrams of an RF transmitter with Natural Pulse Width Modulation (NPWM) in situation where the power amplifier operates in class AB mode and in class D mode,

Fig.4 illustrates a preferred differential power amplifier configuration, Figs.5 and 6 illustrate power amplifiers with a mixer stage,

Fig.7 illustrates a circuit diagram of an embodiment with an envelope processor and differential cascode coupled mixer power amplifier, Fig.8 illustrates a differential cascode coupled polar modulator power amplifier, and

Figs.9-12 illustrate circuit diagrams of different implementations of RF transmitters according to the NPWM principle.

DETAILED DESCRIPTION OF EMBODIMENTS

Although the present invention has been described in connection with the specified embodiments, it is not intended to be limited to the specific form set forth herein. Rather, the scope of the present invention is limited only by the accompanying claims. In the claims, the term "comprising" does not exclude the presence of other elements or steps. Additionally, although individual features may be included in different claims, these may possibly be advantageously combined, and the inclusion in different claims does not imply that a combination of features is not feasible and/or advantageous. In addition, singular references do not exclude a plurality. Thus, references to "a", "an", "first", "second" etc. do not preclude a plurality. Furthermore, reference signs in the claims shall not be construed as limiting the scope.

Fig.1 shows in block diagram form a preferred RF transmitter implemented on a single integrated circuit 10. The RF transmitter is suited for multiple frequency band operation as well as operation according to multiple wireless standards. A digital processor receives a baseband input signal 1 and outputs an RF signal 3 in response by modulating the input signal 1 with an RF carrier. A control circuit 4 cooperates with the digital processor and generates a control signal 5 to control a mode of operation of the RF power amplifier 6 that also receives the RF signal 3 and generates an amplified RF output signal 7 representing the RF signal 3. This amplified RF signal 7 can then be applied to an RF antenna 8.

The control circuit 4 generates the control signal 5 based on a control parameter. The control signal 5 may in general be either an analog or a digital signal, and it is based on a control parameter. The control parameter may be a level of the input signal 1, a level of the RF signal 3, or the control parameter can be determined pre- selected based on a currently selected wireless mode of operation, i.e. depending on the selected wireless standard, e.g. such that the active wireless standard directly determines the mode of operation of the power amplifier 6. In a preferred embodiment, the control circuit 4 operates such that the generated control signal 5 can causes the power amplifier 6 to operate either in class AB mode of operation or in class D mode of operation. Thus, the RF transmitter is in a high linearity mode, where a high linearity of the RF output signal 7 is achieved at a rather low power efficiency. During class D mode of operation, the RF transmitter is in a high efficiency mode, where the RF output signal 7 is provided at a high power efficiency with a not optimal linearity. Preferably, class D mode of operation is selected when low signal levels are required, e.g. determined by level demanding wireless operating standards are active, and/or when high input signal 1 levels occur. Class AB is efficient at high power levels but the efficiency drops at low power levels where class D preferably takes over to keep efficiency high.

Figs.2 and 3 show the same preferred RF transmitter embodiment with an NPWM modulator principle. Fig.2 shows the RF transmitter when the RF power amplifier 26 is in class AB mode of operation where NPWM modulation is switched off, while Fig.3 shows the RF power amplifier 36 is in class D mode of operation and the NPWM modulation is active.

In both of Figs.2 and 3 the baseband processor BBP generates a digital amplitude signal A(t) and a digital phase signal φ(t) versus time t. These amplitude and phase signals are generated based on the I and Q baseband signals, e.g. using the cordic algorithm. At the output of the baseband processor, D/A converters provide amplitude information and phase information. The two different phase information signals are applied to AM modulators AMM, while the amplitude information signal serves as a control signal 25, 35 and is applied to the power amplifier 26, 36 to control its mode of operation, i.e. class AB or class D. A sigma-delta based phase locked loop ΣΔ-PLL has only one crystal connected, e.g. at a frequency of 26 MHz, and ΣΔ-PLL is capable of generating a large range of different carrier frequencies based on this crystal. A voltage- controlled oscillator RC VCO has a large tuning range, and the two carriers, in quadrature, generated from ΣΔ-PLL and the RC VCO are divided by 2. Depending on a selection signal SEL, the signals are hereafter modulated in multiplexers MUX and thereafter modulated in amplitude with the phase information signals. The bandwidth of the amplitude modulators AMM is possible to implement with a large bandwidth such that no bandwidth- limiting elements are present. The result of the amplitude modulation are the signals xi(t) and x₂(t). After the summation point the resulting signal is X₁(X)+ x₂(t), and this signal is applied at an input of the power amplifier 26, 36. Finally, an antenna is connected to the output of the power amplifier 26, 36 via a bandpass filter BPF. The BPF has the role of filtering out spurious tones that can fall in top of the adjacent channels and provide a clean spectrum to the antenna. The BPF functions in addition as a matching circuit too.

In Fig.2, i.e. in class AB mode of the power amplifier 26, the amplitude and phase information signals A(t) and φ(t) are represented by not NPWM modulated signals, as the NPWM modulation is switched off. Thus, the amplitude information will be applied separately to the PA in a polar modulator construction. The selection signals of the multiplexer is SEL=O, and the output of the MUX will pass the two quadrature carriers, sin(cθR_Ft) and cos(θ)RFt). The output stage is biased in class AB mode of operation and has high linearity.

In Fig. 3, i.e. in class D mode of operation of the power amplifier 36. By switching the NPWM modulator on and controlling the selection inputs SEL of the multiplexers, with -sin(2cθRFt) and +sin(2cθRFt) the RF transmitter thus works in high efficiency mode with the power amplifier 36 biased in class D mode of operation. The phase signals are now represented by NPWM modulated versions of the signals seen in Fig.2, i.e. NPWM{A(t)sinfo(t) + ty_o\ and NPWM {A(t)cos[$(t) + §₀]} . Before D/A conversion, these signals were converted in a naturally sampled or NPWM bitstream. However, the NPWM modulation can be done in the analog domain or in the digital domain. In both situations, the sampling clock of the NPWM modulator is related to the RF frequency of the RC VCO as f_c=f_RF/m where m is an integer. Another restriction relates to the phase of the sawtooth of the PWM modulator and the phase of the RF clock represented by LOi(t) and LO_Q(I). The control signal 35 applied to the power amplifier 36 is still A(t), i.e. not NPWM modulated.

After the addition of the signals xi(t) and x₂(t), the signal now applied at the input of the class D amplifier 36 is: X, (t) + X₂(O = — sin[ω_RFt -φ(t)] + — Ϋ sin[(2£ + I)GW - (-l)*φ(t)l

-1₍-_I) ^{4 cos}(^ ^{+ 1}W^ 2 |_s._n(2π^₀ _ ₍__1)t ^ _ ^ _s._n[φ(0]]j π S

The amplitude information is not yet present in the spectrum of eq. (1). It is added later in the output stage. The envelope with a DC-DC converter or class-S modulator has its own disadvantages. The range of this control is limited and the efficiency of the class-S modulator is of concern as the total efficiency will depend on it. The tracking bandwidth of the modulator is limited. Therefore, fast varying envelope signals are difficult to reproduce without distortion. Implementation of the power amplifier and NPWM modulator will be described in the following.

Fig.4 shows a circuit diagram for a preferred power amplifier based on a differential configuration with a pair of transistors Q3, Q4 providing a cascode coupling 41. The power amplifier has separated paths for amplitude and phase modulations. The common base 42 for the cascode transistors 41 is used as one path, while another set of transistors Ql, Q2 is configured to constitute a differential input RF+, RF-. Output of the power amplifier is connected to an antenna via a matching circuit Mc. Voltage supply is denoted Vcc, and it is applied to the power amplifier via a DC-DC converter 43.

The cascode transistors 43 are suitable for a number of reasons: 1) They allow large voltage swings at the output without reliability problems. Therefore, large power can be obtained with a relative large output impedance levels. The breakdown voltage of the compound transistor is higher than B_VCEO of a single transistor. 2) The under- stage transistors Ql, Q2 can be of low- voltage type meaning that they have lower breakdown voltages but larger power gain at higher frequencies. The cascode transistors 43 are high- voltage type with higher B_VCEO • Compound transistors perform better at higher frequencies and have a higher breakdown than a single differential stage. 3)

Another degree of freedom is gained by adding the cascode transistors 43 : they can serve as power control. Fig.5 shows another preferred power amplifier: a differential cascode based power amplifier with a mixer stage Mx. A static DC-DC converter SDC serves to connect the power amplifier to supply voltage VCC. In fact, the cascode transistors are configured as a Gilbert-cell to control the current of the under- stage transistors and the amount of current in the load. In this concept, the amplitude modulation or envelope

AM+, AM- is applied at one input of the mixer Mx and the phase modulation PM+, PM- is provided at the input of the differential under- stage Ql, Q2. The under- stage Ql, Q2 works with constant envelope signals modulated in phase and acts as a voltage-to-current converter for the phase signals PM+, PM-. Thereafter, the current produced by the under- stage is controlled by the amplitude modulated signal AM+, AM- at the input of the mixer Mx. The understage Ql, Q2 is biased in class AB mode.

Fig.6 shows the configuration of Fig.5 with an additional analog pre- distorter or envelope linearizer 60 inserted before the AM+, AM- input of the mixer Mx. The pre-distorter 60 serves to linearize the mixer stage with respect to the amplitude modulated inputs AM+, AM-. The pre-distorter 60 is of expanding type in order to compensate for the tanh(x) transfer characteristic of the mixer stage Mx.

Fig.7 shows a preferred power amplifier implementation of the circuit of Fig.6, including a phase modulation circuit part 72 with phase inputs PM+, PM-, and an envelope modulation circuit part 71 with inputs AM+, AM-. The envelope modulation circuit part 71 includes an implementation of the pre-distorter 60 of Fig.6, and this pre- distorter is now described in details.

The bias currents needed by the mixer Mx can be quite large as the current gain of the transistors at this frequency is low. A current buffer is needed to reduce harmonic distortion caused by the common-mode signals. Transistors Q9 and QlO work as a current buffer delivering large currents to the amplitude modulation inputs AM+, AM- of the mixer Mx. The amplitude modulation inputs AM+, AM- are applied to the linearized transconductor Q7, Q8. This linear voltage-current conversion is followed by conversion in a voltage on the resistors Ry. The role of those resistors will be disclosed later. By varying the voltage V_BIAS, the common-mode voltage at the mixer input will change. This sets the collector-emitter voltage of the under- stage transistors Ql, Q2 of the output stage. The voltage imbalance at the input of the pre-distorter is transferred at the voltage nodes Vl, V2 around a common-mode voltage generated by V_BIAS- In order to create the DC conditions for a pure cascode output stage, the current source I_BIAS generates a controlled offset of about 20OmV between the voltages Vl and V2. Therefore, the voltage Vl at the base of transistors Q4 and Q5 produces sufficient imbalance to shut-off the middle transistors Q4 and Q5. The whole current from the under- stage transistors flows only through lateral transistors Q3 and Q6. Thus, the power amplifier works in the cascode mode and can deliver maximum power close to the one-dB compression point (IdB CP). By decreasing the imbalance between the Vl and V2 nodes, the power gain decreases and, at ΔV=0 the power gain of the PA is zero as the two signal currents of the lateral transistors Q3, Q6 are fully compensated by the currents of the middle transistors Q4, Q5. The power control of this power amplifier is in the range of 70-80 dB with accurate analog steps. To allow envelope signals, the power amplifier is backed-off to points C or C respectively (e.g. C corresponds to an average power of 19 dBm allowing 7.5 dB or more for envelope signals). The excursion from A to B around C portrays the mechanism of power control under envelope modulated signals. The bandwidth of the envelope modulation processor is larger than 500 MHz. Therefore, this concepts allows rapid changes in amplitude as required by modern OFDM modulated signals (with 64-128QAM signals).

Fig.8 shows a power amplifier configured as polar modulator with envelope control AM on the base of the cascode transistors 81. In this approach the cascode transistors 81 work as emitter followers for the envelope signal that will be applied as a common-mode signal on the collectors of the under-stage Ql, Q2. The Early effect present at the transistors of the under-stage Ql, Q2 allows modulation of the common-mode collector current of the transistors Ql and Q2. This translates directly in an envelope signal at the differential output of the PA. The modulation mechanism can be simply understood from:

In (2) Ici,2 are the common-mode currents of the transistors Ql, Q2. The VcE represents their collector-emitter voltage and V_A is the Early voltage of the Qubic4G BiCMOS process. Obviously, a collector-emitter imbalance translates in a linear change of the collector current. The under-stage Ql, Q2 works with constant envelope signals modulated in phase and acts as a voltage-to-current converter for the phase signals PM+, PM-. Thereafter, the current produced by the under-stage Ql, Q2 is controlled by the AM signal of the cascode transistors. The under-stage is biased in class AB.

Figs.9-12 show preferred transistor level implementations. It is understood that circles numbered Ia- Id, 2a-2d, 3a-3d, 4a-4d, respectively, indicate connections between upper and lower circuits shown in these Figures.

Fig.9 shows a preferred implementation at a transistor level that solves the problem that the amplitude and phase information creates a disparity between the long pulses and very short pulses representing smaller amplitudes of the signal. This implementation is an NPWM RF transmitter where the duty-cycle of the NPWM modulator is always the same. No extra digital signal processing is needed in order to change "digitally" the duty cycle. Therefore, the characteristics of the NPWM are not changed. As the phase signal does not change a lot in amplitude, the short pulses are not any longer present in the NPWM signal. The envelope information, i.e. the amplitude information signal A(t), is applied to the envelope driver 93 and the mixer Mx. In this case, the class-S amplifier, i.e. the static DC-DC converter SDC provides a static change in the supply voltage 92 of the power amplifier, whereas the envelope driver 93 / mixer Mx tandem applies the fast varying envelope to the power amplifier.

The efficiency is taken care off by the class-D operation of the under-stage with operation class control 91 from the current I_DC- In conclusion, linearity is highly determined by the envelope processing circuits and the efficiency is determined by the class-D operation of the under-stage and the NPWM modulator. A static DC-DC converter will have a higher efficiency compared to the dynamic one and therefore, the total efficiency will not be limited by it. Fig.10 shows a variation of the circuit of Fig.9. In Fig.10 the DC-DC converter SDC of Fig.9 is not present at all, and the mixer Mx serves only for the power control 102. Still, the class control 101 is similar to that of Fig.9. The large variation in power obtainable from the mixer control does not require an extra external expensive component like the class-S amplifier. A variation in power of more than 70-80 dB is possible. This type of implementation is more suited for signals with relative small peak- to-average ratios, and Fig.10 can be seen as a low cost version of the implementation shown in Fig.9. Fig.11 shows another NPWM RF transmitter with cacode envelope control. In this specific implementation, the PWM modulator acts only on the phase information φ(t). Class of operation control 111 is similar to that described for the implementation of Figs.9 and 10. The envelope signal 113, A(t) is added to the base of the two cascode transistors Q21, Q22 together with a bias voltage. Again, a static DC-DC converter SDC is used only for power control.

Fig.12 shows an implementation suited for signals with no large peak-to- average ratios. The cascode stage controls the power of the output power amplifier via power control 122. However, this control has a smaller range than its mixer counterpart. Class control 121 is as previously described.

To summarize, the described embodiments present highly digitized transmitter functions with NPWM{AM/Vector PM} modulators class AB /D power amplifier and static DC-DC. The RF transmitter can work in class AB mode with high linearity and class D with high efficiency. Switching from one class to another is facilitated from a class control circuit that operates as a common-mode control. A broadband driver precedes a differential-cascode power amplifier. This broadband driver works as a soft limiter for AB operation and hard limiter for class-D operation.

In preferred embodiment, a hybrid ΔΣ-modulator is used together with a large tuning range RC oscillator. Amplitude and phase information are provided from a digital baseband processor and the phase modulation applied to a carrier by an amplitude modulator. The amplitude modulation can be applied to the output power amplifier as an analog signal after separate D/A conversion. Two alternative approaches can be applied: the mixer envelope control and the cascode bias control.

The classical polar modulator approach uses a fast DC-DC converter for tracking the envelope of the signal. This solution circumvents the disadvantages encountered in the DC-DC converter approach. Another problem solved is the power control and the operation class control that provides a solution tailored to different input power levels and efficiency requirements. Digitally controlled parameters (power, efficiency, modulation and linearity) provide an accurate monitoring of the power amplifier.

Claims

CLAIMS:

1. RF transmitter arranged to receive an input signal (1) and generate an output RF signal (7) representing the input signal (1), the RF transmitter comprising: a power amplifier (6, 26, 36) arranged to amplify an RF signal (3) and generate the output RF signal (7) in response, wherein a mode of operation of the power amplifier can be controlled, and a control circuit (4) operationally connected (5) to the power amplifier (6, 26, 36) to control the mode of operation of the power amplifier (6, 26, 36) in response to a control parameter.

2. RF transmitter according to claim 1, wherein the control circuit (4) is capable of controlling a class of operation of the power amplifier (6, 26, 36).

3. RF transmitter according to claim 2, wherein the control circuit (4) operates as a common-mode control.

4. RF transmitter according to claim 1, wherein the control circuit (4) is arranged to control the mode of operation of the power amplifier (6, 26, 36) in response to at least one of a level of the input signal (1), a required power, a required efficiency, a desired type of modulation, or a desired degree of linearity.

5. RF transmitter according to claim 1, wherein the power amplifier (6, 26, 36) has a differential configuration.

6. RF transmitter according to claim 5, wherein the power amplifier (6, 26, 36) includes a set of cascode coupled transistors (81).

7. RF transmitter according to claim 6, wherein the cascode coupled transistors (81) are used to control an output power of the power amplifier (6, 26, 36).

8. RF transmitter according to claim 1, wherein the power amplifier (6, 26, 36) includes separated paths for amplitude modulation signals (AM+, AM-) and phase modulation signals (PM+, PM-).

9. RF transmitter according to claim 1, wherein the control circuit (4) is arranged to function as a soft limiter upon controlling the power amplifier (6, 26, 36) to operate in class AB mode.

10. RF transmitter according to claim 1, wherein the control circuit (4) is arranged to function as a hard limiter upon controlling the power amplifier (6, 26, 36) to operate in class D mode.

11. RF transmitter according to claim 1, wherein the control circuit (4) is capable of generating an amplitude modulated signal (5) to the power amplifier (6, 26,

36) to control its mode of operation.

12. RF transmitter according to claim 11, wherein the power amplifier (6, 26, 36) includes a mixer stage (Mx) with first and second inputs arranged to receive the amplitude modulated signal (AM+, AM-) at the first input and a phase modulated signal (PM+, PM-) at the second input.

13. RF transmitter according to claim 12, wherein the power amplifier (6, 26, 36) further includes an envelope pre-distorter (60) to compensate for a non-linearity of the first input of the mixer stage (Mx).

14. RF transmitter according to claim 1, including a digital processor (2) arranged to generate amplitude and phase information of the input signal (1), and wherein the phase information is applied to an amplitude modulator that applies an RF carrier signal to the input signal (1).

15. RF transmitter according to claim 14, including a sigma-delta frequency synthesizer (ΣΔ-PLL) arranged to generate the RF carrier signal.

16. An integrated circuit (10) comprising an RF transmitter according to claim 1.