WO2007146845A3 - Configurable and scalable hybrid multi-tiered caching storage system - Google Patents

Configurable and scalable hybrid multi-tiered caching storage system Download PDF

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Publication number
WO2007146845A3
WO2007146845A3 PCT/US2007/070816 US2007070816W WO2007146845A3 WO 2007146845 A3 WO2007146845 A3 WO 2007146845A3 US 2007070816 W US2007070816 W US 2007070816W WO 2007146845 A3 WO2007146845 A3 WO 2007146845A3
Authority
WO
WIPO (PCT)
Prior art keywords
configurable
storage system
memory means
tiered caching
hybrid multi
Prior art date
Application number
PCT/US2007/070816
Other languages
French (fr)
Other versions
WO2007146845A2 (en
Inventor
Rey H Bruce
Noeme P Mateo
Ricky S Nite
Original Assignee
Bitmicro Networks Inc
Rey H Bruce
Noeme P Mateo
Ricky S Nite
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/450,005 external-priority patent/US7506098B2/en
Priority claimed from US11/450,023 external-priority patent/US7613876B2/en
Application filed by Bitmicro Networks Inc, Rey H Bruce, Noeme P Mateo, Ricky S Nite filed Critical Bitmicro Networks Inc
Publication of WO2007146845A2 publication Critical patent/WO2007146845A2/en
Publication of WO2007146845A3 publication Critical patent/WO2007146845A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G06F3/0605—Improving or facilitating administration, e.g. storage management by facilitating the interaction with a user or administrator
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/068—Hybrid storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0685—Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/21—Employing a record carrier using a specific recording technology
    • G06F2212/217—Hybrid disk, e.g. using both magnetic and solid state storage devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/22—Employing cache memory using specific memory technology
    • G06F2212/225—Hybrid cache memory, e.g. having both volatile and non-volatile portions

Abstract

A hybrid storage system comprising mechanical disk drive means, flash memory means, SDRAM memory means, and SRAM memory means is described. IO processor circuits and DMA controller circuits are devised to eliminate host intervention. Multi-tiered caching system and novel data structure for mapping logical address to physical address results in a configurable and scalable high performance computer data storage solution.
PCT/US2007/070816 2006-06-08 2007-06-08 Configurable and scalable hybrid multi-tiered caching storage system WO2007146845A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/450,023 2006-06-08
US11/450,005 2006-06-08
US11/450,005 US7506098B2 (en) 2006-06-08 2006-06-08 Optimized placement policy for solid state storage devices
US11/450,023 US7613876B2 (en) 2006-06-08 2006-06-08 Hybrid multi-tiered caching storage system

Publications (2)

Publication Number Publication Date
WO2007146845A2 WO2007146845A2 (en) 2007-12-21
WO2007146845A3 true WO2007146845A3 (en) 2008-12-31

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/070816 WO2007146845A2 (en) 2006-06-08 2007-06-08 Configurable and scalable hybrid multi-tiered caching storage system

Country Status (1)

Country Link
WO (1) WO2007146845A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8433845B2 (en) 2009-04-08 2013-04-30 Google Inc. Data storage device which serializes memory device ready/busy signals
US20100262773A1 (en) 2009-04-08 2010-10-14 Google Inc. Data striping in a flash memory data storage device
WO2011044154A1 (en) * 2009-10-05 2011-04-14 Marvell Semiconductor, Inc. Data caching in non-volatile memory
US8201020B2 (en) 2009-11-12 2012-06-12 International Business Machines Corporation Method apparatus and system for a redundant and fault tolerant solid state disk
US9626126B2 (en) 2013-04-24 2017-04-18 Microsoft Technology Licensing, Llc Power saving mode hybrid drive access management
US9946495B2 (en) 2013-04-25 2018-04-17 Microsoft Technology Licensing, Llc Dirty data management for hybrid drives
KR101995623B1 (en) * 2014-01-16 2019-07-02 인텔 코포레이션 An apparatus, method, and system for a fast configuration mechanism
US10671460B2 (en) 2018-02-05 2020-06-02 Micron Technology, Inc. Memory access communications through message passing interface implemented in memory systems

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020166026A1 (en) * 2001-01-29 2002-11-07 Ulrich Thomas R. Data blocking mapping
US20040205299A1 (en) * 2003-04-14 2004-10-14 Bearden Brian S. Method of triggering read cache pre-fetch to increase host read throughput
US20050210304A1 (en) * 2003-06-26 2005-09-22 Copan Systems Method and apparatus for power-efficient high-capacity scalable storage system
US20050256976A1 (en) * 2004-05-17 2005-11-17 Oracle International Corporation Method and system for extended memory with user mode input/output operations

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020166026A1 (en) * 2001-01-29 2002-11-07 Ulrich Thomas R. Data blocking mapping
US20040205299A1 (en) * 2003-04-14 2004-10-14 Bearden Brian S. Method of triggering read cache pre-fetch to increase host read throughput
US20050210304A1 (en) * 2003-06-26 2005-09-22 Copan Systems Method and apparatus for power-efficient high-capacity scalable storage system
US20050256976A1 (en) * 2004-05-17 2005-11-17 Oracle International Corporation Method and system for extended memory with user mode input/output operations

Also Published As

Publication number Publication date
WO2007146845A2 (en) 2007-12-21

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