WO2007125744A1 - 両面電極構造の半導体装置及びその製造方法 - Google Patents

両面電極構造の半導体装置及びその製造方法 Download PDF

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Publication number
WO2007125744A1
WO2007125744A1 PCT/JP2007/057812 JP2007057812W WO2007125744A1 WO 2007125744 A1 WO2007125744 A1 WO 2007125744A1 JP 2007057812 W JP2007057812 W JP 2007057812W WO 2007125744 A1 WO2007125744 A1 WO 2007125744A1
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WIPO (PCT)
Prior art keywords
wiring
semiconductor device
double
package substrate
substrate
Prior art date
Application number
PCT/JP2007/057812
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English (en)
French (fr)
Inventor
Masamichi Ishihara
Fumihiko Ooka
Yoshihiko Ino
Original Assignee
Oki Electric Industry Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co., Ltd. filed Critical Oki Electric Industry Co., Ltd.
Priority to US12/279,402 priority Critical patent/US7884466B2/en
Priority to KR1020087023980A priority patent/KR101161572B1/ko
Priority to CN2007800151245A priority patent/CN101432870B/zh
Publication of WO2007125744A1 publication Critical patent/WO2007125744A1/ja
Priority to US12/978,877 priority patent/US20110089551A1/en

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Definitions

  • the present invention relates to a semiconductor device having a double-sided electrode structure that can be used for small electronic devices such as mobile phones and digital cameras, small robots, and small sensors, and a method for manufacturing the same.
  • Patent Document 2 in a lead frame type double-sided electrode package, the force that is vertically penetrated by the lead frame has the same electrode arrangement on the lower surface and the upper surface, and there is no flexibility in vertical connection.
  • Patent Document 3 a double-sided electrode structure is formed by providing an electrode penetrating a substrate in a BGA type double-sided electrode package.
  • the electrode arrangement on the upper surface is the through-hole itself, and the connection pattern with the upper connection IC is not flexible.
  • Patent Document 4 discloses a double-sided electrode structure by forming protruding electrodes on a substrate, but there is no specific disclosure of the protruding electrode forming method and connection method. Although the rewiring of the upper surface is also disclosed, this method only discloses the conventional method of forming a pattern using lithography by forming a low-resistance metal film on the upper surface, and this is a significant cost issue. It can be said that it has.
  • Patent Document 1 Japanese Patent Laid-Open No. 2001-127243
  • Patent Document 2 Japanese Patent Laid-Open No. 2003-249604
  • Patent Document 3 Japanese Patent Laid-Open No. 2005-235824
  • Patent Document 4 Japanese Patent Laid-Open No. 2002-158312
  • An object of the present invention is to solve such problems and to enable a thin-sided and low-cost manufacturing of a double-sided electrode package that can be arbitrarily rewired on the upper surface of a substrate and can be easily connected to the upper part. It is said.
  • a plurality of chips can be easily built in one board, and wiring can be taken out to any number of places on the top and bottom of the board, allowing flexibility in connection patterns with the upper connection IC.
  • the purpose is to have.
  • a recess is formed in a package substrate constituted by a multilayer organic substrate with multilayer wiring, and an LSI chip is accommodated in the recess.
  • the resin is injected into the periphery and top surface of the LSI chip, which is mounted in the recess of the package substrate and connected to the multilayer wiring, to the same height as the top surface of the package substrate and sealed.
  • Wiring is performed on the upper surface of the sealed resin, and this wiring is connected to the multilayer wiring on the front surface of the package substrate, and the front surface bump for external connection on the upper surface of the resin substrate.
  • a backside bump electrode for external connection to be connected to the multilayer wiring is formed on the backside of the knock board.
  • a step portion is formed in the concave portion of the cage substrate, a terminal wiring connected to the multilayer wiring is formed in the step portion, and the terminal wiring is used as a bonding wire connection electrode. It connects with the electrode formed on the upper surface of the chip.
  • a metal pad portion connected to the multilayer wiring is formed on the uppermost layer of the bottom of the recess portion of the knock substrate, and this metal pad portion is flip-chip connected to the upper surface electrode of the LSI chip arranged downward.
  • the sealing of the resin is performed on the top surface of the package substrate so that the surface of the LSI chip and the top surface of the package are flush with the periphery and top surface of the LSI chip mounted in the recess of the package substrate. This is done by pouring the grease to the same height.
  • Wiring on the upper surface of the resin is performed by an ink jet method using metal particles or screen printing. Copper particles can be used as the metal particles. In this case, reduction using atomic hydrogen is performed.
  • the method for manufacturing a semiconductor device having a double-sided electrode structure includes multilayer wiring on a multilayer organic substrate, and terminal wiring on each of the multilayer wirings across the front surface and the back surface of the substrate.
  • a recess is formed in the cage substrate constituted by connecting the two, and the LSI chip is accommodated in the recess. Fill and seal the periphery and top surface of the LSI chip that is mounted in the recess of the knock board and connected to the multilayer wiring to the same height as the top surface of the knock board.
  • a wiring to be connected to the terminal wiring on the front surface of the knock board is formed on the top surface of the resin, and a front surface bump electrode for external connection is formed at the tip of the wiring.
  • a back bump electrode for external connection connected to the terminal wiring on the back surface of the package substrate is formed.
  • wiring can be taken out at arbitrary locations above and below the substrate, and the upper surface of the substrate can be arbitrarily rewired This makes it possible to provide flexibility in the connection pattern with the upper connection IC.
  • FIG. 1 is a diagram illustrating a semiconductor device (organic substrate type double-sided electrode package) having a double-sided electrode structure according to the present invention.
  • FIG. 2 is a cross-sectional view (A) and a perspective view (B) of a package substrate.
  • FIG. 3 is a diagram for explaining an example of manufacturing a nodule / cage substrate.
  • FIG. 4 is a diagram for explaining chip die bonding for bonding an LSI chip.
  • FIG. 5 is a diagram for explaining wire bonding between a multilayer organic substrate and an LSI chip.
  • FIG. 6 is a cross-sectional view (A) and a perspective view (B) of the state where the cavity portion is sealed with grease.
  • FIG. 7 is a diagram illustrating rewiring on the mold front surface.
  • FIG. 8 is a diagram illustrating connection of bump electrodes.
  • FIG. 9 is a plan view illustrating a wiring pattern different from FIG. 1 (B).
  • FIG. 10 is a schematic cross-sectional view of a processing apparatus used as a copper wiring cleaning apparatus.
  • FIG. 1 is a diagram illustrating a semiconductor device (organic substrate type double-sided electrode package) having a double-sided electrode structure according to the present invention.
  • FIG. 1 (A) shows a state after an LSI chip is accommodated in a package substrate and wire-bonded. It is a perspective view from above showing a state, and (B) is a perspective view of an upward force shown in a state where rewiring is performed after sealing with a resin, and further, bumps for external connection are formed and completed. .
  • a knocker substrate composed of a multilayer organic substrate with multilayer wiring is formed with a recess for partially storing an LSI chip and a step portion around the recess.
  • the wiring layer of the multilayer organic substrate is provided on the same surface as the bottom surface of the recess and the stepped portion, in addition to the back surface side and the front surface side.
  • the wiring layer on the front side is indicated as terminal wiring.
  • the terminal wiring is also provided on the back surface side of the multilayer organic substrate, the bottom surface of the recess (for flip chip connection), and the step portion (for wire bonding).
  • the metal pad part (terminal wiring) on the upper surface of the stepped part connected to the wiring layer of the multilayer organic substrate is connected to the electrode formed on the upper surface of the LSI chip by the Au wire as a bonding wire connection electrode.
  • the LSI chip may be flip-chip connected to the uppermost metal pad portion (terminal wiring) at the bottom of the concave portion of the upper surface electrode arranged downward.
  • the wiring layer at the bottom of the recess is not necessarily required, but even if there is a wiring in the die bond part, an insulating layer is applied on it or an insulating die bond material is used. Therefore, there is no problem in die bonding.
  • sealing is performed with epoxy resin to protect it from external force stress and contamination.
  • This resin sealing is performed so that the resin sealing surface and the upper surface of the package are flat (coplanar) around the LSI chip mounted in the recess of the multilayer organic substrate and the upper surface (cavity portion). This is done by injecting the resin to the same height as the top surface of the package substrate.
  • wiring is performed on the mold front surface to connect to the terminal wiring formed on the top surface of the knock board (rewiring).
  • the wiring that extends on the top surface of the knocking board is extended to the resin surface by inkjet printing or screen printing using metal nanoparticles (especially copper nanoparticles).
  • a bump electrode (connection protrusion) is formed as an external connection terminal at the tip of the wiring extending to the resin surface.
  • This van The positive electrode is also formed on the back surface not only on the front surface.
  • the rewiring is extended in the package substrate without extending to the resin surface for the purpose of equalizing the arrangement of the knock electrodes. Can also be formed. Furthermore, in order to maintain the upper and lower connection strength, an extra bump electrode that is not connected anywhere can be provided.
  • FIG. 2 is a cross-sectional view (A) and a perspective view (B) of the package substrate.
  • the knock substrate is composed of a multilayer organic substrate with multilayer wiring, and partially forms a recess for accommodating the LSI chip and a step portion around the recess.
  • the multilayer organic substrate has a low electrical resistance because the circuit is formed of pure metal (copper) conductor, and the dielectric constant is low because of the insulating layer formed of organic resin. It has the characteristics such as excellent.
  • the wiring layer (including the terminal wiring) of the multilayer organic substrate is provided on the same surface as the bottom surface of the recess and the stepped portion in addition to the back surface and the front surface.
  • the terminal wiring in Fig. 2 (B) shows the front side wiring layer.
  • the stepped portion provided with the terminal wiring for wiring connection with the LSI chip does not necessarily have to be provided on all four sides, which is exemplified as being provided on all four sides of the rectangular recess.
  • the recess forming side for housing the semiconductor chip is referred to as the front surface, and the opposite side is referred to as the back surface.
  • the multilayer organic substrate is a substrate in which a wiring pattern is formed in each layer of a substrate composed of a plurality of layers, and via holes for connecting the wiring patterns of the respective layers are formed as necessary.
  • a conductor layer is formed inside the via hole, and this conductor layer is connected to a land which is an end face electrode portion formed on the lower surface side. Furthermore, solder material is attached to this land to form bump electrodes for external connection.
  • FIG. 3A copper foils for forming metal conductors are formed on both upper and lower surfaces of an organic resin insulating layer (substrate) formed of glass epoxy.
  • This copper foil can be formed by, for example, a chemical plating method.
  • FIG. 3B a hole (via hole) is selectively drilled using a laser to make a three-dimensional connection of insulating layers, that is, the upper and lower portions formed in the subsequent step (D). A via part that connects the wiring patterns on both sides is formed.
  • the via hole is filled with copper plating.
  • wiring patterns are formed on the upper and lower copper foils. This is formed, for example, by applying a photoresist to the copper foil on the insulating layer, transferring the pattern by mask exposure, developing, etching, removing the resist, and the like.
  • a hole (via hole) to be a via portion is further drilled with a laser in two newly formed organic resin insulating layers (glass epoxy). .
  • the via hole is filled with copper plating. Then, a wiring pattern is formed on the upper and lower copper foils.
  • an LSI chip is bonded (chip die bonding).
  • the LSI chip is bonded to the bottom of the recess formed in the multilayer organic substrate with an insulating die bond material.
  • Power that illustrates one LSI chip As will be described later with reference to FIG. 9B, it is possible to incorporate a plurality of chips.
  • the multilayer organic substrate and the LSI chip are wire-bonded.
  • a metal pad portion (terminal wiring) is formed on the upper surface of the stepped portion of the concave side wall portion of the multilayer organic substrate, and this metal pad portion is connected to the multilayer wiring layer.
  • the metal pad portion that becomes the bonding wire connection electrode and the electrode formed on the upper surface of the LSI chip are connected by an Au wire. This state after wire bonding also corresponds to that described above with reference to FIG.
  • a flip chip connection can be made to the uppermost metal pad portion at the bottom of the recess by anisotropic conductive resin bonding or the like.
  • chip die bond and electrode connection are formed simultaneously.
  • the LSI surface should be facing downward.
  • the upper surface electrode of the downward LSI chip is connected through a wiring pattern including the uppermost metal pad portion at the bottom of the concave portion of the multilayer organic substrate.
  • the stepped portion of the knock board and the wiring layer provided on the stepped portion are not necessarily required.
  • FIG. 6 is a cross-sectional view (A) and a perspective view (B) of the state where the cavity portion is sealed with grease.
  • the resin sealing surface and the upper surface of the package are flat (on the same plane) around the LSI chip mounted in the recess of the multilayer organic substrate. This is done by injecting (molding) the resin up to the same height as the top surface.
  • wiring is connected to the metal pad portion (terminal wiring) formed on the top surface of the knock board. Is performed (rewiring).
  • the wiring that extends the force on the upper surface of the cage is extended to the resin surface by ink jet method using metal nanoparticles (especially copper nanoparticles) or screen printing.
  • the nano copper metal particles contained in the organic solvent draw a desired pattern by an ink jet method that is practically used in a printer, and then heat treatment is performed to evaporate the organic solvent.
  • circuit paste is formed by applying nano paste containing nano copper metal particles in an organic solvent on a substrate by screen printing method, followed by heating and baking.
  • FIG. 8 is a diagram showing a state in which bump electrodes are connected.
  • Bump electrodes connection protrusions
  • This bump electrode is formed not only on the front side but also on the back side.
  • the bump electrode on the front surface can be formed by applying a solder resist after rewiring (forming an insulating film) and then opening the bump part at that position. With the above process, the manufacture as an organic substrate type double-sided electrode package is completed.
  • FIGS. 9 (A) and 9 (B) are plan views illustrating wiring patterns different from those in FIG. 1 (B).
  • the Fig. 9 (A) shows an example in which one LSI chip is accommodated in one package substrate
  • Fig. 9 (B) shows an example in which two LSI chips are accommodated in one package substrate. Is shown.
  • the manufacture of only one double-sided electrode package has been described as an example. However, in actuality, a large number of the double-sided electrode packages are manufactured in a state where they are connected vertically and horizontally, and as shown in FIG. After the process, the double-sided electrode package is cut for singulation.
  • Copper wiring is formed by an inkjet method.
  • Nano copper metal particles are contained in an organic solvent, and a desired pattern is drawn by an ink jet method that is practically used in a printer. Thereafter, heat treatment is performed by evaporating the organic solvent.
  • the present invention removes dirt and oxides from the organic solvent from the copper wiring formed in this way.
  • heat treatment for evaporating the organic solvent is performed, copper oxide is formed by surface oxidation of copper, which can also be removed by subsequent atomic hydrogen treatment.
  • this invention is applicable also when not performing the heat processing which evaporates an organic solvent.
  • the heat treatment is not performed, the organic solvent is contained, but the organic solvent can be removed by an atomic hydrogen treatment performed later.
  • FIG. 10 is a schematic cross-sectional view of a processing apparatus used as a copper wiring cleaning apparatus. From the gas inlet on the upper surface of the reaction chamber, a raw material containing hydrogen such as hydrogen, ammonia, hydrazine or the like is fed as a raw material for atomic hydrogen or ammonia decomposition species through a cleaning gas supply mechanism.
  • a raw material containing hydrogen such as hydrogen, ammonia, hydrazine or the like is fed as a raw material for atomic hydrogen or ammonia decomposition species through a cleaning gas supply mechanism.
  • a substrate heating mechanism such as a heater is installed immediately below the reaction chamber, and the sample (substrate) force is placed on the sample stage in the reaction chamber immediately above the heating mechanism with the deposition surface facing upward.
  • tungsten A catalyst body made of wire is installed, and the catalyst body is heated to a high temperature by a catalyst body heating mechanism to decompose the gas that flows in.
  • atomic hydrogen or ammonia decomposing species are generated by a catalytic decomposition reaction with a heated catalyst.
  • Copper interconnect oxides are removed by atomic hydrogen reduction, and organic contaminants can be removed by the formation of hydrocarbons by the reaction of atomic hydrogen and carbon.
  • a compound containing nitrogen which is a raw material of atomic hydrogen or ammonia decomposition species
  • a compound containing nitrogen for example, ammonia or hydrazine
  • atomic nitrogen is generated simultaneously with atomic hydrogen by bringing the compound gas into contact with a heated catalyst body, and the metal surface oxide film is reduced by atomic hydrogen and / or organic substances are removed.
  • the metal surface can be nitrided with atomic nitrogen.
  • the catalyst material in addition to the above-mentioned tungsten, tantalum, molybdenum, vanadium, rhenium, platinum, thorium, zirconium, yttrium, hafnium, palladium, iridium, ruthenium, iron, nickel, chromium, aluminum,
  • One material of silicon or carbon, single oxide of these materials, single nitride of these materials, single carbide of these materials (excluding carbon) these material forces Two or more selected forces Mixed crystals or compound oxides, or two or more of these selected material strengths or mixed crystals or compound nitrides or any of these material (excluding carbon) forces selected Any one of powerful mixed crystals or compound carbides can be used.
  • the temperature of the catalyst body is, for example, a temperature range of 1000 ° C. to 2200 ° C. in the case of a tungsten catalyst body.
  • the raw material supply mechanism in FIG. 10 is for supplying, for example, hexamethyldisilazane silane used for depositing a SiN-based film, if necessary.
  • the vacuum system is for exhausting residual reaction gas.

Abstract

　本発明は、多層配線した多層有機基板により構成されるパッケージ基板に凹部を形成して、該凹部内にＬＳＩチップを収納する。この多層配線と接続したＬＳＩチップを封止した樹脂の上面に配線し、かつ、この配線を、パッケージ基板のおもて面において多層配線に接続された端子用配線、及び樹脂上面の外部接続用のおもて面バンプ電極と接続する。パッケージ基板の裏面側において、多層配線と接続される外部接続用の裏面バンプ電極を形成する。

Description

明 細 書
両面電極構造の半導体装置及びその製造方法
技術分野
[0001] 本発明は、携帯電話、デジカメ等の小型電子機器や小型ロボット、小型センサに用 いることのできる両面電極構造の半導体装置及びその製造方法に関する。
背景技術
[0002] LSIチップの高集積ィ匕に伴い、ノ ッケージサイズの縮小化も強く要求されており、 様々な実装パッケージ構造が提案されている。近年、半導体ベアチップに貫通電極 を形成して積層しょうとする開発が盛んに行われている。一方、リアルサイズの両面 電極パッケージもこれから製品化される可能性が高い。いずれの技術においても、従 来の両面電極パッケージは貫通電極構造を必要としているが（特許文献 1参照）、現 在の貫通孔の絶縁方法は、高温で処理されるため半導体の実装プロセスへの適用 は困難であった。このように、半導体基板への貫通孔の形成とその絶縁方法にはま だ課題が残されて ヽて、貫通電極を必要とせずに配線することが望まれる。
[0003] 特許文献 2は、リードフレーム型の両面電極パッケージにおいて、リードフレームで 上下に貫通させている力 下面と上面の電極配置は同じであり、上下接続の融通性 は無い。
[0004] 特許文献 3は、 BGAタイプの両面電極パッケージにお 、て、基板を貫通する電極を 設けて両面電極構造を形成して!/、る。しかし上面の電極配置部は貫通部そのもので あり、上部接続 ICとの接続パターンに融通性がない。
[0005] 特許文献 4は基板上に突起電極を形成して両面電極構造を開示しているが、その 突起電極形成方法や接続方法などの具体的な開示は全く無 、。また上面の再配線 も開示しているが、この手法は上面メツキで低抵抗金属膜を形成してリソグラフィーを 用いてパターン形成する従来手法のみの開示に留まっており、コスト的には大きな課 題を持っていると言える。
特許文献 1 :特開 2001—127243号公報
特許文献 2：特開 2003 - 249604号公報 特許文献 3：特開 2005 - 235824号公報
特許文献 4：特開 2002— 158312号公報
発明の開示
発明が解決しょうとする課題
[0006] 本発明は、係る問題点を解決して、基板上面を任意に再配線可能にして、上部 との接続を容易にした両面電極パッケージを薄くかつ低コストで製造可能にすること を目的としている。
[0007] また、本発明は、 1つの基板に複数チップを簡単に内蔵できるだけでなぐ任意の 数だけ基板上部及び下部の任意の箇所に配線を取り出して、上部接続 ICとの接続 パターンに融通性を持たせることを目的としている。
課題を解決するための手段
[0008] 本発明の両面電極構造の半導体装置は、多層配線した多層有機基板により構成 されるパッケージ基板に凹部を形成して、該凹部内に LSIチップを収納する。パッケ ージ基板の凹部内に装着して多層配線と接続した LSIチップの周囲及び上面に、パ ッケージ基板の最上面と同じ高さにまで榭脂を注入して封止する。この封止した榭脂 の上面に配線し、かつ、この配線を、パッケージ基板のおもて面において多層配線 に接続された端子用配線、及び榭脂上面の外部接続用のおもて面バンプ電極と接 続する。ノ ッケージ基板の裏面側において、多層配線と接続される外部接続用の裏 面バンプ電極を形成する。
[0009] ノ^ケージ基板の凹部には、段差部を形成して、この段差部に前記多層配線に接 続される端子用配線を形成し、該端子用配線をボンディングワイヤ接続電極として、 LSIチップの上面に形成されている電極と接続する。ノ ッケージ基板の凹部底部の 最上層に、多層配線に接続される金属パッド部を形成し、この金属パッド部を下向き 配置した LSIチップの上面電極とフリップチップ接続する。榭脂の封止は、パッケ一 ジ基板の凹部内に装着した LSIチップの周囲及び上面に、該榭脂封止面とパッケ一 ジ上面が同一平面になるように、パッケージ基板の最上面と同じ高さにまで榭脂を注 入することにより行われる。榭脂上面の配線は、金属粒子を用いたインクジェット方式 或いはスクリーン印刷により行われる。金属粒子として、銅粒子を用いることができ、こ の場合、原子状水素を用いた還元が実施される。
[0010] また、本発明の両面電極構造の半導体装置の製造方法は、多層有機基板に多層 配線すると共に、該基板のおもて面及び裏面にぉ ヽて前記多層配線にそれぞれ端 子用配線を接続することにより構成されるノ^ケージ基板に凹部を形成して、該凹部 内に LSIチップを収納する。ノ ッケージ基板の凹部内に装着して多層配線と接続し た LSIチップの周囲及び上面に、ノ ッケージ基板の最上面と同じ高さにまで榭脂を 注入して封止する。ノ ッケージ基板のおもて面の端子用配線と接続する配線を、榭 脂の上面に形成し、かつ、この配線の先端に、外部接続用のおもて面バンプ電極を 形成する。パッケージ基板の裏面の端子用配線と接続される外部接続用の裏面バン プ電極を形成する。
発明の効果
[0011] 本発明によれば、側面配線でもなく内部接続でもなぐノ¾ケージ基板を工夫して 容易に高密度の両面電極パッケージを、薄くかつ低コストで製造することができる。
[0012] また、本発明によれば、 1つの基板に複数チップを簡単に内蔵できるだけでなぐ任 意の数だけ基板上部及び下部の任意の箇所に配線を取り出して、基板上面を任意 に再配線可能にし、上部接続 ICとの接続パターンに融通性を持たせることができる。 図面の簡単な説明
[0013] [図 1]本発明の両面電極構造の半導体装置 (有機基板型両面電極パッケージ)を例 示する図である。
[図 2]パッケージ基板の断面図 (A)、及び斜視図（B)である。
[図 3]ノ¾ /ケージ基板の製造の一例を説明する図である。
[図 4]LSIチップを接着するチップダイボンドを説明する図である。
[図 5]多層有機基板と LSIチップのワイヤボンドを説明する図である。
[図 6]キヤビティ部を榭脂で封止した状態の断面図 (A)及び斜視図 (B)である。
[図 7]モールドおもて面における再配線を説明する図である。
[図 8]バンプ電極の接続を説明する図である。
[図 9]図 1 (B)とは異なる配線パターンを例示する平面図である。
[図 10]銅配線洗浄装置として用いた処理装置の断面の概略図である。 発明を実施するための最良の形態
[0014] 以下、例示に基づき、本発明を説明する。図 1は、本発明の両面電極構造の半導 体装置 (有機基板型両面電極パッケージ)を例示する図であり、（A)は、パッケージ 基板内に LSIチップを収容してワイヤボンドした後の状態を示す上方からの斜視図で あり、（B)は、榭脂封止後再配線し、さらに、外部接続用のバンプを形成して完成さ せた状態で示す上方力 の斜視図である。
[0015] 多層配線した多層有機基板により構成されるノ ッケージ基板は、図 1 (A)に示すよ うに、部分的に LSIチップを収納するための凹部、及び凹部周囲に段差部を形成し ている。多層有機基板の配線層は、裏面側及びおもて面側に加えて、凹部底面及 び段差部とそれぞれ同一面に備えている。図中、おもて面側の配線層を、端子用配 線と表示している。同様に、端子用配線は、多層有機基板の裏面側、凹部底面 (フリ ップチップ接続用）、及び段差部 (ワイヤボンド用）にも設けられて 、る。多層有機基 板の配線層に接続されている段差部上面の金属パッド部 (端子用配線）は、ボンディ ングワイヤ接続電極として、 LSIチップの上面に形成されている電極と Auワイヤーに より接続される。あるいは、 LSIチップは、その下向き配置した上面電極を、凹部底部 の最上層の金属パッド部 (端子用配線）とフリップチップ接続してもよい。なお、ワイヤ ボンド接続の場合、凹部底部の配線層は必ずしも必要としないが、ダイボンド部に配 線があっても、その上に絶縁層を塗布したり、あるいは絶縁性のダイボンド材を使うこ とにより、ダイボンドに支障は無い。
[0016] 図 1 (B)に示すように、ワイヤボンド後、外界力 の応力、汚染から守るために、ェポ キシ榭脂により封止される。この榭脂封止は、多層有機基板の凹部内に装着した LS Iチップの周囲及び上面 (キヤビティ部）に、該榭脂封止面とパッケージ上面がフラット (同一平面）になるように、ノ ッケージ基板の最上面と同じ高さにまで榭脂を注入する ことにより行われる。その後、モールドおもて面において、ノ ッケージ基板の最上面に 形成されて ヽる端子用配線にまで接続する配線が行われる（再配線)。 ノ ッケージ基 板上面力 延びるこの配線は、金属ナノ粒子 (特に銅ナノ粒子）を用いたインクジェッ ト方式或いはスクリーン印刷により、榭脂面まで延長される。この榭脂面まで延長した 配線の先端に外部接続用端子としてのバンプ電極 (接続突起)を形成する。このバン プ電極は、おもて面だけでなぐ裏面にも形成する。なお、図 1 (B)に示すように、ノ ンプ電極配置を等間隔にする目的で、再配線を榭脂面まで延長することなぐパッケ ージ基板内で延長し、その延長端にバンプ電極を形成することもできる。さらに、上 下接続強度保持のために、どこにも接続されな 、余分なバンプ電極を設けることもで きる。
[0017] 次に、上述した両面電極構造の半導体装置 (有機基板型両面電極パッケージ)の 製造工程の詳細を、図 2〜図 8を参照してさらに説明する。まず、本発明の半導体装 置に用いられるノ ッケージ基板について説明する。図 2は、パッケージ基板の断面図 (A)、及び斜視図（B)である。ノ ッケージ基板は、多層配線した多層有機基板により 構成され、部分的に LSIチップを収納するための凹部と、この凹部周囲の段差部を 形成している。多層有機基板は、純粋な金属 (銅)導体にて回路が形成されているた め電気抵抗が小さぐまた有機榭脂にて絶縁層が形成されているため誘電率が小さ ぐ且つ軽量ィ匕に優れているなどの特徴を有している。多層有機基板の配線層（端 子用配線を含む）は、裏面側及びおもて面側に加えて、凹部底面及び段差部とそれ ぞれ同一面に備えている。図 2 (B)の端子用配線は、おもて面側配線層を示している 。 LSIチップと配線接続するための端子用配線を設けた段差部は、矩形凹部の内周 4辺の全てに備えるものとして例示している力 必ずしも 4辺全てに設ける必要はない 。なお、図示の有機基板型両面電極パッケージにおいて、半導体チップを収容する 凹部形成側をおもて面、その反対側を裏面と称して!/ヽる。
[0018] 多層有機基板は、複数層から成る基板の各層に、それぞれ配線パターンを形成し 、必要に応じて各層の配線パターンを接続するためのビアホールを形成したもので ある。このビアホールの内部には導体層が形成され、この導体層が下面側に形成さ れた端面電極部であるランドと接続されている。さら〖こ、このランドには、ハンダ材料を 付着させて、外部接続用のバンプ電極を形成する。
[0019] 次に、上述したパッケージ基板の製造の一例を、図 3を参照して説明する。まず、 図 3 (A)にお 、て、ガラスエポキシにより形成した有機榭脂絶縁層（基板)の上下両 面に、金属導体を形成する銅箔が成膜される。この銅箔は、例えば、化学めつき法に て形成できる。 [0020] 図 3 (B)において、レーザを用いて選択的に孔（ビアホール）開け加工を行なって、 絶縁層の 3次元接続を行うべき部分、即ち後の工程 (D)で形成される上下両面の配 線パターンを相互に接続するビア部を形成する。
[0021] 図 3 (C)において、ビアホール内の残渣除去（デスミア）をした後、ビアホール内を 銅メツキにより充填する。
[0022] 図 3 (D)にお 、て、上下両面の銅箔に対して、配線パターンを形成する。これは、 例えば、絶縁層上の銅箔に対して、ホトレジストを塗布しマスク露光でパターンを転 写し、現像、エッチング、レジスト除去等の工程を経て形成される。
[0023] 図 3 (E)にお ヽて、上下それぞれに、有機榭脂絶縁層（ガラスエポキシ)をラミネート
(層状加工)し、さら〖こ、それぞれの上に銅箔を形成する。
[0024] 図 3 (F)にお ヽて、新たに形成した有機榭脂絶縁層（ガラスエポキシ)の 2層に対し て、さらにビア部となる孔 (ビアホール）開けを、レーザを用いて行う。
[0025] 図 3 (G)において、ビアホール内の残渣除去（デスミア）をした後、ビアホール内を 銅メツキにより充填する。そして、上下 2層の銅箔に対して、配線パターンを形成して
、 4層（配線層）基板を完成する。
[0026] 次に、図 4に示すように、 LSIチップを接着する（チップダイボンド)。 LSIチップは、 多層有機基板に形成された凹部底面に絶縁性のダイボンド材により接着される。 1個 の LSIチップを例示した力 図 9 (B)を参照して後述するように、複数のチップを内蔵 することも可會である。
[0027] 次に、図 5に示すように、多層有機基板と LSIチップをワイヤボンドする。多層有機 基板の凹部側壁部の段差部上面に金属パッド部 (端子用配線)が形成されており、こ の金属パッド部は、多層配線層に接続されている。このボンディングワイヤ接続電極 となる金属パッド部と、 LSIチップの上面に形成されている電極が Auワイヤーにより 接続される。このワイヤボンド後の状態は、また、図 1 (A)を参照して前述したものに 相当する。
[0028] 或いは、異方性導電性榭脂接着等により、凹部底部の最上層の金属パッド部と、フ リップチップ接続することもできる。フリップチップ接続の場合はチップダイボンドと電 極接続が同時に形成される。フリップチップ接続の場合は LSI形成面を下向きにして 接続することにより、下向き LSIチップの上面電極は、多層有機基板の凹部底部の最 上層の金属パッド部を含む配線パターンを通して接続される。なお、フリップチップ接 続の場合、ノ ッケージ基板の段差部、及びこの段差部に設ける配線層は、必ずしも 必要ではない。
[0029] 図 6は、キヤビティ部を榭脂で封止した状態の断面図 (A)及び斜視図（B)である。
ワイヤボンド後、外界力 の応力、汚染から守るために、エポキシ榭脂により封止され る。この榭脂封止は、多層有機基板の凹部内に装着した LSIチップの周囲及び上面 (キヤビティ部）に、該榭脂封止面とパッケージ上面がフラット（同一平面）になるように 、 ノッケージ基板の最上面と同じ高さにまで榭脂を注入 (モールド)することにより行 われる。
[0030] 次に、図 7に示すように、榭脂を注入したモールドおもて面において、ノ ッケージ基 板の最上面に形成されている金属パッド部 (端子用配線）にまで接続する配線が行 われる（再配線)。ノ ッケージ上面力も延びるこの配線は、金属ナノ粒子 (特に銅ナノ 粒子）を用いたインクジェット方式或いはスクリーン印刷により、榭脂面まで延長される 。有機溶媒中に含有させたナノ銅金属粒子を、プリンターで実用されているインクジ エツト法で所望のパターンを描いた後、有機溶剤を蒸発させる熱処理を行う。或いは 、スクリーン印刷法の場合は、有機溶媒中にナノ銅金属粒子を含有させたナノペース トを、基板上にスクリーン印刷法で塗布した後、加熱焼成することにより、回路配線を 形成する。上面の配線を銅ナノ粒子で施した場合は、原子状水素を用いた還元を実 施して、銅配線の有機溶媒による汚れや酸化物を除去するが、この詳細は後述する
[0031] 図 8は、バンプ電極を接続した状態で示す図である。上述の榭脂面まで延長した配 線の先端に外部接続用端子としてのバンプ電極 (接続突起)を形成する。このバンプ 電極は、おもて面だけでなぐ裏面にも形成する。おもて面のバンプ電極の形成は、 再配線後にソルダーレジストを塗布 (絶縁膜形成）し、その後、バンプ部を開口して、 その位置に形成することもできる。以上の工程によって、有機基板型両面電極パッケ ージとしての製造は完成する。
[0032] 図 9 (A) (B)は、それぞれ、図 1 (B)とは異なる配線パターンを例示する平面図であ る。図 9 (A)は、 1つのパッケージ基板内に 1個の LSIチップを収容した例を示し、ま た、図 9 (B)は、 1つのパッケージ基板内に 2個の LSIチップを収容した例を示してい る。
[0033] 以上、 1個のみの両面電極パッケージの製造を例示して説明したが、実際には、多 数個が縦横に接続された状態で製造され、図 8に示すように表裏バンプ電極形成ェ 程後に、両面電極パッケージは個片化するために切断される。
[0034] 上述したように、上面の配線が銅ナノ粒子で施した場合は、原子状水素を用いた還 元を実施して、銅配線の有機溶媒による汚れや酸ィ匕物を室温以上 200°C以下の低 温で除去するが、以下、これについて、説明する。
[0035] (1)インクジェット法で銅配線を形成する。
[0036] 有機溶媒中にナノ銅金属粒子が含有されており、それをプリンターで実用されてい るインクジェット法で所望のノターンを描く。その後、有機溶剤を蒸発させた熱処理が 行われる。
[0037] 本発明は、このように形成された銅配線に対して、有機溶媒による汚れや酸化物を 除去する。有機溶剤を蒸発させる熱処理を行った場合、銅の表面酸化によって酸ィ匕 銅が形成されてしまうが、これも後の原子状水素処理によって除去ができる。或いは 、本発明は、有機溶剤を蒸発させる熱処理を行わない場合にも適用できる。熱処理 を行わない場合は、有機溶剤を含有した状態になるが、後に行う原子状水素処理に よって有機溶媒の除去も可能となる。
[0038] (2)次に、銅配線洗浄装置中で原子状水素もしくはアンモニア分解種で銅酸ィ匕物お よび有機溶媒汚染物を除去する。
[0039] 図 10は、銅配線洗浄装置として用いた処理装置の断面の概略図である。反応室の 上面のガス流入口からは、原子状水素もしくはアンモニア分解種の原料として、水素 、アンモニア、ヒドラジン等の水素を含んだ原料を、クリーニングガス供給機構を通し て送り込む。
[0040] 反応室外の直下部にはヒータ等の基板加熱機構を設置し、この加熱機構直上の反 応室内の試料ステージ上に、試料 (基板）力 被着面を上に向けて設置される。ガス 流入口からのガスを拡散させるシャワーヘッドと、試料の中間に、例えばタングステン 線からなる触媒体を設置し、該触媒体を触媒体加熱機構により高温に加熱して流入 したガスを分解する。これによつて、原子状水素もしくはアンモニア分解種が、加熱触 媒による接触分解反応により生成される。銅配線の酸化物は原子状水素の還元によ り取り除かれ、有機汚染物は原子状水素と炭素の反応により炭化水素が形成される ことで除去できる。
[0041] 原子状水素もしくはアンモニア分解種の原料である上述の水素を含む化合物とし て、窒素も含む化合物、例えば、アンモニア、ヒドラジンを用いることができる。この場 合、該化合物気体を加熱された触媒体に接触させることにより原子状水素と同時に 原子状窒素が発生し、原子状水素による金属表面酸化膜の還元、及び又は、有機 物の除去とともに、原子状窒素により金属表面の窒化処理を行うことができる。
[0042] 触媒体材料としては、上述のタングステン以外にも、タンタル、モリブデン、バナジゥ ム、レニウム、白金、トリウム、ジルコニウム、イットリウム、ハフニウム、パラジウム、イリ ジゥム、ルテニウム、鉄、ニッケル、クロム、アルミニウム、シリコン、炭素のいずれか 1 つの材料、これら材料の単体の酸化物、これら材料の単体の窒化物、これら材料 (炭 素を除く）の単体の炭化物、これらの材料力 選択された 2種類以上力 なる混晶ま たは化合物の酸ィ匕物、これらの材料力も選択された 2種類以上力もなる混晶または 化合物の窒化物、又は、これらの材料 (炭素を除く）力も選択された 2種類以上力もな る混晶または化合物の炭化物の何れか 1つを用いることができる。また、触媒体の温 度は、例えば、タングステン触媒体の場合は、 1000°Cから 2200°Cの温度範囲が適当 である。
[0043] なお、図 10中の原料供給機構は、必要に応じて、例えば、 SiN系膜を堆積するため に用いられるへキサメチルジシラザンゃシラン等を供給するためのものである。また、 真空系は、反応残余ガスを排出するためのものである。
[0044] このような銅配線洗浄装置を用いて、試料 (基板)として、ナノ銅金属粒子を用いた ノターニング配線を形成したウェハ (複数個のノ ッケージを縦横に接続した状態）、 或いは個片化したパッケージ基板を、試料ステージに設置する。そして、ナノ銅金属 粒子を用いた配線による汚染を除去するため、水素ガスを流量 30sccmで 10分間流 入し、この処理により、汚染の除去を行う。

Claims

請求の範囲
[1] 多層配線した多層有機基板により構成されるノ^ケージ基板に凹部を形成して、該 凹部内に LSIチップを収納し、
前記パッケージ基板の凹部内に装着して前記多層配線と接続した LSIチップの周 囲及び上面に、パッケージ基板の最上面と同じ高さにまで榭脂を注入して封止し、 この封止した榭脂の上面に配線し、かつ、この配線を、前記パッケージ基板のおも て面にお 1ヽて前記多層配線に接続された端子用配線、及び榭脂上面の外部接続用 のおもて面バンプ電極と接続し、
前記パッケージ基板の裏面側にぉ 、て、前記多層配線と接続される外部接続用の 裏面バンプ電極を形成した、
ことから成る両面電極構造の半導体装置。
[2] 前記パッケージ基板の凹部には、段差部を形成して、この段差部に前記多層配線に 接続される端子用配線を形成し、該端子用配線をボンディングワイヤ接続電極として 、 LSIチップの上面に形成されて ヽる電極と接続した請求項 1に記載の両面電極構 造の半導体装置。
[3] 前記パッケージ基板の凹部底部の最上層に、前記多層配線に接続される金属パッド 部を形成し、この金属パッド部を下向き配置した LSIチップの上面電極とフリップチッ プ接続した請求項 1に記載の両面電極構造の半導体装置。
[4] 前記榭脂上面の配線は、有機溶媒中に含有させた金属粒子を用いたインクジェット 方式或いはスクリーン印刷により行われる請求項 1に記載の両面電極構造の半導体 装置。
[5] 前記金属粒子は、銅粒子であり、かつ、原子状水素を用いた還元が実施される請求 項 4に記載の両面電極構造の半導体装置。
[6] 多層有機基板に多層配線すると共に、該基板のおもて面及び裏面において前記多 層配線にそれぞれ端子用配線を接続することにより構成されるノ ッケージ基板に凹 部を形成して、該凹部内に LSIチップを収納し、
前記パッケージ基板の凹部内に装着して前記多層配線と接続した LSIチップの周 囲及び上面に、パッケージ基板の最上面と同じ高さにまで榭脂を注入して封止し、 前記パッケージ基板のおもて面の端子用配線と接続する配線を前記樹脂の上面 に形成し、かつ、この配線の先端に、外部接続用のおもて面バンプ電極を形成し、 前記パッケージ基板の裏面の前記端子用配線と接続される外部接続用の裏面バ ンプ電極を形成した、
ことから成る両面電極構造の半導体装置の製造方法。
[7] 前記パッケージ基板の凹部には、段差部を形成して、この段差部に前記多層配線に 接続される端子用配線を形成し、該端子用配線をボンディングワイヤ接続電極として 、 LSIチップの上面に形成されて ヽる電極と接続した請求項 6に記載の両面電極構 造の半導体装置の製造方法。
[8] 前記パッケージ基板の凹部底部の最上層に、前記多層配線に接続される金属パッド 部を形成し、この金属パッド部を下向き配置した LSIチップの上面電極とフリップチッ プ接続した請求項 6に記載の両面電極構造の半導体装置の製造方法。
[9] 前記榭脂上面の配線は、有機溶媒中に含有させた金属粒子を用いたインクジェット 方式或いはスクリーン印刷により行われる請求項 6に記載の両面電極構造の半導体 装置の製造方法。
[10] 前記金属粒子は、銅粒子であり、かつ、原子状水素を用いた還元が実施される請求 項 9に記載の両面電極構造の半導体装置の製造方法。
PCT/JP2007/057812 2006-04-25 2007-04-09 両面電極構造の半導体装置及びその製造方法 WO2007125744A1 (ja)

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