WO2007114559A1 - Self-aligned flash memory cell and method of manufacturing the same - Google Patents

Self-aligned flash memory cell and method of manufacturing the same Download PDF

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Publication number
WO2007114559A1
WO2007114559A1 PCT/KR2007/000488 KR2007000488W WO2007114559A1 WO 2007114559 A1 WO2007114559 A1 WO 2007114559A1 KR 2007000488 W KR2007000488 W KR 2007000488W WO 2007114559 A1 WO2007114559 A1 WO 2007114559A1
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Prior art keywords
layer
flash memory
substrate
memory cell
silicon nitride
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PCT/KR2007/000488
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French (fr)
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Han Heung Kim
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Excel Semiconductor Inc,
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Publication of WO2007114559A1 publication Critical patent/WO2007114559A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a flash memory device and a method of forming the same, and more particularly, to a structure of a self-aligned flash memory cell and a method of forming the same.
  • a non- volatile memory is a memory that can retain stored information even when the power is turned off.
  • the non- volatile memory there is a flash memory. Since data stored therein can be electrically erased and reprogrammed, the flash memory is used in various devices. According to a cell array structure, the flash memory is classified into a NOR-type flash memory which offers high speed random access and an NAND-type flash memory which offers fast programming and erasing speed and can be integrated.
  • a cell transistor of the flash memory has a structure further including a floating gate in addition to a conventional metal oxide semiconductor (MOS) transistor.
  • MOS metal oxide semiconductor
  • a tunnel oxide layer is formed on a semiconductor substrate and a floating gate is formed on the tunnel oxide layer.
  • a gate interlayer dielectric layer is formed on the floating gate and a control gate electrode is formed on the gate interlayer dielectric layer.
  • FN Fowler-Nordheim
  • FN tunneling method electrons are injected from the semiconductor substrate into the floating gate by a high electric field applied to the tunnel oxide layer so as to perform the writing operation.
  • hot electrons generated at a channel region in and around a drain are injected into the floating gate so as to perform the writing operation.
  • electrons stored in the floating gate are extracted by FN tunneling in a direction of a source or of the semiconductor substrate.
  • the first method there are problems in that, overhead of a device for generating the high voltage increases, and periphery circuits that can stand the high voltage have to be constructed. Therefore, the method does not follow the current trend that a driving voltage is lowered.
  • a coupling ratio representing that what ratio is used to allocate the voltage to the floating gate becomes an issue.
  • the coupling ratio depends on an electrostatic capacity between the control gate and the floating gate and an electrostatic capacity between the channel portion of the substrate and the floating gate. For example, in order to effectively perform the electron injection, the coupling ratio is increased, so that much of the voltage applied to the control gate has to be allocated to the floating gate. Therefore, an electrostatic capacity of a capacitor constructed with the control gate and the floating gate has to be increased.
  • FIG. 1 is a view showing a conventional gate electrode structure of a memory cell transistor in an NAND-type flash memory cell.
  • a control gate 9, a floating gate 13, a dielectric layer 5, a gate insulating layer 11, a device separation layer 3, and a substrate 10 are shown.
  • a method of increasing a channel width W and a method of increasing of height H of the floating gate are used.
  • the method of increasing a height of the floating gate has been more widely used than the method of increasing a channel width.
  • FIGS. 2 to 5 are views for explaining a self-aligned method of forming a gate structure of a conventional flash memory cell and show a data disclosed in IEDM 1994, p61 by TOSHIBA.
  • the trenches 19 formed in FIG. 2 are filled with an oxide layer
  • a flash memory cell including: a semiconductor substrate; a device separation layer formed on the semiconductor substrate; a gate insulating layer which is formed between the semiconductor substrate and the device separation layer and is to be a channel region of the flash memory; a floating gate which is formed on the gate insulating layer and is enclosed by the device separation layer; a dielectric layer formed on the floating gate; and a control gate formed on the dielectric layer, wherein the semiconductor substrate includes one or more protrusions in a direction of a width of the channel region of the flash memory cell.
  • a method of manufacturing a self-aligned flash memory cell including steps of: stacking a buffer oxide layer, a first silicon nitride layer, and a first silicon oxide layer on a silicon substrate and performing a patterning process thereon down to the first silicon nitride layer; forming a second silicon oxide layer on the patterned region of the first silicon nitride layer by performing an oxidation process, stacking a second silicon nitride layer, and performing a planarization process thereon; forming trenches in the substrate and filling the trenches with an oxidation layer; performing a planarization process on the oxidation layer filling the trenches down to the second silicon nitride layer; removing the second silicon nitride layer by performing an etching process, removing portions of the oxide layer filling the trenches and the second silicon oxide layer, sequentially forming a tunnel oxide layer and a first polysilicon layer, and
  • a method of manufacturing a self-aligned flash memory cell including steps of: stacking a buffer oxide layer, a first silicon nitride layer, and a first silicon oxide layer on a silicon substrate and performing a patterning process thereon down to the first silicon nitride layer; forming a second silicon oxide layer on the patterned region of the first silicon nitride layer, stacking a second silicon nitride layer, and performing a planarization process thereon; forming trenches in the substrate and filling the trenches with an oxide layer; performing a planarization etching process on the oxide layer filling the trenches down to the second silicon nitride layer; removing the second silicon nitride layer by performing an etching process, removing portions of the oxide layer filling the trenches and the second silicon oxide layer, sequentially forming a tunnel oxide layer and a first polysilicon layer, and performing a planarization process there
  • the self-aligned flash memory cell according to the present invention has enhanced FN tunneling and is provided with a wide channel width, so that it is possible to increase a sensing margin caused from a decrease in unit cell current.
  • FIG. 8 is a view showing a self-aligned flash memory cell according to an embodiment of the present invention.
  • the flash memory cell includes a gate insulating layer 111 which is to be a channel region of the flash memory cell and is formed on the substrate 110 in a device separation layer 103, a floating gate 113 which is formed on the gate insulating layer 111 and is enclosed by the device separation layer 103, an oxide-nitride-oxide (ONO) dielectric layer 105 formed on the floating gate 113, and a control gate 109 formed on the dielectric layer 105.
  • a gate insulating layer 111 which is to be a channel region of the flash memory cell and is formed on the substrate 110 in a device separation layer 103
  • a floating gate 113 which is formed on the gate insulating layer 111 and is enclosed by the device separation layer 103
  • an oxide-nitride-oxide (ONO) dielectric layer 105 formed on the floating gate 113
  • a control gate 109 formed on the dielectric layer 105.
  • a planarization etching process using chemical mechanical planarization (CMP) is performed on the oxide layer 140 filling the trenches 109 down to the silicon nitride layer 107 which is used as the hard mask. Thereafter, the silicon nitride layer 107 is removed by performing a predetermined etching process, and a spacer silicon nitride layer 108 that is used to locally generate high electric fields at a region where a tunnel oxide layer is to be formed is formed. Spacers are formed by performing a dry etching process on the spacer silicon nitride layer 108, and by using the spacers as masks, portions of the substrate are etched.
  • CMP chemical mechanical planarization
  • the silicon nitride layer 117 is planarized by performing a planarization process. Thereafter, the silicon oxide layer 115 which is used as the hard mask and the silicon nitride layer 107 are etched to form trenches 109. The trenches 109 are filled with an oxide layer 140 by performing the LPCVD process.
  • the second polysilicon layer 109, the ONO dielectric layer 105, and the first polysilicon layer 113 are partially etched by performing a patterning process.
  • the self-aligned flash memory cell according to the present invention has an enhanced Fowler-Nordheim (FN) tunneling and is provided with a wide channel width, so that it is possible to increase a sensing margin caused from a decrease in unit cell current.
  • FN Fowler-Nordheim

Abstract

Provided a self-aligned flash memory cell and a method of manufacturing the same. The method of manufacturing the self-aligned flash memory cell includes: forming a spacer silicon nitride layer at a region where a tunnel oxide layer is to be formed; forming spacers by performing etching process on the spacer silicon nitride layer and forming one or more protrusions of a substrate in a direction of a width of a channel region of the flash memory cell by etching portions of the silicon substrate by using the spacers as masks; etching portions of an oxide layer filling trenches, sequentially forming the tunnel oxide layer and a first polysilicon layer, and performing a planarization process thereon; conformably forming a dielectric layer on the entire planarized first polysilicon layer; stacking a second polysilicon layer which is used to form a control gate on the dielectric layer formed on the substrate; and partially etching the second polysilicon layer, the dielectric layer, and the first polysilicon layer by performing a patterning process.

Description

Description SELF-ALIGNED FLASH MEMORY CELL AND METHOD OF
MANUFACTURING THE SAME
Technical Field
[1] The present invention relates to a flash memory device and a method of forming the same, and more particularly, to a structure of a self-aligned flash memory cell and a method of forming the same. Background Art
[2] A non- volatile memory is a memory that can retain stored information even when the power is turned off. As an example of the non- volatile memory, there is a flash memory. Since data stored therein can be electrically erased and reprogrammed, the flash memory is used in various devices. According to a cell array structure, the flash memory is classified into a NOR-type flash memory which offers high speed random access and an NAND-type flash memory which offers fast programming and erasing speed and can be integrated.
[3] In general, a cell transistor of the flash memory has a structure further including a floating gate in addition to a conventional metal oxide semiconductor (MOS) transistor. In the cell transistor of the flash memory, a tunnel oxide layer is formed on a semiconductor substrate and a floating gate is formed on the tunnel oxide layer. A gate interlayer dielectric layer is formed on the floating gate and a control gate electrode is formed on the gate interlayer dielectric layer. For a writing operation of the nonvolatile memory, a Fowler-Nordheim (FN) tunneling method and a hot electron injection method are used. In the FN tunneling method, electrons are injected from the semiconductor substrate into the floating gate by a high electric field applied to the tunnel oxide layer so as to perform the writing operation. In the hot electron injection method, hot electrons generated at a channel region in and around a drain are injected into the floating gate so as to perform the writing operation. For a deleting operation of the flash memory, electrons stored in the floating gate are extracted by FN tunneling in a direction of a source or of the semiconductor substrate.
[4] In order to effectively inject or extract a carrier into or from the floating gate, 1) a method of applying a high voltage to the control gate and the substrate, 2) a method of allocating most of the control gate voltage to the floating gate, are used.
[5] In the first method, there are problems in that, overhead of a device for generating the high voltage increases, and periphery circuits that can stand the high voltage have to be constructed. Therefore, the method does not follow the current trend that a driving voltage is lowered. In the second method, when a high voltage is applied to the control gate, a coupling ratio representing that what ratio is used to allocate the voltage to the floating gate becomes an issue. The coupling ratio depends on an electrostatic capacity between the control gate and the floating gate and an electrostatic capacity between the channel portion of the substrate and the floating gate. For example, in order to effectively perform the electron injection, the coupling ratio is increased, so that much of the voltage applied to the control gate has to be allocated to the floating gate. Therefore, an electrostatic capacity of a capacitor constructed with the control gate and the floating gate has to be increased.
[6] FIG. 1 is a view showing a conventional gate electrode structure of a memory cell transistor in an NAND-type flash memory cell. Referring to FIG. 1, a control gate 9, a floating gate 13, a dielectric layer 5, a gate insulating layer 11, a device separation layer 3, and a substrate 10 are shown. In this structure, in order to increase a coupling ratio between the control gate 9 and the floating gate 13, a method of increasing a channel width W and a method of increasing of height H of the floating gate are used. However, for the high integration, in order to increase a coupling ratio, the method of increasing a height of the floating gate has been more widely used than the method of increasing a channel width.
[7] FIGS. 2 to 5 are views for explaining a self-aligned method of forming a gate structure of a conventional flash memory cell and show a data disclosed in IEDM 1994, p61 by TOSHIBA.
[8] Referring to FIG. 2, a tunnel oxide layer 11 and a first polysilicon layer 13 are stacked on a silicon substrate 10, and a silicon nitride layer 7 that is to be used as a hard mask is stacked. Thereafter, trenches 19 are formed by performing a patterning process. In a conventional patterning process, a photoresist is stacked on the silicon oxide layer, exposed, and developed so as to form a photoresist pattern. The lower silicon nitride layer 7 is etched by using the photoresist pattern as an etching mask, and the photoresist pattern is removed. Thereafter, the first polysilicon layer 13, the tunnel oxide layer 11, and the substrate 10 are etched by using a silicon nitride pattern 7 as an etching mask.
[9] Referring to FIG. 3, the trenches 19 formed in FIG. 2 are filled with an oxide layer
40 by performing a low pressure chemical vapor deposition (LPCVD) process.
[10] Referring to FIG. 4, a planarization etching process using chemical mechanical pla- narization (CMP) is performed on the oxide layer 40 filling the trenches 19, so that portions of the oxide layer 40 on the first polysilicon layer 13 and the silicon nitride layer 7 used as the hard mask are removed. An etching process is performed again on the oxide layer 40 filling the trenches 19, so that portions of side walls of patterns constructed with the first polysilicon layer 13 are exposed. An oxide-nitride-oxide (ONO) dielectric layer 5 is then conformably formed on the entire substrate 10. [11] Referring to FlG. 5, a second poly silicon layer 9 that is used to form the control gate 9 is stacked on the dielectric layer 5 formed on the substrate 10. The polysilicon layer 9, the ONO dielectric layer 5, and the first polysilicon layer 13 are partially etched by performing a patterning process.
[12] According to a United Patent Number 6,074,917, there is a conventional problem in that, in a process of patterning a gate line, it is difficult to etch vertical portions of the ONO layer that is the dielectric layer. When the vertical portions of the ONO layer are not properly etched by performing an anisotropic etching process, a portion of the first polysilicon layer at a bottom of the inclined vertical portions of the ONO layer is not sufficiently removed, so that a bridge may be formed between transistors of a flash memory string connected in series.
[13] In order to prevent the aforementioned problem, spacers are formed at both side walls of the floating gate pattern so as to easily perform the anisotropic etching process on the ONO dielectric layer, or an over-etching process may be performed on the ONO dielectric layer. In a case where the ONO layer is sufficiently etched, the device separation layer of the trenches may be etched, so that the substrate under the first polysilicon layer pattern may be exposed. When the substrate is exposed, in a process for forming the floating gate by selectively etching the first polysilicon layer pattern after etching the ONO dielectric layer, a portion of the substrate may be etched, so that device characteristics may decrease and deterioration may occur. In addition, since a region where the control gate and the floating gate overlap is small, in order to increase the coupling ratio, the height of the floating gate has to be increased. However, as described above, when the height H of the floating gate increases, the vertical portions of the ONO dielectric layer increase, so that the vertical portions become a problem when etched.
[14] In order to solve the problems, in another conventional method, a flash memory cell with a split gate structure manufactured by SST company (United Patent Number 5,029,130) is used. In a conventional self-aligned structure, when electrons are injected into or extracted from the floating gate using the FN tunneling method, an electro field of more than lOMV/cm is required. However, in the flash memory with the split gate structure of SST company, electrons can be injected or extracted by using an electric field of less than 6M/cm that is much less than lOM/cm which is a minimum required for the conventional self-aligned flash memory. A principle that the method can be implemented is that locally enhanced electric fields are formed between the floating gate and the control gate. The structure having the locally enhanced electric fields can be implemented by using band bending of a nonplanar insulating material which exists between the floating gate and the control gate. FIGS. 6 and 7 show a data disclosed in ED 1987, p.1681 by TOSHIBA. [15] However, since the flash memory structure with the split gate structure has complexity of processes and a difficulty in cell shrink, the flash memory structure with the split gate structure has a limitation to be used for a high integrated flash memory cell.
Disclosure of Invention Technical Problem
[16] The present invention provides a self-aligned flash memory cell in order to solve problems of a conventional self-aligned flash memory cell and a flash memory cell with a split gate structure and remove the complexity of forming processes and lack of a process margin.
[17] The present invention also provides a method of manufacturing a self-aligned flash memory cell in which enhanced Fowler-Nordheim (FN) tunneling is possible.
[18] The present invention also provides a method of manufacturing a self-aligned flash memory cell which is provided with a wide channel width, so that it is possible to increase a sensing margin caused from a decrease in unit cell current according to high integration of a memory.
Technical Solution
[19] According to an aspect of the present invention, there is provided a flash memory cell including: a semiconductor substrate; a device separation layer formed on the semiconductor substrate; a gate insulating layer which is formed between the semiconductor substrate and the device separation layer and is to be a channel region of the flash memory; a floating gate which is formed on the gate insulating layer and is enclosed by the device separation layer; a dielectric layer formed on the floating gate; and a control gate formed on the dielectric layer, wherein the semiconductor substrate includes one or more protrusions in a direction of a width of the channel region of the flash memory cell.
[20] According to exemplary embodiments, the substrate may include a dent in the direction of the width of the channel region of the flash memory cell. The protrusion of the substrate of the flash memory cell may have an apex with an interior angle less than 90°
[21] According to another aspect of the present invention, there is provided a method of manufacturing a self-aligned flash memory cell, the method including steps of: stacking a buffer oxide and a silicon nitride layer on a silicon substrate, forming trenches by performing a patterning process, and filling trenches with an oxide layer; performing a planarization etching process on the oxide layer filling the trenches down to the silicon nitride layer; removing the silicon nitride layer by performing an etching process and forming a spacer silicon nitride layer at a region where a tunnel oxide layer is to be formed; forming spacers by performing etching process on the spacer silicon nitride layer and forming one or more protrusions of the substrate in a direction of a width of a channel region of the flash memory cell by etching portions of the silicon substrate by using the spacers as masks; etching portions of the oxide layer filling the trenches, sequentially forming the tunnel oxide layer and a first polysilicon layer, and performing a planarization process thereon; conformably forming a dielectric layer on the entire planarized first polysilicon layer; stacking a second polysilicon layer which is used to form a control gate on the dielectric layer formed on the substrate; and partially etching the second polysilicon layer, the dielectric layer, and the first polysilicon layer by performing a patterning process.
[22] According to another aspect of the present invention, there is provided a method of manufacturing a self-aligned flash memory cell, the method including steps of: stacking a buffer oxide layer, a first silicon nitride layer, and a first silicon oxide layer on a silicon substrate and performing a patterning process thereon down to the first silicon nitride layer; forming a second silicon oxide layer on the patterned region of the first silicon nitride layer by performing an oxidation process, stacking a second silicon nitride layer, and performing a planarization process thereon; forming trenches in the substrate and filling the trenches with an oxidation layer; performing a planarization process on the oxidation layer filling the trenches down to the second silicon nitride layer; removing the second silicon nitride layer by performing an etching process, removing portions of the oxide layer filling the trenches and the second silicon oxide layer, sequentially forming a tunnel oxide layer and a first polysilicon layer, and performing a planarization process thereon; conformably forming a dielectric layer on the entire planarized first polysilicon layer; stacking a second polysilicon layer which is used to form a control gate on the dielectric layer formed on the substrate; and partially etching the second polysilicon layer, the dielectric layer, and the first polysilicon layer by performing a patterning process.
[23] According to exemplary embodiments, the second silicon layer may be formed by performing an oxidation process in order to form an active region having an electric field concentration effect.
[24] According to another aspect of the present invention, there is provided a method of manufacturing a self-aligned flash memory cell, the method including steps of: stacking a buffer oxide layer, a first silicon nitride layer, and a first silicon oxide layer on a silicon substrate and performing a patterning process thereon down to the first silicon nitride layer; forming a second silicon oxide layer on the patterned region of the first silicon nitride layer, stacking a second silicon nitride layer, and performing a planarization process thereon; forming trenches in the substrate and filling the trenches with an oxide layer; performing a planarization etching process on the oxide layer filling the trenches down to the second silicon nitride layer; removing the second silicon nitride layer by performing an etching process, removing portions of the oxide layer filling the trenches and the second silicon oxide layer, sequentially forming a tunnel oxide layer and a first polysilicon layer, and performing a planarization process thereon; forming one or more protrusions of the substrate in a direction of a width of a channel region of the flash memory cell by forming recesses on the oxide layer filling the trenches and conformably forming a dielectric layer on the entire substrate; stacking a second polysilicon layer which is used to form a control gate on the dielectric layer formed on the substrate; and partially etching the second polysilicon layer, the dielectric layer, and the first polysilicon layer by performing a patterning process.
[25] Accordingly, the self-aligned flash memory cell according to the present invention has enhanced FN tunneling and is provided with a wide channel width, so that it is possible to increase a sensing margin caused from a decrease in unit cell current.
[26] The attached drawings for illustrating exemplary embodiments of the present invention are referred to in order to gain a sufficient understanding of the present invention, the merits thereof, and the objectives accomplished by the implementation of the present invention. Brief Description of the Drawings
[27] The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:
[28] FIG. 1 is a view showing a conventional gate electrode structure of a memory cell transistor in an NAND-type flash memory cell;
[29] FIGS. 2 to 5 are views for explaining a self-aligned method of forming a gate structure in a conventional flash memory;
[30] FIGS. 6 and 7 are views showing a data disclosed in ED 1987, p.1681 by
TOSHIBA.
[31] FIG. 8 is a view showing a self-aligned flash memory cell according to an embodiment of the present invention;
[32] FIGS. 9 to 12 are views for explaining a first example of a manufacturing process for forming a self-aligned flash memory cell according to the present invention; and
[33] FIGS. 13 to 17 are views for explaining a second example of a manufacturing process for forming a self-aligned flash memory cell according to the present invention. Best Mode for Carrying Out the Invention
[34] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the attached drawings. Like reference numerals in the drawings denote like elements.
[35] FlG. 8 is a view showing a self-aligned flash memory cell according to an embodiment of the present invention. Referring to FlG. 8, a cross-sectional view of the self-aligned flash memory cell in a direction of a width is shown. The flash memory cell includes a device separation layer 103 formed on a silicon substrate 110. In addition, the flash memory cell includes a gate insulating layer 111 which is to be a channel region of the flash memory cell and is formed on the substrate 110 in a device separation layer 103, a floating gate 113 which is formed on the gate insulating layer 111 and is enclosed by the device separation layer 103, an oxide-nitride-oxide (ONO) dielectric layer 105 formed on the floating gate 113, and a control gate 109 formed on the dielectric layer 105.
[36] Here, the substrate 110 of the flash memory cell has one or more protrusions in a direction of the width of the channel region, and the substrate 110 has a dent in the direction of the width of the channel region. The protrusion of the substrate has an apex with an interior angle less than 90°. Accordingly, the gate insulating layer 111 formed on the protrusion of the substrate 110 has locally enhanced electric fields (shown as circles), so that electron injection and extraction into and from the floating gate 113 can be performed in a low electric filed at the same as or a faster speed than that in a conventional method.
[37] A first example of a manufacturing process for forming the self-aligned flash memory cell 800 having the locally enhanced electric fields (shown as circles) at the gate insulating layer is shown in FIGS. 9 to 12.
[38] Referring to FlG. 9, a buffer oxide layer 102 and a silicon nitride layer 107 which will be used as a hard mask are stacked on the silicon substrate 110, and trenches 109 are formed by performing a patterning process. Thereafter, the trenches 109 are filled with an oxide layer 140 by performing a low pressure chemical vapor deposition (LPCVD) process.
[39] Referring to FlG. 10, a planarization etching process using chemical mechanical planarization (CMP) is performed on the oxide layer 140 filling the trenches 109 down to the silicon nitride layer 107 which is used as the hard mask. Thereafter, the silicon nitride layer 107 is removed by performing a predetermined etching process, and a spacer silicon nitride layer 108 that is used to locally generate high electric fields at a region where a tunnel oxide layer is to be formed is formed. Spacers are formed by performing a dry etching process on the spacer silicon nitride layer 108, and by using the spacers as masks, portions of the substrate are etched.
[40] Referring to FlG. 11, in order to increase an electrostatic capacity of a capacitor, an etching process is performed on the oxide layer 140 filling the trenches 109. Thereafter, a tunnel oxide layer 111 and a first polysilicon layer 113 are sequentially formed, and a planarization process using CMP or the like is performed thereon. The ONO dielectric layer 105 is then conformably formed on the entire substrate 110.
[41] Referring to FlG. 12, a second polysilicon layer 115 that is used to form the control gate is formed on the dielectric layer 105 formed on the substrate 110. By performing a patterning process, the second polysilicon layer 115, the ONO dielectric layer 105, and the first polysilicon layer 113 are partially etched.
[42] Accordingly, the flash memory cell according to the current embodiment has an enhanced Fowler-Nordheim (FN) tunneling.
[43] FIGS. 13 to 17 are views for explaining a second example of a manufacturing process for forming a self-aligned flash memory cell 800 having locally enhanced electric fields at a gate insulating layer.
[44] Referring to FlG. 13, a buffer oxide layer 102, a silicon nitride layer 107, and a silicon oxide layer 115 which will be used as a hard mask are stacked on a silicon substrate 110. After a patterning process is performing thereon down to the silicon nitride layer 107, in order to form an active region having an electric field concentration effect, a silicon oxide layer 116 is formed by performing an oxidation process, and a silicon nitride layer 117 is stacked.
[45] Referring to FlG. 14, the silicon nitride layer 117 is planarized by performing a planarization process. Thereafter, the silicon oxide layer 115 which is used as the hard mask and the silicon nitride layer 107 are etched to form trenches 109. The trenches 109 are filled with an oxide layer 140 by performing the LPCVD process.
[46] Referring to FlG. 15, a planarization etching process using CMP is performed on the oxide layer 140 filling the trenches 109 down to the silicon nitride layer 117 that was used as the hard mask. Thereafter, the silicon nitride layer 117 is removed by performing a predetermined etching process, and in order to form the tunnel oxide layer, portions of the oxide layer 140 filling the trenches 109 and the oxide layer 116 formed by performing the oxidation process are removed. The tunnel oxidation layer 111 and the first polysilicon layer 113 are then sequentially formed.
[47] Referring to FlG. 16, a planarization process using CMP or the like is performed on the first polysilicon layer 113. The ONO dielectric layer 105 is then conformably formed on the entire substrate 110. Thereafter, a second polysilicon layer 109 is stacked on the dielectric layer 105 formed on the substrate 110 in order to form the control gate.
[48]
[49] The second polysilicon layer 109, the ONO dielectric layer 105, and the first polysilicon layer 113 are partially etched by performing a patterning process.
[50] Referring to FlG. 17, unlike the aforementioned process shown in FlG. 16, after the planarization process is performed on the first polysilicon 113, recesses are formed on the oxidation layer 140 in order to increase an electrostatic capacity between the control gate and the floating gate, and the ONO dielectric layer 105 is conformable formed on the entire substrate 110. Thereafter, the second polysilicon layer which is used to form the control gate 109 is formed on the dielectric layer 105 formed on the substrate. The second polysilicon layer, the ONO dielectric layer 105, and the first polysilicon layer 113 are partially etched by performing a patterning process.
[51] Therefore, the flash memory cell according to the embodiment is provided with a wide channel width, so that it is possible to increase a sensing margin caused from a decrease in unit cell current.
[52] While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims. Industrial Applicability
[53] The self-aligned flash memory cell according to the present invention has an enhanced Fowler-Nordheim (FN) tunneling and is provided with a wide channel width, so that it is possible to increase a sensing margin caused from a decrease in unit cell current.

Claims

Claims
[1] A flash memory cell comprising: a silicon substrate; a device separation layer formed on the silicon substrate; a gate insulating layer which is formed between the substrate and the device separation layer and is to be a channel region of the flash memory; a floating gate which is formed on the gate insulating layer and is enclosed by the device separation layer; a dielectric layer formed on the floating gate; and a control gate formed on the dielectric layer, wherein the substrate comprises one or more protrusions in a direction of a width of the channel region of the flash memory cell.
[2] The flash memory cell according to claim 1, wherein the substrate comprises a dent in the direction of the width of the channel region of the flash memory cell.
[3] The flash memory cell according to claim 1, wherein the dielectric layer is an oxide-nitride-oxide (ONO) layer.
[4] The flash memory cell according to claim 1, wherein the device separation layer is made of an oxide layer filling trenches formed in the substrate.
[5] The flash memory cell according to claim 1 or 2, wherein the protrusion of the substrate of the flash memory cell has an apex with an interior angle less than
90°
[6] A method of manufacturing a self-aligned flash memory cell, the method comprising steps of: stacking a buffer oxide and a silicon nitride layer on a silicon substrate, forming trenches by performing a patterning process, and filling trenches with an oxide layer; performing a planarization etching process on the oxide layer filling the trenches down to the silicon nitride layer; removing the silicon nitride layer and forming a spacer silicon nitride layer at a region where a tunnel oxide layer is to be formed; forming spacers on the spacer silicon nitride layer and forming one or more protrusions of the substrate in a direction of a width of a channel region of the flash memory cell by etching portions of the silicon substrate by using the spacers as masks; etching portions of the oxide layer filling the trenches, sequentially forming the tunnel oxide layer and a first polysilicon layer, and performing a planarization process thereon; conformably forming a dielectric layer on the entire planarized first polysilicon layer; stacking a second polysilicon layer which is used to form a control gate on the dielectric layer formed on the substrate; and partially etching the second polysilicon layer, the dielectric layer, and the first polysilicon layer by performing a patterning process.
[7] The method according to claim 6, wherein the trenches are filled with the oxide layer by using a low pressure chemical vapor deposition (LPCVD) method.
[8] The method according to claim 6, wherein the dielectric layer is an ONO layer.
[9] The method according to claim 6, wherein the protrusion of the substrate used in the method of manufacturing the self-aligned flash memory cell has an apex with an interior angle less than 90°
[10] A method of manufacturing a self-aligned flash memory cell, the method comprising steps of: stacking a buffer oxide layer, a first silicon nitride layer, and a first silicon oxide layer on a silicon substrate and performing a patterning and etching process thereon down to the first silicon nitride layer; forming a second silicon oxide layer on the patterned region of the first silicon nitride layer by performing an oxidation process, stacking a second silicon nitride layer, and performing a planarization process thereon; forming trenches in the substrate and filling the trenches with an oxidation layer; performing a planarization process on the oxidation layer filling the trenches down to the second silicon nitride layer; removing the second silicon nitride layer, portions of the oxide layer filling the trenches and the second silicon oxide layer, sequentially forming a tunnel oxide layer and a first polysilicon layer, and performing a planarization process thereon; conformably forming a dielectric layer on the entire planarized first polysilicon layer; stacking a second polysilicon layer which is used to form a control gate on the dielectric layer formed on the substrate; and partially etching the second polysilicon layer, the dielectric layer, and the first polysilicon layer by performing a patterning process.
[11] The method according to claim 10, wherein the second silicon layer is formed by performing an oxidation process in order to form an active region having an electric field concentration effect.
[12] The method according to claim 10, wherein the dielectric layer is an ONO layer.
[13] A method of manufacturing a self-aligned flash memory cell, the method comprising steps of: stacking a buffer oxide layer, a first silicon nitride layer, and a first silicon oxide layer on a silicon substrate and performing a patterning process thereon down to the first silicon nitride layer; forming a second silicon oxide layer on the patterned region of the first silicon nitride layer, stacking a second silicon nitride layer, and performing a pla- narization process thereon; forming trenches in the substrate and filling the trenches with an oxide layer; performing a planarization etching process on the oxide layer filling the trenches down to the second silicon nitride layer; removing the second silicon nitride layer, portions of the oxide layer filling the trenches and the second silicon oxide layer, sequentially forming a tunnel oxide layer and a first polysilicon layer, and performing a planarization process thereon; forming one or more protrusions of the substrate in a direction of a width of a channel region of the flash memory cell by forming recesses on the oxide layer filling the trenches and conformably forming a dielectric layer on the entire substrate; stacking a second polysilicon layer which is used to form a control gate on the dielectric layer formed on the substrate; and partially etching the second polysilicon layer, the dielectric layer, and the first polysilicon layer by performing a patterning process.
[14] The method according to claim 13, wherein the second silicon oxide layer is formed by performing an oxidation process in order to form an active region having an electric field concentration effect.
[15] The method according to claim 13, wherein the dielectric layer is an ONO layer.
[16] The method according to claim 13, wherein the protrusion of the substrate used in the method of manufacturing the self-aligned flash memory cell has an apex with an interior angle less than 90°
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