WO2007110515A3 - Procede de detachement d'un film mince par fusion de precipites - Google Patents

Procede de detachement d'un film mince par fusion de precipites Download PDF

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Publication number
WO2007110515A3
WO2007110515A3 PCT/FR2007/000534 FR2007000534W WO2007110515A3 WO 2007110515 A3 WO2007110515 A3 WO 2007110515A3 FR 2007000534 W FR2007000534 W FR 2007000534W WO 2007110515 A3 WO2007110515 A3 WO 2007110515A3
Authority
WO
WIPO (PCT)
Prior art keywords
precipitates
substrate
thin film
melting
detaching
Prior art date
Application number
PCT/FR2007/000534
Other languages
English (en)
Other versions
WO2007110515A2 (fr
WO2007110515A8 (fr
Inventor
Aurelie Tauzin
Bruce Faure
Arnaud Garnier
Original Assignee
Commissariat Energie Atomique
Soitec Silicon On Insulator
Aurelie Tauzin
Bruce Faure
Arnaud Garnier
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique, Soitec Silicon On Insulator, Aurelie Tauzin, Bruce Faure, Arnaud Garnier filed Critical Commissariat Energie Atomique
Priority to CN2007800116203A priority Critical patent/CN101449369B/zh
Priority to EP07731215.5A priority patent/EP2002474B1/fr
Priority to JP2009502149A priority patent/JP5198429B2/ja
Priority to US12/293,193 priority patent/US7670930B2/en
Priority to KR1020087026389A priority patent/KR101329484B1/ko
Publication of WO2007110515A2 publication Critical patent/WO2007110515A2/fr
Publication of WO2007110515A3 publication Critical patent/WO2007110515A3/fr
Publication of WO2007110515A8 publication Critical patent/WO2007110515A8/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy

Abstract

Un procédé de fabrication d'un film mince à partir d'un substrat comporte les étapes suivantes : (1) implantation dans le substrat par exemple en silicium, d'ions d'une espèce non gazeuse, par exemple du gallium, cette espèce et les conditions d'implantation étant choisies, en fonction du matériau du substrat, en sorte de permettre la formation de précipités confinés en profondeur, répartis au sein d'une couche, ces précipités étant en une phase solide ayant une température de fusion inférieure à celle du substrat; (2) éventuelle mise en contact intime de cette face du substrat avec un raidisseur ; et (3) détachement d'un film mince par rupture du substrat au niveau de la couche de précipités par l'application d'une sollicitation de détachement, mécanique et/ou chimique, dans des conditions où les précipités sont en phase liquide.
PCT/FR2007/000534 2006-03-29 2007-03-28 Procede de detachement d'un film mince par fusion de precipites WO2007110515A2 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN2007800116203A CN101449369B (zh) 2006-03-29 2007-03-28 通过熔化析出物拆分薄膜的方法
EP07731215.5A EP2002474B1 (fr) 2006-03-29 2007-03-28 Procede de detachement d'un film mince par fusion de precipites
JP2009502149A JP5198429B2 (ja) 2006-03-29 2007-03-28 沈殿物の溶融による薄膜の分離方法
US12/293,193 US7670930B2 (en) 2006-03-29 2007-03-28 Method of detaching a thin film by melting precipitates
KR1020087026389A KR101329484B1 (ko) 2006-03-29 2007-03-28 침전물을 용융시킴으로써 박막을 분리하는 방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0651088 2006-03-29
FR0651088A FR2899378B1 (fr) 2006-03-29 2006-03-29 Procede de detachement d'un film mince par fusion de precipites

Publications (3)

Publication Number Publication Date
WO2007110515A2 WO2007110515A2 (fr) 2007-10-04
WO2007110515A3 true WO2007110515A3 (fr) 2008-01-10
WO2007110515A8 WO2007110515A8 (fr) 2009-02-05

Family

ID=37101330

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2007/000534 WO2007110515A2 (fr) 2006-03-29 2007-03-28 Procede de detachement d'un film mince par fusion de precipites

Country Status (7)

Country Link
US (1) US7670930B2 (fr)
EP (1) EP2002474B1 (fr)
JP (1) JP5198429B2 (fr)
KR (1) KR101329484B1 (fr)
CN (1) CN101449369B (fr)
FR (1) FR2899378B1 (fr)
WO (1) WO2007110515A2 (fr)

Families Citing this family (19)

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FR2748851B1 (fr) 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
FR2848336B1 (fr) * 2002-12-09 2005-10-28 Commissariat Energie Atomique Procede de realisation d'une structure contrainte destinee a etre dissociee
FR2856844B1 (fr) 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
FR2861497B1 (fr) * 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
FR2891281B1 (fr) 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
US7910456B1 (en) * 2006-05-26 2011-03-22 Silicon Genesis Corporation Liquid based substrate method and structure for layer transfer applications
FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
FR2922359B1 (fr) * 2007-10-12 2009-12-18 Commissariat Energie Atomique Procede de fabrication d'une structure micro-electronique impliquant un collage moleculaire
FR2930072B1 (fr) 2008-04-15 2010-08-20 Commissariat Energie Atomique Procede de transfert d'une couche mince par echange protonique.
JP2010165927A (ja) * 2009-01-16 2010-07-29 Sumitomo Electric Ind Ltd 発光素子用基板
FR2942073B1 (fr) * 2009-02-10 2011-04-29 Soitec Silicon On Insulator Procede de realisation d'une couche de cavites
FR2943174B1 (fr) * 2009-03-12 2011-04-15 Soitec Silicon On Insulator Adaptation du parametre de maille d'une couche de materiau contraint
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
JP5581619B2 (ja) * 2009-07-07 2014-09-03 株式会社村田製作所 圧電デバイスの製造方法および圧電デバイス
FR2961948B1 (fr) 2010-06-23 2012-08-03 Soitec Silicon On Insulator Procede de traitement d'une piece en materiau compose
TWI445061B (zh) * 2011-01-24 2014-07-11 Hon Hai Prec Ind Co Ltd 氮化鎵基板的製作方法
DE102011010751A1 (de) 2011-02-09 2012-08-09 Osram Opto Semiconductors Gmbh Verfahren zur Durchführung eines Epitaxieprozesses
FR2974944B1 (fr) * 2011-05-02 2013-06-14 Commissariat Energie Atomique Procédé de formation d'une fracture dans un matériau

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Also Published As

Publication number Publication date
JP5198429B2 (ja) 2013-05-15
EP2002474B1 (fr) 2016-09-21
WO2007110515A2 (fr) 2007-10-04
EP2002474A2 (fr) 2008-12-17
US7670930B2 (en) 2010-03-02
KR20090005091A (ko) 2009-01-12
KR101329484B1 (ko) 2013-11-13
FR2899378A1 (fr) 2007-10-05
CN101449369A (zh) 2009-06-03
US20090061594A1 (en) 2009-03-05
JP2009531845A (ja) 2009-09-03
FR2899378B1 (fr) 2008-06-27
WO2007110515A8 (fr) 2009-02-05
CN101449369B (zh) 2011-11-23

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