WO2007109428A3 - Packaging method of chip or package equipped with bumps - Google Patents

Packaging method of chip or package equipped with bumps Download PDF

Info

Publication number
WO2007109428A3
WO2007109428A3 PCT/US2007/063540 US2007063540W WO2007109428A3 WO 2007109428 A3 WO2007109428 A3 WO 2007109428A3 US 2007063540 W US2007063540 W US 2007063540W WO 2007109428 A3 WO2007109428 A3 WO 2007109428A3
Authority
WO
WIPO (PCT)
Prior art keywords
under
fill material
bumps
chip
operation confirmation
Prior art date
Application number
PCT/US2007/063540
Other languages
French (fr)
Other versions
WO2007109428A2 (en
Inventor
Kohichiro Kawate
Yoshihisa Kawate
Andrew C Lottes
Original Assignee
3M Innovative Properties Co
Kohichiro Kawate
Yoshihisa Kawate
Andrew C Lottes
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 3M Innovative Properties Co, Kohichiro Kawate, Yoshihisa Kawate, Andrew C Lottes filed Critical 3M Innovative Properties Co
Priority to CN200780007101XA priority Critical patent/CN101395709B/en
Publication of WO2007109428A2 publication Critical patent/WO2007109428A2/en
Publication of WO2007109428A3 publication Critical patent/WO2007109428A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/90—Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
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    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
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    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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Abstract

To provide a packaging method that connects a semiconductor chip and a substrate through an under-fill material and after an operation confirmation test is conducted, the under-fill material is heat cured. A packaging method of a semiconductor chip or package equipped with bumps, comprises the steps of arranging a heat-fluidizing and thermosetting under-fill material film between a semiconductor chip or package equipped with bumps and a substrate; applying heat and pressure at a temperature and a pressure sufficiently high to cause fluidization of the under-fill material film and to achieve provisional electrical connection; conducting an operation confirmation test; and if the operation confirmation test proves successful, further heating and curing the under-fill material film to obtain the final electronic device, or if the operation confirmation test proves unsuccessful, removing a defective chip or package at a temperature and a pressure sufficient to cause fluidization of the under-fill material film, and repeating the steps described above by using a new chip or package equipped with bumps.
PCT/US2007/063540 2006-03-20 2007-03-08 Packaging method of chip or package equipped with bumps WO2007109428A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN200780007101XA CN101395709B (en) 2006-03-20 2007-03-08 Packaging method of chip or package equipped with bumps

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006-076625 2006-03-20
JP2006076625A JP2007258207A (en) 2006-03-20 2006-03-20 Mounting method of bumped chip or package

Publications (2)

Publication Number Publication Date
WO2007109428A2 WO2007109428A2 (en) 2007-09-27
WO2007109428A3 true WO2007109428A3 (en) 2007-12-13

Family

ID=38523148

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/063540 WO2007109428A2 (en) 2006-03-20 2007-03-08 Packaging method of chip or package equipped with bumps

Country Status (4)

Country Link
JP (1) JP2007258207A (en)
CN (1) CN101395709B (en)
TW (1) TW200741909A (en)
WO (1) WO2007109428A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009182272A (en) 2008-01-31 2009-08-13 Sanyo Electric Co Ltd Device mounting board and method of manufacturing same, semiconductor module and method of manufacturing the same, and portable device
JP5698500B2 (en) * 2009-11-23 2015-04-08 ダウ グローバル テクノロジーズ エルエルシー Epoxy resin formulation for underfill applications

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0669280A (en) * 1992-08-18 1994-03-11 Fujitsu Ltd Mounting structure for bare chip
WO1998031738A1 (en) * 1997-01-17 1998-07-23 Loctite Corporation Thermosetting resin compositions
US5843251A (en) * 1989-03-09 1998-12-01 Hitachi Chemical Co., Ltd. Process for connecting circuits and adhesive film used therefor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5843251A (en) * 1989-03-09 1998-12-01 Hitachi Chemical Co., Ltd. Process for connecting circuits and adhesive film used therefor
JPH0669280A (en) * 1992-08-18 1994-03-11 Fujitsu Ltd Mounting structure for bare chip
WO1998031738A1 (en) * 1997-01-17 1998-07-23 Loctite Corporation Thermosetting resin compositions

Also Published As

Publication number Publication date
JP2007258207A (en) 2007-10-04
CN101395709A (en) 2009-03-25
WO2007109428A2 (en) 2007-09-27
CN101395709B (en) 2010-12-22
TW200741909A (en) 2007-11-01

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