WO2007098236A3 - Contact formation - Google Patents

Contact formation Download PDF

Info

Publication number
WO2007098236A3
WO2007098236A3 PCT/US2007/004573 US2007004573W WO2007098236A3 WO 2007098236 A3 WO2007098236 A3 WO 2007098236A3 US 2007004573 W US2007004573 W US 2007004573W WO 2007098236 A3 WO2007098236 A3 WO 2007098236A3
Authority
WO
WIPO (PCT)
Prior art keywords
trench
depositing
contact formation
gates
present disclosure
Prior art date
Application number
PCT/US2007/004573
Other languages
French (fr)
Other versions
WO2007098236A2 (en
Inventor
James Mathew
H Montgomery Manning
Original Assignee
Micron Technology Inc
James Mathew
H Montgomery Manning
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc, James Mathew, H Montgomery Manning filed Critical Micron Technology Inc
Priority to EP07751342A priority Critical patent/EP1989734A2/en
Priority to JP2008556414A priority patent/JP5403398B2/en
Priority to CN2007800068498A priority patent/CN101390208B/en
Publication of WO2007098236A2 publication Critical patent/WO2007098236A2/en
Publication of WO2007098236A3 publication Critical patent/WO2007098236A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

The present disclosure includes various method, circuit, device, and system embodiments. One such method embodiment includes creating a trench (527) in an insulator stack material (222) having a portion of the trench positioned between two of a number of gates (112) and depositing a spacer material (630) to at least one side surface of the trench. This method also includes depositing a conductive material (732, 834) into the trench and depositing a cap material into the trench.
PCT/US2007/004573 2006-02-27 2007-02-20 Contact formation WO2007098236A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP07751342A EP1989734A2 (en) 2006-02-27 2007-02-20 Contact formation
JP2008556414A JP5403398B2 (en) 2006-02-27 2007-02-20 Contact formation method
CN2007800068498A CN101390208B (en) 2006-02-27 2007-02-20 Contact formation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/363,661 2006-02-27
US11/363,661 US20070202677A1 (en) 2006-02-27 2006-02-27 Contact formation

Publications (2)

Publication Number Publication Date
WO2007098236A2 WO2007098236A2 (en) 2007-08-30
WO2007098236A3 true WO2007098236A3 (en) 2007-11-22

Family

ID=38284019

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/004573 WO2007098236A2 (en) 2006-02-27 2007-02-20 Contact formation

Country Status (8)

Country Link
US (4) US20070202677A1 (en)
EP (2) EP1989734A2 (en)
JP (1) JP5403398B2 (en)
KR (1) KR101082288B1 (en)
CN (1) CN101390208B (en)
SG (1) SG183588A1 (en)
TW (1) TWI343093B (en)
WO (1) WO2007098236A2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070202677A1 (en) 2006-02-27 2007-08-30 Micron Technology, Inc. Contact formation
JP5403862B2 (en) * 2006-11-28 2014-01-29 チェイル インダストリーズ インコーポレイテッド Method for producing fine metal pattern
JP2009176819A (en) * 2008-01-22 2009-08-06 Elpida Memory Inc Semiconductor device and manufacturing method thereof
TWI419033B (en) * 2009-03-05 2013-12-11 Elan Microelectronics Corp Method for manufacturing two - layer circuit board structure for capacitive touch panel
US8241944B2 (en) 2010-07-02 2012-08-14 Micron Technology, Inc. Resistive RAM devices and methods
US20160086956A1 (en) * 2013-04-30 2016-03-24 Ps5 Luxco S.A.R.L. Semiconductor device and method for manufacturing semiconductor device
US10998228B2 (en) * 2014-06-12 2021-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned interconnect with protection layer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6066556A (en) * 1997-12-23 2000-05-23 Samsung Electronics Co., Ltd. Methods of fabricating conductive lines in integrated circuits using insulating sidewall spacers and conductive lines so fabricated
US20040152294A1 (en) * 2003-02-05 2004-08-05 Choi Kyeong Keun Method for forming metal line of semiconductor device
US20040161923A1 (en) * 2003-02-14 2004-08-19 Samsung Electronics Co., Ltd Method for forming wire line by damascene process using hard mask formed from contacts

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3146316B2 (en) * 1991-05-17 2001-03-12 日本テキサス・インスツルメンツ株式会社 Semiconductor device and manufacturing method thereof
US6531730B2 (en) * 1993-08-10 2003-03-11 Micron Technology, Inc. Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same
US5420061A (en) * 1993-08-13 1995-05-30 Micron Semiconductor, Inc. Method for improving latchup immunity in a dual-polysilicon gate process
JP2765478B2 (en) * 1994-03-30 1998-06-18 日本電気株式会社 Semiconductor device and manufacturing method thereof
JP3532325B2 (en) * 1995-07-21 2004-05-31 株式会社東芝 Semiconductor storage device
JPH09260600A (en) 1996-03-19 1997-10-03 Sharp Corp Manufacture of semiconductor memory device
JPH09293781A (en) 1996-04-26 1997-11-11 Sony Corp Manufacture of semiconductor device
US5759892A (en) * 1996-09-24 1998-06-02 Taiwan Semiconductor Manufacturing Company Ltd Formation of self-aligned capacitor contact module in stacked cyclindrical dram cell
US6262450B1 (en) * 1998-04-22 2001-07-17 International Business Machines Corporation DRAM stack capacitor with vias and conductive connection extending from above conductive lines to the substrate
US6174767B1 (en) * 1998-05-11 2001-01-16 Vanguard International Semiconductor Corporation Method of fabrication of capacitor and bit-line at same level for 8F2 DRAM cell with minimum bit-line coupling noise
TW468276B (en) 1998-06-17 2001-12-11 United Microelectronics Corp Self-aligned method for forming capacitor
JP2001007039A (en) * 1999-06-18 2001-01-12 Hitachi Ltd Method for manufacturing semiconductor integrated circuit device
US6255168B1 (en) 1999-09-13 2001-07-03 United Microelectronics Corp. Method for manufacturing bit line and bit line contact
US6504210B1 (en) * 2000-06-23 2003-01-07 International Business Machines Corporation Fully encapsulated damascene gates for Gigabit DRAMs
US6376353B1 (en) * 2000-07-03 2002-04-23 Chartered Semiconductor Manufacturing Ltd. Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects
JP2003100769A (en) * 2001-09-20 2003-04-04 Nec Corp Semiconductor device and its manufacturing method
TW518719B (en) * 2001-10-26 2003-01-21 Promos Technologies Inc Manufacturing method of contact plug
KR100481173B1 (en) * 2002-07-12 2005-04-07 삼성전자주식회사 Semiconductor memory device using Damascene bit line and method for fabricating the same
KR100481177B1 (en) * 2002-08-21 2005-04-07 삼성전자주식회사 A semiconductor device reducing a cell pad resistance and the fabrication method thereof
US6696339B1 (en) * 2002-08-21 2004-02-24 Micron Technology, Inc. Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices
US7138719B2 (en) * 2002-08-29 2006-11-21 Micron Technology, Inc. Trench interconnect structure and formation method
US6730959B1 (en) * 2002-10-30 2004-05-04 Powerchip Semiconductor Corp. Structure of flash memory device and fabrication method thereof
US7074717B2 (en) * 2003-03-04 2006-07-11 Micron Technology, Inc. Damascene processes for forming conductive structures
US6921692B2 (en) * 2003-07-07 2005-07-26 Micron Technology, Inc. Methods of forming memory circuitry
US7217647B2 (en) * 2004-11-04 2007-05-15 International Business Machines Corporation Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern
US20060148168A1 (en) * 2005-01-06 2006-07-06 Sheng-Chin Li Process for fabricating dynamic random access memory
US8125018B2 (en) * 2005-01-12 2012-02-28 Spansion Llc Memory device having trapezoidal bitlines and method of fabricating same
US7723229B2 (en) * 2005-04-22 2010-05-25 Macronix International Co., Ltd. Process of forming a self-aligned contact in a semiconductor device
US7214621B2 (en) * 2005-05-18 2007-05-08 Micron Technology, Inc. Methods of forming devices associated with semiconductor constructions
US20070048951A1 (en) * 2005-08-31 2007-03-01 Hocine Boubekeur Method for production of semiconductor memory devices
US20070202677A1 (en) * 2006-02-27 2007-08-30 Micron Technology, Inc. Contact formation

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6066556A (en) * 1997-12-23 2000-05-23 Samsung Electronics Co., Ltd. Methods of fabricating conductive lines in integrated circuits using insulating sidewall spacers and conductive lines so fabricated
US20040152294A1 (en) * 2003-02-05 2004-08-05 Choi Kyeong Keun Method for forming metal line of semiconductor device
US20040161923A1 (en) * 2003-02-14 2004-08-19 Samsung Electronics Co., Ltd Method for forming wire line by damascene process using hard mask formed from contacts

Also Published As

Publication number Publication date
US20100233875A1 (en) 2010-09-16
JP5403398B2 (en) 2014-01-29
US8377819B2 (en) 2013-02-19
JP2009528678A (en) 2009-08-06
CN101390208B (en) 2012-06-13
TW200739812A (en) 2007-10-16
KR101082288B1 (en) 2011-11-09
CN101390208A (en) 2009-03-18
US8034706B2 (en) 2011-10-11
US7737022B2 (en) 2010-06-15
US20090176365A1 (en) 2009-07-09
SG183588A1 (en) 2012-09-27
EP2194573A2 (en) 2010-06-09
TWI343093B (en) 2011-06-01
US20120009779A1 (en) 2012-01-12
KR20090003276A (en) 2009-01-09
US20070202677A1 (en) 2007-08-30
WO2007098236A2 (en) 2007-08-30
EP2194573A3 (en) 2013-05-01
EP1989734A2 (en) 2008-11-12

Similar Documents

Publication Publication Date Title
WO2008112101A3 (en) Packaging methods for imager devices
WO2007098236A3 (en) Contact formation
WO2009142982A3 (en) Metal gate structure and method of manufacturing same
WO2008099863A1 (en) Semiconductor, semiconductor device, and complementary transistor circuit device
TW200746317A (en) Method of forming a semiconductor device and semiconductor device
WO2008011687A3 (en) Conductive contacts on ge
WO2008063761A3 (en) Method of packaging a device using a dielectric layer
WO2006138491A3 (en) Back-to-front via process
WO2007074404A3 (en) Method and apparatus for patterning a conductive layer, and a device produced thereby
TW200701532A (en) Memory device including barrier layer for improved switching speed and data retention
TW200703522A (en) Method of making a substrate contact for a capped MEMS at the pcakage level
TW200741968A (en) Butted contact structure and method for forming the same
WO2006039907A3 (en) Electrical circuit with a nanostructure and method for contacting a nanostructure
WO2007102998A3 (en) Stacked guard structures
GB2452388A (en) An electrostatic coalescing device
TW200802743A (en) High frequency device module and method for manufacturing the same
WO2007069886A3 (en) Method for interconnecting tracks present on opposite sides of a substrate
WO2008021227A3 (en) High profile contacts for microelectromechanical systems
TWI256684B (en) Method of fabricate interconnect structures
WO2005034186A3 (en) Method for forming a semiconductor device having isolation regions
WO2007120301A3 (en) Electronic device with a multi-gated electrode structure and a process for forming the electronic device
WO2007098305A3 (en) Method and apparatus for forming a semiconductor-on-insulator (soi) body-contacted device
WO2007112137A3 (en) Electrical connector devices and methods of employing same
TWI265570B (en) Semiconductor device with composite etch stop layer and fabrication method thereof
WO2009095835A3 (en) Fully insulated semiconductor device and a method of manufacturing the same

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 2008556414

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 200780006849.8

Country of ref document: CN

Ref document number: 2007751342

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 1020087023686

Country of ref document: KR

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07751342

Country of ref document: EP

Kind code of ref document: A2