WO2007095217A1

WO2007095217A1 - Single latch data circuit in a multiple level cell non-volatile memory device

Info

Publication number: WO2007095217A1
Application number: PCT/US2007/003749
Authority: WO
Inventors: Tommaso Vali; Giovanni Santin; Michele Incarnati
Original assignee: Micron Technology, Inc.
Priority date: 2006-02-15
Filing date: 2007-02-14
Publication date: 2007-08-23

Abstract

A single latch, circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.

Description

SINGLE LATCH DATA CIRCUIT IN A MULTIPLE LEVEL CELL NONVOLATILE MEMORY DEVICE

TECHNICAL FIELD OF THE INVENTION The present invention relates generally to memory devices and in particular the present invention relates to non-volatile memory devices.

BACKGROUND OF THE INVENTION

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.

As the performance and complexity of electronic systems increase, the requirement for additional memory in a system also increases. However, in order to continue to reduce the costs of the system, the parts count must be kept to a minimum. This can be accomplished by increasing the memory density of an integrated circuit. Memory density can be increased by using multiple level cells (MLC). MLC memory can increase the amount of data stored in an integrated circuit without adding additional cells and/or increasing the size of the die. The MLC method stores two or more data bits in each memory cell.

A multilevel cell has multiple V_t windows that each indicate a different state as shown in Figure 1. Multilevel cells take advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific voltage range stored on the cell. This technology permits the storage of two or more bits per cell, depending on the quantity of voltage ranges assigned to the cell.

For example, a cell may be assigned four different voltage ranges of 200 mV for each range. Typically, a dead space or margin of 0.2 V to 0.4V is between each range. If the threshold voltage of the cell is within the first range, the cell is storing a l l. If the threshold voltage is within the second range, the cell is storing a 10. This continues for as many ranges that are used for the cell. MLC requires tight control of the threshold voltages in order to use multiple threshold levels per cell.

One critical parameter of MLC flash memory integrated circuits is the transistor count of the sense amplifier that is used to read the programmed values in the cells. The high parallelism of flash memory devices requires that the same sense amplifier data latch be used at least one for each bit line being read out of the array. This problem is worse for MLC devices since the circuits need to handle two bits from each bit line. This greatly increases the number of transistors required for read-modify- write operations. Due to intense competition and consumer desire for longer battery life in electronic devices, manufacturers must constantly find ways to reduce the quantity of components in devices while maintaining reliability. For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for reducing the quantity of transistors required in sense amplifier data latches in MLC memory devices.

SUMMARY

The above-mentioned problems with flash memories and other problems are addressed by the present invention and will be understood by reading and studying the following specification.

The present invention encompasses a memory latch circuit. The circuit comprises a latch having a node and an inverted node. A first control transistor is coupled between an output of the circuit and the node. A second control transistor is coupled between the output and the inverted node. A reset transistor is coupled to the inverted node. The control transistors selectively coupling either the node or the inverted node to the output in response to control signals on the transistor gates. The reset transistor pulls the inverted node to ground potential in response to a reset signal.

The method includes writing the desired data to one of either the least significant bit or the most significant bit of a cell to be programmed. A second programming operation programs reinforcing data to the remaining bit of the cell. The reinforcing data adjusts the threshold level of the cell to the voltage required by the desired data.

Further embodiments of the invention include methods and apparatus of varying scope.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows a diagram of the threshold voltage distributions of a multiple level cell memory.

Figure 2 shows a simplified diagram of one embodiment of a NAND flash memory array. Figure 3 shows a schematic diagram of one embodiment of a data latch of the present invention.

Figure 4 shows a diagram of the threshold voltage distribution in accordance with a page one read operation of the present invention.

Figure 5 shows a diagram of the threshold voltage distribution in accordance with a page zero read operation of the present invention.

Figure 6 shows a schematic diagram of one embodiment of two data latches in accordance with the programming operation of the present invention.

Figure 7 shows a schematic diagram of the data latches and support circuitry of the present invention. Figure 8 shows a block diagram of one embodiment of a memory system of the present invention.

Figure 9 shows a block diagram of one embodiment of a memory module of the present invention. DETAILED DESCRIPTION

In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof.

Figure 2 illustrates a simplified diagram of one embodiment for a semiconductor NAND flash memory array of the present invention. This memory array is for purposes of illustration only as the present invention is not limited any one non-volatile memory technology or architecture. The memory array of Figure 2, for purposes of clarity, does not show all of the elements typically required in a memory array. For example, only two bit lines are shown (BLl and BL2) when the number of bit lines required actually depends upon the memory density and chip architecture. The bit lines are subsequently referred to as (BLl — BLN). The bit lines (BLl — BLN) are eventually coupled to sense amplifiers (not shown) that detect the state of each cell.

The array is comprised of an array of floating gate cells 201 arranged in series strings 204, 205. Each of the floating gate cells 201 are coupled drain to source in each series chain 204, 205. A word line (WLO — WL31 ) that spans across multiple series strings 204, 205 is coupled to the control gates of every floating gate cell in a row in order to control their operation. In one embodiment, an array is comprised of 32 word lines. However, the present invention is not limited to any one word line quantity.

In operation, the word lines (WLO — WL31) select the individual floating gate memory cells in the series chain 204, 205 to be written to or read from and operate the remaining floating gate memory cells in each series string 204, 205 in a pass through mode. Each series string 204, 205 of floating gate memory cells is coupled to a source line 206 by a source select gate 216, 217 and to an individual bit line (BLl - BLN) by a drain select gate 212, 213. The source select gates 216, 217 are controlled by a source select gate control line SG(S) 218 coupled to their control gates. The drain select gates 212, 213 are controlled by a drain select gate control line SG(D) 214.

In the embodiment of Figure 2, WLO is at the bottom of the page and WL31 is at the top of the page. However, these labels are for purposes of illustration only as WLO can also begin at the top of the page with the word line numbers increasing towards the bottom of the page.

Each cell can be programmed as a single bit per cell (i.e., single level cell — SLC) or multiple bits per cell (i.e., multiple level cell — MLC). Each cell's threshold voltage (V_t) determines the data that is stored in the cell. For example, in a single bit per cell, a V_t of 0.5V might indicate a programmed cell (i.e., logical 0 state) while a V_t of —0.5V might indicate an erased cell (i.e., logical 1 state). Multiple level cell operation has been discussed previously.

The embodiments of the present invention are not limited to two bits per cell. Some embodiments may store more than two bits per cell, depending on the quantity of different voltage ranges that can be differentiated on the cell. During a typical prior art programming operation, the selected word line for the flash memory cell to be programmed is biased with a series of programming pulses that start at a voltage (e.g., 20V) with each subsequent pulse voltage increasing incrementally until the cell is programmed or a maximum programming voltage is reached. Unselected word lines are biased at V_pass (e.g., 1 OV). Selected bit lines are biased at OV while unselected bit lines are biased V_Cc to inhibit the program operation for those series strings.

A verification (read) operation with a selected word line voltage of OV is then performed to determine if the floating gate is at the proper voltage (e.g., 0.5 V). In one embodiment, the unselected word line voltages can be any voltage equal to or greater than ground potential. The bit lines are precharged to Vcc while the SG(D) and SG(S) are selected. Each of the memory cells is programmed/verified in a substantially similar fashion.

Figure 3 illustrates a schematic diagram of a data latch circuit 300 of the present invention coupled to a portion of a series string of memory cells 340 of a NAND flash memory array.

The latch circuit 300 is comprised of two inverters 304, 305 that are coupled to a DATA node and a DATA* node that is the inverse of the DATA node. Three control transistors 301, 302, and 306 are coupled to the inverters 304, 305 to control the operation of the latch circuit 300. Two of the transistors 301, 302 control which side (i.e., DATA or DATA*) of the latch 304, 305, in response to active high RDA and RDB control signals, is coupled to the SENSE_OUT node. The other transistor 306 is a reset transistor that has an active high PRST signal coupled to the gate to control when the transistor is turned on to pull the DATA* output of the latch to ground.

The series string of memory cells 340, in one embodiment, is comprised of thirty- two floating gate flash memory cells as illustrated in Figure 2. Each of the memory cells in unselected rows that are biased by the "WLUNSEL" voltage that is coupled to each of the "unselected" word lines. The selected word line is biased by the "WLSEL" voltage. Alternate embodiments can use other quantities of memory cells in each series string as well as different non-volatile memory cell technology.

The select gate source transistor 325 and the select gate drain transistor 324 are on opposing sides of the string 340. The series string 340 is then coupled to the global bit line GBL that is coupled to an NMOS control transistor 322 that controls access to the sense amplifier by the string 340. The gate of the control transistor 322 is biased by a "SENSE" voltage that controls operation of the transistor 322.

A precharge PMOS transistor 320 couples the NMOS control transistor 322 to V_<χ for precharging the bit line during a read operation. A logical low level on the gate of the PMOS transistor 320 turns the transistor on. A sense amplifier output transistor 310 has its gate coupled between the NMOS transistor 322 and the PMOS transistor 320. A logical high on the gate of this, transistor 310 pulls the latch circuit 300 to ground as will be described subsequently. A logical low on the gate causes the latch circuit 300 to see a high impedance state.

Operation of the latch circuit 300 of Figure 3 is discussed with reference to the threshold voltage distributions illustrated in Figures 4 and 5. Each distribution, 401 — 404 of Figure 4 and 501 — 504 of Figure 5, represents a different MLC state. The MLC data stored in each cell represents two pages of data, page 1 and page 0 (i.e., Pl-PO).

Figure 4 illustrates the threshold voltage distributions 401 — 404 for reading page 1 (Pl) of the memory cells. The most negative state 401 is a logical "11" state. The next state 402 is the logical "10" state. The following state 403 is the logical "00" state. The most positive state 404 is the logical "01" state. The read voltage, RD2, that is applied to the selected word line as the "WLSEL" voltage is illustrated between the middle two states 402, 403.

Figure 5 illustrates the threshold voltage distributions 501 - 504 for reading page 0 (PO) of the memory cells. The most negative state 501 is a logical "11" state. The next most positive state 502 is the logical "10" state. The following state 503 is a logical "00" state. The most positive state 504 is the logical "01" state. The read voltages, RDl and RD3, are applied to the selected word line as the "WLSEL" voltage. The read 1 voltage (i.e., RDl) is between the first and second states 501, 502. The read 3 voltage (i.e., RD3) is between the last two states 503, 504. Referring to Figures 3 and 4, the first state (i.e., logical 11) 401 is read by the following procedure. At a first time, to, the PRST signal is a logical 1 and RDA is a logical 0. This results in the latch circuit DATA* signal being a logical 0 and DATA is loaded with a logical 1.

At time ti, the PRST signal is a logical 0 to turn off the transistor 306. The memory cell transistor 330 is coupled to the selected word line bias WLSEL that is now at the read voltage RD2 as illustrated in Figure 4. The sense amplifier then performs a sense operation as is well known in the art. After the sense operation, RDA is a logical 1 to turn on its respective transistor 301 and RDB is kept at a logical 0 to keep the transistor 302 turned off, thus connecting the DATA node of the latch to the SENSE_OUT node that is now floating. This results in the logical 1 (i.e., DATA) of pagel of the first state 401 being read.

The second state (i.e., logical 10) 402 is read by the following procedure. At a first time, to, the PRST signal is a logical 1 and RDA is a logical 0. This results in the latch circuit DATA* signal being a logical 0 and DATA is loaded with a logical 1.

At time tt, the PRST signal is a logical 0 to turn off the transistor 306. The memory cell transistor 330 is coupled to the selected word line bias WLSEL that is now at the read voltage RD2 as illustrated in Figure 4. The sense amplifier then performs a sense operation as is well known in the art. After the sense operation, RDA is a logical 1 to turn on its respective transistor 301 and RDB is kept at a logical 0 to keep the transistor 302 turned off, thus connecting the DATA node of the latch to the SENSE OUT node that is now floating. This results in the logical 1 (i.e., DATA) of pagel of the second state 402 being read. The third state (i.e., logical 00) 403 is read by the following procedure. At a first time, to, the PRST signal is a logical 1 and RDA is a logical 0. This results in the latch circuit DATA* signal being a logical 0 and DATA is loaded with a logical 1.

At time t_t, the PRST signal is a logical 0 to turn off the transistor 306. The memory cell transistor 330 is coupled to the selected word line bias WLSEL that is now at the read voltage RD2 as illustrated in Figure 4. The sense amplifier then performs a sense operation as is well known in the art. After the sense operation, RDA is a logical 1 to turn on its respective transistor 301 and RDB is kept at a logical 0 to keep the transistor 302 turned off, thus connecting the DATA node of the latch to the SENSE OUT node that is now at a logical 0. This results in the logical 0 (i.e., DATA) of pagel of the third state 403 being read.

The fourth state (i.e., logical 01) 404 is read by the following procedure. At a first time, to, the PRST signal is a logical 1 and RDA is a logical 0. This results in the latch circuit DATA* signal being a logical 0 and DATA is loaded with a logical 1.

At time t], the PRST signal is a logical 0 to turn off the transistor 306. The memory cell transistor 330 is coupled to the selected word line bias WLSEL that is now at the read voltage RD2 as illustrated in Figure 4. The sense amplifier then performs a sense operation as is well known in the art. After the sense operation, RDA is a logical 1 to turn on its respective transistor 301 and RDB is kept at a logical 0 to keep the transistor 302 turned off, thus connecting the DATA node of the latch to the SENSE_OUT node that is now at a logical 0. This results in the logical 0 (i.e., DATA) of pagel of the fourth state 404 being read.

Referring to Figures 3 and 5, the first state 501 of page 0 (i.e., PO) is read by the following procedure. At a first time, to, the PRST signal is a logical 1 and RDA is a logical 0. This results in the latch circuit DATA* signal being a logical 0 and DATA is loaded with a logical 1. At time ti, the PRST signal is a logical 0 to .turn off the transistor 306. The memory cell transistor 330 is coupled to the selected word line bias WLSEL that is now at the read voltage RDl as illustrated in Figure 5. The sense amplifier then performs a sense operation as is well known in the art. After the sense operation, RDA is a logical 1 to turn on its respective transistor 301 and RDB is kept at a logical 0 to keep the transistor 302 turned off thus connecting the DATA node of the latch to the SENSE_OUT node that is now floating. This results in the node DATA being a logic 1. At time t₂, the PRST signal is a logical 0 to turn off the transistor 306. The memory cell transistor 330 is coupled to the selected word line bias WLSEL that is now at the read voltage RD3 as illustrated in Figure 5. The sense amplifier then performs a sense operation as is well known in the aft. After the sense operation, RDA is a logical 0, RDB is a logical 1 to turn on its respective transistor 302 thus connecting the DATA* node of the latch formed by the inverters 304, 305 to the SENSE OUT node that is now floating. This results in the logical 1 (i.e., DATA) of page 0 of the first state 501 being read.

The second state (i.e., logical 10) 502 is read by the following procedure. At a first time, to, the PRST signal is a logical 1 and RDA is a logical 0. This results in the latch circuit DATA* signal being a logical 0 and DATA is loaded with a logical 1.

At time ti, the PRST signal is a logical 0 to turn off the transistor 306. The memory cell transistor 330 is coupled to the selected word line bias WLSEL that is now at the read voltage RDl as illustrated in Figure 5. The sense amplifier then performs a sense operation as is well known in the art. After the sense operation, RDA is a logical 1 to turn on its respective transistor 301 and RDB is kept at a logical 0 to keep the transistor 302 turned off thus connecting the DATA node of the latch to the SENSE_OUT node that is now a logical 0. ^' This results in the node DATA being a logic 0.

At time t₂, the PRST signal is a logical 0 to turn off the transistor 306. The memory cell transistor 330 is coupled to the selected word line bias WLSEL that is now at the read voltage RD3 as illustrated in Figure 5. The sense amplifier then performs a sense operation as is well known in the art. After the sense operation, RDA is a logical 0, RDB is a logical 1 to turn on its respective transistor 302 thus connecting the DATA* node of the latch formed by the inverters 304, 305 to the SENSE-OUT node that is now floating. This results in the logical 0 (i.e., DATA) of page 0 of the second state 502 being read. The third state (i.e., logical 00) 503 is read by the following procedure. At a first time, to, the PRST signal is a logical 1 and RDA is a logical 0. This results in the latch circuit DATA* signal being a logical 0 and DATA is loaded with a logical 1.

At time ti, the PRST signal is a logical 0 to turn off the transistor 306. The memory cell transistor 330 is coupled to the selected word line bias WLSEL that is now at the read voltage RDl as illustrated in Figure 5. The sense amplifier then performs a sense operation as is well known in the art. After the sense operation, RDA is a logical 1 to turn on its respective transistor 301 and RDB is kept at a logical 0 to keep the transistor 302 turned off thus connecting the DATA node of the latch to the SENSE_OUT node that is now at a logical 0. This results in the node DATA being a logic 0.

At time t₂, the PRST signal is a logical 0 to turn off the transistor 306. The memory cell transistor 330 is coupled to the selected word line bias WLSEL that is now at the read voltage RD3 as illustrated in Figure 5. The sense amplifier then performs a sense operation as is well known in the art. After the sense operation, RDA is a logical 0, RDB is a logical 1 to turn on its respective transistor 302 thus connecting the DATA* node of the latch formed by the inverters 304, 305 to the SENSEJDUT node that is now floating. This results in the logical 0 (i.e., DATA) of page 0 of the third state 503 being read.

The fourth state (i.e., logical 01) 504 is read by the following procedure. At a first time, to, the PRST signal is a logical 1 and RDA is a logical 0. This results in the latch circuit DATA* signal being a logical 0 and DATA is loaded with a logical 1.

At time t₂, the PRST signal is a logical 0 to turn off the transistor 306. The memory cell transistor 330 is coupled to the selected word line bias WLSEL that is now at the read voltage RD3 as illustrated in Figure 5. The sense amplifier then performs a sense operation as is well known in the art. After the sense operation, RDA is a logical 0, RDB is a logical 1 to turn on its respective transistor 302 thus connecting the DATA* node of the latch formed by the inverters 304, 305 to the SENSEjDUT node that is now at a logical 0. This results in the logical 1 (i.e., DATA) of page 0 of the fourth state 504 being read.

A read-modify- write technique is used to generate the inhibit voltage of the program operation of a NAND cell when its V_t pass the verify level. One embodiment for a circuit to accomplish this is illustrated in Figure 6. The circuit is comprised of a latch 600, made up of two inverters 602, 603, with a control transistor 605. The gate of the transistor 605 is connected to "CSENSEl" control signal that goes high when a cell has been verified as programmed during a verify operation. The drain of the transistor 605 is shown coupled to a circuit ground in dotted lines. The dotted lines represent the functional equivalent of the circuit to which the transistor 605 is coupled as illustrated subsequently with reference to Figure 7.

The read-modify-write technique involves storing the data to be programmed in the latch 600 as DATA during the program pulse and then modify it when the V_t of the cell has become higher than a predetermined verify value. In other words, the cell has been successfully programmed. For example, assuming that DATA to be programmed is a logical 0 and while the "CSENSEl" signal is low, the transistor 605 is turned off and the latch output through the inverter gate 606 is a logical "0". The inverter gate 606 is enabled whenever the program pulse (i.e., pgm_pulse) goes high. During this time, the logical low signal is applied to the bit line thus allowing the cells on the selected word line to be programmed. When CSENSEl goes high after the verify operation has passed, DATA* is pulled to a logical 0 through the transistor 605 and the output of the inverter gate 606 is a logical high. This Vcc bias is applied to the bit line, thereby inhibiting the program operation.

Figure 7 illustrates the data latches and support circuitry of the present invention. This circuit includes the first data latch circuit 300 as illustrated in Figure 3 and the second data latch circuit 600 as illustrated in Figure 6. The pass transistors 701 , 702 and support circuitry 704, 705 that ties the latches 300, 600 together is also shown. A pull-up transistor 721 is coupled to a VFY_MATCH signal that is a logic high when the programmed data has been verified. A pull-down transistor 720 is coupled to the first latch circuit 300 with a "PULLDOWNJEN" signal coupled to the gate that goes high to turn on the transistor 720. After the read-modify-write operation described previously, VFY_MATCH is precharged or pulled up to a logical 1 level. Then ifall the bits to be programmed are modified from 0 to 1, the node DATA* will be at a logical 0 and the common line VFY MATCH will stay at a logical 1. If some of the bits to be programmed are still at a logical 0 after the read-modify-write operation, the information regarding the bits failing to verify can be extracted. To extract the bit information, PASSl is set high, PASSO is set low, and PULLDOWNJEN is set to a high state. The VFY_MATCH line is pulled down if any of page 0 (PO) die not pass the verify operation during a PO programming.

By making PASSl = 0, PASSO = 1, and PULLDOWN_EN = 1, the VFY_MATCH line will be pulled down if any of Pl, having PO = 0, did not pass the verify operation. By making PASSl = 1, PASSO = 1, and PULLDOWN_EN = 1, the VFY_MATCH line is pulled down if any of the data to be programmed did not pass the verify operation.

To verify the programming of PO, the first latch circuit 300 is preset so that DATA node is a logical 1. PO = 0 is loaded into the second latch circuit 600 at node DATA. A verify voltage, VFYl is applied to WLSEL and PASSl = 1. In one embodiment, the VFYl voltage is located between the first two MLC states. A sense operation is then performed by the sense amplifier as is well known in the art. After the sense operation, CSENSEl = 1.

If the threshold voltage sensed is greater than or equal to VFYl, SENSE_OUT = 0, NODEB = 0, and PO becomes a logical 1. The programming is inhibited as explained previously for the next programming pulse.

If the threshold voltage sensed is less than VFYl, SENSEJDUT is in a high impedance state and PO stays a logical low. The programming operation is then performed again.

To verify the programming of Pl with VF Y3 voltage when PO = 1, PO is read and stored in the first latch 300 at the DATA node during the beginning of the programming operation. Pl = 0 is loaded into the second latch 600 at the DATA node. A verify voltage, VF Y3 is used to bias the selected word line as WLSEL. VFY3, in one embodiment, is a voltage located between the third and fourth MLC states. VFY2, in one embodiment, is a voltage located between the second and third MLC states. The gates of the pass transistors 701, 702 are biased as PASSl = 1 and PASSO = 0.

A sense operation is then performed. After the sense amplifier has accomplished the sense operation, CSENSEl = 1. If the threshold voltage, V_t, is greater than or equal to VFY3, the SENSE_OUT node = 0 and NODEB = 0. PO becomes a logical 1 and the programming operation is inhibited for the next programming pulse only for cells having PO = 1. If V_t is less than VFY3, the SENSE_OUT node is high impedance and PO stays as a logical 0. The programming operation is performed again. To verify the programming of Pl with VFY2 when PO = 0, PO is read and loaded into the first latch circuit at the DATA node during the beginning of the programming operation. The DATA node of the second latch 600 is loaded with Pl = 0. A verify voltage, VFY2, biases the selected word line as the WLSEL voltage. PASSO = 1 and PASSl = 0. A sense operation is then performed by the sense amplifier. After the sense operation, CSENSEl = 1.

If the sensed threshold voltage', Vt, is greater than or equal to VF Y3, the SENSE OUT node is a logical 0, NODEB = 0, and PO becomes a logical 1. The next programming operation is inhibited only for cells having Pl = O. If the sensed threshold is less than VFY3, the SENSE OUT node is in a high impedance state. In this case, PO stays as a logical 0 and the programming operation is performed again.

Figure 8 illustrates a functional block diagram of a memory device 800 that can incorporate the flash memory array and programming method embodiments of the present invention. The memory device 800 is coupled to a processor 810 that is responsible for executing the software driver of the present invention for writing SLC data into an MLC device. The processor 810 may be a microprocessor or some other type of controlling circuitry. The memory device 800 and the processor 810 form part of a memory system 820. The memory device 800 has been simplified to focus on features of the memory that are helpful in understanding the present invention.

The memory device includes an array of flash memory cells 830 as described above with reference to Figure 8. The memory array 830 is arranged in banks of rows and columns. The control gates of each row of memory cells is coupled with a word line while the drain and source connections of the memory cells are coupled to bitlines. As is well known in the art, the connections of the cells to the bitlines determines whether the array is a NAND architecture, an AND architecture, or a NOR architecture.

An address buffer circuit 840 is provided to latch address signals provided on address input connections AO-Ax 842. Address signals are received and decoded by a row decoder 844 and a column decoder 846 to access the memory array 830. It will be appreciated by those skilled in the art, with the benefit of the present description/that the number of address input connections depends on the density and architecture of the memory array 830. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.

The memory device 800 reads data in the memory array 830 by sensing voltage or current changes in the memory array columns using sense/buffer circuitry 850. The sense/buffer circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array 830. Data input and output buffer circuitry 860 is included for bi-directional data communication over a plurality of data connections 862 with the controller 810. Write circuitry 855 is provided to write data to the memory array.

Control circuitry 870 decodes signals provided on control connections 872 from the processor 810. These signals are used to control the operations on the memory array 830, including data read, data write (program), and erase operations. The control circuitry 870 may be a state machine, a sequencer, or some other type of controller.

The flash memory device illustrated in Figure 8 has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art.

Figure 9 is an illustration of an exemplary memory module 900. Memory module 900 is illustrated as a memory card, although the concepts discussed with reference to memory module 900 are applicable to other types of removable or portable memory, e.g., USB flash drives, and are intended to be within the scope of "memory module" as used herein. In addition, although one example form factor is depicted in Figure 9, these concepts are applicable to other form factors as well.

In some embodiments, memory module 900 will include a housing 905 (as depicted) to enclose one or more memory devices 910, though such a housing is not essential to all devices or device applications. At least one memory device 910 is a non-volatile memory [including or adapted to perform elements of the invention] . Where present, the housing 905 includes one or more contacts 915 for communication with a host device. Examples of host devices include digital cameras, digital recording and playback devices, PDAs, personal computers, memory card readers, interface hubs and the like. For some embodiments, the contacts 915 are in the form of a standardized interface. For example, with a USB flash drive, the contacts 915 might be in the form of a USB Type-A male connector. For some embodiments, the contacts 915 are in the form of a semi-proprietary interface, such as might be found on COMPACTFLASH memory cards licensed by SANDISK Corporation, MEMORYSTICK memory cards licensed by SONY Corporation, SD SECURE DIGITAL memory cards licensed by TOSHIBA Corporation and the like. In general, however, contacts 915 provide an interface for passing control, address and/or data signals between the memory module 900 and a host having compatible receptors for the contacts 915.

The memory module 900 may optionally include additional circuitry 920 which may be one or more integrated circuits and/or discrete components. For some embodiments, the additional circuitry 920 may include a memory controller for controlling access across multiple memory devices 910 and/or for providing a translation layer between an external host and a memory device 910. For example, there may not be a one-to-one correspondence between the number of contacts 915 and a number of I/O connections to the one or more memory devices 910. Thus, a memory controller could selectively couple an I/O connection (not shown in Figure 9) of a memory device 910 to receive the appropriate signal at the appropriate I/O connection at the appropriate time or to provide the appropriate signal at the appropriate contact 915 at the appropriate time. Similarly, the communication protocol between a host and the memory module 900 may be different than what is required for access of a memory device 910. A memory controller could then translate the command sequences received from a host into the appropriate command sequences to achieve the desired access to the memory device 910. Such translation may further include changes in signal voltage levels in addition to command sequences.

The additional circuitry 920 may further include functionality unrelated to control of a memory device 910 such as logic functions as might be performed by an ASIC (application specific integrated circuit). Also, the additional circuitry 920 may include circuitry to restrict read or write access to the memory module 900, such as password protection, biometrics or the like. The additional circuitry 920 may include circuitry to indicate a status of the memory module 900. For example, the additional circuitry 920 may include functionality to determine whether power is being supplied to the memory module 900 and whether the memory module 900 is currently being accessed, and to display an indication of its status, such as a solid light while powered and a flashing light while being accessed. The additional circuitry 920 may further include passive devices, such as decoupling capacitors to help regulate power requirements within the memory module 900. Conclusion

In summary, the embodiments of the present invention handle two bits from an MLC memory device with only a single latch. Only one additional latch is used to implement MLC programming with a read-modify-write and verify during a programming operation. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.

Claims

What is claimed is:

1. A memory latch circuit comprising: a latch having a node and an inverted node; a first transistor coupled between an output and the node; a second transistor coupled between the output and the inverted node; and a reset transistor coupled to the inverted node.

2. The latch circuit of claim 1 and further including a series memory string having a bit line coupled to the output.

3. The latch circuit of claim 1 wherein the latch is comprised of a pair of inverter gates coupled such that an input of each inverter is coupled to an output of the other inverter.

4. The latch circuit of claim 2 wherein the memory string is comprised of a plurality of non-volatile memory cells arranged in a NAND configuration.

5. The latch circuit of claim 1 wherein the first, second, and reset transistors are NMOS transistors.

6. The latch circuit of claim 1 wherein the first, second, and reset transistors have gate connections that are coupled to active high signals.

7. The latch circuit of claim 1 wherein the output is coupled to a sense amplifier output transistor.

8. A memory latch circuit comprising: a latch having a node and an inverted node; a first control transistor coupled between an output and the node to couple the node to the output in response to a first control signal; a second control transistor coupled between the output and the inverted node to couple the inverted node to the output in response to a second control signal; a reset transistor coupled to the inverted node for pulling the inverted node to ground in response to a reset signal.

9. The memory latch of claim 8 wherein the first control signal, second control signal, and reset signal are connected to gate inputs of their respective transistors and turn on the respective transistor in response to a logical high.

10. A memory latch circuit to implement a multiple level cell memory programming operation, the circuit comprising: a first latch having a node and an inverted node; a first transistor coupled between an output and the node; a second transistor coupled between the output and the inverted node; a reset transistor coupled to the inverted node; a second latch having a node and an inverted node; a sense control transistor coupled to the inverted node; and an output inverter gate coupled to the inverted node such that an output of the output inverter gate is an output of the second latch.

11. The circuit of claim 10 wherein the sense control transistor selectively pulls the inverted node to ground potential in response to a control sense signal.

12. The circuit of claim 11 wherein the control sense signal is coupled to a gate of the sense control transistor and turns on the transistor, when at a logical high state, to pull the inverted node to ground potential.

13. The circuit of claim 10 wherein the first and second latches are each comprised of a pair of inverter gates coupled such that the output of each gate is connected to an input of the other gate.

14. A flash memory device comprising: a memory array comprising a plurality of non- volatile memory cells arranged in rows and columns such that each column is comprised of a series string of memory cells coupled to a bit line; and a memory latch circuit to implement a multiple level cell memory programming operation on the memory array, the circuit coupled to the memory array and comprising: a first latch having a node and an inverted node; a first transistor coupled between an output and the node; a second transistor coupled between the output and the inverted node; a reset transistor coupled to the inverted node; a second latch having a node and an inverted node; a sense control transistor coupled to the inverted node; and an output inverter gate coupled to the inverted node such that an output of the output inverter gate is coupled to the bit line.

15. The device of claim 14 wherein the memory array is arranged in a NAND architecture.

16. The device of claim 14 and further including a sense transistor that couples the bit line to the output of the first latch.

17. The device of claim 14 wherein each of the plurality of memory cells is adapted to store two bits of data.

18. A memory system comprising: a processor that generates memory signals; and a memory device coupled to the processor and operating in response to the memory signals, the memory device comprising: a memory array comprising a plurality of non- volatile memory cells arranged in rows and columns such that each column is comprised of a series string of memory cells coupled to a bit line; and a memory latch circuit coupled to each bit line of the memory array and comprising: a latch having a node and an inverted node; a first transistor coupled between an output and the node; a second transistor coupled between the output and the inverted node; and a reset transistor coupled to the inverted node.

19. The system of claim 18 wherein the memory array is a NAND architecture memory array.

20. The system of claim 18 and further including a read-modify-write circuit coupled to each bit line for inhibiting programming of selected cells on the bit line, the circuit comprising: a latch having a node and an inverted node; a sense control transistor coupled to the inverted node; and an output inverter gate coupled to the inverted node such that an output of the output inverter gate is coupled to the bit line.

21. A memory module comprising: at least two memory devices, each comprising a multiple level memory array arranged in rows and columns such that the rows comprise word lines coupled to control gates of a plurality of memory cells and the columns comprise bit lines coupled to series strings of memory cells, the memory array further arranged in memory blocks, the memory array further comprising: a memory latch circuit coupled to each bit line of the memory array and comprising: a latch having a node and an inverted node; a first transistor coupled between an output and the node; a second transistor coupled between the output and the inverted node; and a reset transistor coupled to the inverted node; and a plurality of contacts configured to provide selective contact between the memory array and a host system.

22. The module of claim 21 and further including a memory controller coupled to the memory array for controlling operation of the memory device in response to the host system.

23. A method for reading page one data of multiple pages of a multiple level cell memory device having a single latch circuit coupled to each bit line, the latch circuit comprising a latch with inverted and non-inverted nodes, a first control transistor coupled between the non-inverted node and a latch output, a second control transistor coupled between the inverted node and the latch output, and a reset transistor coupled between the inverted node and circuit ground, the method comprising: resetting the latch at a first time; biasing a selected word line of the memory device with ground potential at the first time; biasing the selected word line with a read voltage greater than ground potential at a second time; and coupling the non-inverted node to the latch output at the second time to read the page one data.

24. The method of claim 23 wherein resetting the latch comprises coupling the inverted node to circuit ground through the reset transistor.

25. The method of claim 23 wherein coupling comprises turning on the first control transistor with a high signal.

26. A method for reading page zero data of multiple pages of a multiple level cell memory device having a single latch circuit coupled to each bit line, the latch circuit comprising a latch with inverted and non-inverted nodes, a first control transistor coupled between the non-inverted node and a latch output, a second control transistor coupled between the inverted node and the latch output, and a reset transistor coupled between the inverted node and circuit ground, the method comprising: resetting the latch at a first time; biasing a selected word line of the memory device at ground potential at the first time; coupling the non-inverted node to the latch output at a second time; biasing the selected word line at a first read voltage, greater than or equal to ground potential, at the second time; coupling the inverted node to the latch output at a third time; and biasing the selected word line at a second read voltage, greater than the first read voltage, at the third time to read the page zero data.

27. The method of claim 26 wherein the reset transistor is turned on only during the first time.

28. The method of claim 26 wherein the non-inverted node is coupled to the output by turning on the first control transistor and the inverted node is coupled to the output by turning on the second control transistor.

29. The method of claim 26 wherein the first read voltage is between first and second threshold voltage distributions and the second read voltage is between third and fourth threshold voltage distributions.

30. A memory module comprising: a memory device comprising a multiple level memory array arranged in rows and columns such that the rows comprise word lines coupled to control gates of a plurality of memory cells and the columns comprise bit lines coupled to series strings of memory cells, the memory array further arranged in memory blocks, the memory array further comprising: a memory latch circuit coupled to each bit line of the memory array and comprising: a latch having a node and an inverted node; a first transistor coupled between an output and the node; a second transistor coupled between the output and the inverted node; and a reset transistor coupled to the inverted node; a housing for enclosing the memory device; and a plurality of contacts coupled to the housing and configured to provide selective contact between the memory array and a host system.