WO2007072247A3 - An improved lift-off technique suitable for nanometer-scale patterning of metal layers - Google Patents

An improved lift-off technique suitable for nanometer-scale patterning of metal layers Download PDF

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Publication number
WO2007072247A3
WO2007072247A3 PCT/IB2006/054468 IB2006054468W WO2007072247A3 WO 2007072247 A3 WO2007072247 A3 WO 2007072247A3 IB 2006054468 W IB2006054468 W IB 2006054468W WO 2007072247 A3 WO2007072247 A3 WO 2007072247A3
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WO
WIPO (PCT)
Prior art keywords
layer
lift
mask
predefined
deposited
Prior art date
Application number
PCT/IB2006/054468
Other languages
French (fr)
Other versions
WO2007072247A2 (en
Inventor
Ronald Dekker
Francois Neuilly
Vijayaraghavan Madakasira
Stacey N Serafin
Original Assignee
Koninkl Philips Electronics Nv
Ronald Dekker
Francois Neuilly
Vijayaraghavan Madakasira
Stacey N Serafin
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Ronald Dekker, Francois Neuilly, Vijayaraghavan Madakasira, Stacey N Serafin filed Critical Koninkl Philips Electronics Nv
Publication of WO2007072247A2 publication Critical patent/WO2007072247A2/en
Publication of WO2007072247A3 publication Critical patent/WO2007072247A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0331—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers for lift-off processes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Abstract

The present invention relates to a method for forming a metal layer (216) with a predefined lateral shape at a predefined position on a semiconductor substrate (200). The method of the invention provides a novel lift-off process that is suitable in particular for patterning metal layers with lateral extensions in the deep sub-micrometer range, such as gold nanowires. The method uses a layer stack that comprises a first lift-off layer (202), such as silicon dioxide, and a first mask layer (204) on the first lift-off layer for defining the desired lateral shape of the metal layer prior to its deposition. Silicon nitride is an example of a suitable mask-layer material. An opening (208) is formed in the layer stack which has the predefined lateral shape in the first mask layer, forms a first recess (210) in the first lift-off layer and laterally reaches underneath the first mask layer (204), and which exposes a semiconductor surface section (212) at the predefined position. The metal layer (214) is deposited on the exposed semiconductor surface section and on previously deposited layer sections. Finally, the first lift-off layer is removed by etching, thus lifting off the first silicon nitride layer and metal layer sections deposited thereon.
PCT/IB2006/054468 2005-12-22 2006-11-28 An improved lift-off technique suitable for nanometer-scale patterning of metal layers WO2007072247A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05112749.6 2005-12-22
EP05112749 2005-12-22

Publications (2)

Publication Number Publication Date
WO2007072247A2 WO2007072247A2 (en) 2007-06-28
WO2007072247A3 true WO2007072247A3 (en) 2007-10-25

Family

ID=37989197

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2006/054468 WO2007072247A2 (en) 2005-12-22 2006-11-28 An improved lift-off technique suitable for nanometer-scale patterning of metal layers

Country Status (1)

Country Link
WO (1) WO2007072247A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009023371A1 (en) 2009-05-29 2010-12-02 Acandis Gmbh & Co. Kg Method for producing a medical functional element with a self-supporting lattice structure
FR2991885A1 (en) 2012-06-14 2013-12-20 Univ Lorraine PROCESS FOR OBTAINING ENCAPSULATION STRUCTURES
CN106898578B (en) * 2017-03-30 2019-08-06 合肥鑫晟光电科技有限公司 A kind of preparation method of display base plate, array substrate and display device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4256816A (en) * 1977-10-13 1981-03-17 Bell Telephone Laboratories, Incorporated Mask structure for depositing patterned thin films
EP0037040A2 (en) * 1980-03-29 1981-10-07 VLSI Technology Research Association Method of manufacturing a semiconductor device
US4497684A (en) * 1983-02-22 1985-02-05 Amdahl Corporation Lift-off process for depositing metal on a substrate
JPS6038883A (en) * 1983-08-12 1985-02-28 Hitachi Ltd Manufacture of schottky gate type field effect transistor
US4614564A (en) * 1984-12-04 1986-09-30 The United States Of America As Represented By The United States Department Of Energy Process for selectively patterning epitaxial film growth on a semiconductor substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4256816A (en) * 1977-10-13 1981-03-17 Bell Telephone Laboratories, Incorporated Mask structure for depositing patterned thin films
EP0037040A2 (en) * 1980-03-29 1981-10-07 VLSI Technology Research Association Method of manufacturing a semiconductor device
US4497684A (en) * 1983-02-22 1985-02-05 Amdahl Corporation Lift-off process for depositing metal on a substrate
JPS6038883A (en) * 1983-08-12 1985-02-28 Hitachi Ltd Manufacture of schottky gate type field effect transistor
US4614564A (en) * 1984-12-04 1986-09-30 The United States Of America As Represented By The United States Department Of Energy Process for selectively patterning epitaxial film growth on a semiconductor substrate

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
EPHRATH L M ET AL: "LIFT-OFF PROCESS FOR SMALL METAL-METAL SPACINGS", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 22, no. 8B, January 1980 (1980-01-01), pages 3869 - 3870, XP000806529, ISSN: 0018-8689 *
MIURA N ET AL: "FABRICATION OF SUB-MICRON GAP STRUCTURES USING DIRECTLY-DEPOSITED AMORPHOUS CARBON WIRES", JAPANESE JOURNAL OF APPLIED PHYSICS, JAPAN SOCIETY OF APPLIED PHYSICS, TOKYO, JP, vol. 37, no. 4A, PART 1, 1 April 1998 (1998-04-01), pages 2072 - 2073, XP001179891, ISSN: 0021-4922 *

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