WO2007060250A1 - Method and system allowing for indeterminate read data latency in a memory system - Google Patents
Method and system allowing for indeterminate read data latency in a memory system Download PDFInfo
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- WO2007060250A1 WO2007060250A1 PCT/EP2006/068984 EP2006068984W WO2007060250A1 WO 2007060250 A1 WO2007060250 A1 WO 2007060250A1 EP 2006068984 W EP2006068984 W EP 2006068984W WO 2007060250 A1 WO2007060250 A1 WO 2007060250A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1657—Access to multiple memories
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
Definitions
- This invention relates to memory systems and to methods and components that may be provided within a memory system. More particularly, this invention relates to the flow control of read data and the identification of read data returned to a memory controller by hub devices within a memory system.
- a memory system implementing the invention may be comprised of hub devices connected to a memory controller by a daisy chained channel.
- the hub devices may be attached to, or reside upon, memory modules that contain memory devices.
- the memory modules contain a hub device and multiple memory devices.
- the hub device fully buffers command, address and data signals between the memory controller and the memory devices.
- the flow of read data is controlled using either a leveled latency or position dependent latency technique. In both cases, the memory controller is able to predict the return time of read data requested from the memory modules and to schedule commands to avoid collisions as read data is merged onto the controller interface by each memory module.
- the memory controller is able to issue a read data delay adder along with the read command. This instructs the targeted hub device to add additional delay to the return of read data in order to simplify the issuing of commands and to avoid collisions.
- the read data must be returned in the order in which it was requested. Further, the total read data latency must be completely predictable by the memory controller. During run time operations, these two restrictions result in additional gaps being added to packets of read data that are returned from the memory modules. This adds latency to the average read operation.
- hubs are not able to use non-predefined latency techniques (referred to hereafter as 'indeterminate' latency techniques) to return read data faster or slower than normal. These techniques include, but are not limited to, caching read data locally, reading memory devices speculatively, independently managing memory device address pages, data compression, etc.
- a first aspect of the invention provides a method for avoiding limitation to predefined return data times, allowing for indeterminate (i.e. non-predefined) read data latency.
- the method includes determining whether a local data packet has been received. If a local data packet has been received, then the local data packet is stored into a buffer device. The method also includes determining whether the buffer device contains a data packet and determining whether an upstream driver for transmitting data packets to a memory controller via an upstream channel is idle. If the buffer contains a data packet and the upstream driver is idle, then the data packet is transmitted to the upstream driver. The method further includes determining whether an upstream data packet has been received.
- the upstream data packet is in a frame format that includes a frame start indicator and an identification tag for use by the memory controller in associating the upstream data packet with its corresponding read instruction. If an upstream data packet has been received and the upstream driver is not idle, then the upstream data packet is stored into the buffer device. If an upstream data packet has been received and the buffer device does not contain a data packet and the upstream driver is idle, then the upstream data packet is transmitted to the upstream driver. If the upstream driver is not idle, then any data packets in progress continue being transmitted to the upstream driver.
- the hub device includes a device for receiving data packets, an upstream driver for transmitting data packets to a memory controller via an upstream channel and a mechanism including instructions for facilitating indeterminate read data latency.
- the device for receiving data packets includes an upstream receiver for receiving upstream data packets from a downstream hub device and a memory interface for receiving local data packets from a local storage device.
- Each data packet is in a frame format that includes a frame start indicator and an identification tag for use by a memory controller in associating the data packet with its corresponding read instruction.
- the instructions on the mechanism facilitate determining if a local data packet has been received.
- the local data packet is stored into a buffer device.
- the instructions also facilitate determining whether the buffer device contains a data packet and determining whether the upstream driver is idle. If the buffer contains a data packet and the upstream driver is idle, then the data packet is transmitted to the upstream driver.
- the instructions further facilitate determining whether an upstream data packet has been received. If an upstream data packet has been received and the upstream driver is not idle, then the upstream data packet is stored into the buffer device. If an upstream data packet has been received and the buffer device does not contain a data packet and the upstream driver is idle, then the upstream data packet is transmitted to the upstream driver. If the upstream driver is not idle, then any data packets in progress continue being transmitted to the upstream driver.
- a further aspect of the invention provides a memory subsystem with one or more memory modules.
- the memory modules include one or more memory devices connected to a memory controller by a daisy chained channel.
- the read data is returned to the memory controller using a frame format that includes an identification tag and frame start indicator.
- the memory system also includes one or more hub devices on the memory modules for buffering address, commands and data.
- the hub devices include controller channel buffers that are used in conjunction with a preemptive local data merge algorithm to minimize read data latency and enable indeterminate (i.e. non-predefined) read data return times to the memory controller.
- the memory modules include memory devices that are connected to a memory controller by a daisy chained channel.
- the read data is returned to the memory controller using a frame format that includes an identification tag and frame start indicator.
- the memory system also includes one or more hub devices connected to the memory modules for buffering address, commands and data.
- the hub devices include controller channel buffers that are used in conjunction with a preemptive local data merge algorithm to minimize read data latency and enable indeterminate (i.e. non-predefined) read data return times to the memory controller.
- FIG. 1 depicts an exemplary memory system with multiple levels of daisy chained memory modules with point-to-point connections;
- FIG. 2 depicts an exemplary memory system with hub devices that are connected to a memory modules and to a memory controller by a daisy chained channel;
- FIG. 3 depicts a hub logic device that may be utilized by exemplary embodiments ;
- FIG. 4 is a exemplary process flow implemented by the hub logic device in exemplary embodiments.
- FIG. 5 is a read data format that may be utilized by exemplary embodiments .
- Exemplary embodiments utilize controller channel buffers (CCBs) , read data frame formats with identification tags and a preemptive data merge technique to enable minimized and indeterminate read data latency.
- exemplary embodiments allow memory modules to return read data to a memory controller at an unpredicted time.
- Identification tag information is added to the read data packet to indicate the read command that the data is a result of, as well as the hub where the data was read.
- the identification tag information is utilized by the controller to match the read data packet to the read commands issued by the controller. By using the identification tag information, read data can be returned in an order that is different from the issue order of the corresponding read commands.
- Exemplary embodiments also provide a preemptive data merge process to prevent data collisions on the upstream channel when implementing the indeterminate read data latency.
- a CCB is added to the hub device to temporarily store read data.
- the data is transferred from the memory interface to the buffer.
- the hub device detects that an upstream data packet (i.e., a data packet being sent to the controller from a hub device that is downstream from the detecting hub device) is not in the middle of being transferred into the detecting hub device via an upstream channel (it typically takes several transfers to send the entire data packet)
- the detecting hub device checks to see if there is a read data packet in its CCB that is waiting to be sent upstream.
- the hub device If the hub device detects a read data packet in the CCB it drives the read data packet from the CCB onto the upstream data bus. In the meantime, if a new upstream data packet is received via the upstream data bus, the data packet is stored in the CCB on the hub device. In this manner, data packets coming upstream do not collide with data packets being sent upstream from the CCB on the hub device. In the case where there is more than one data packet in the CCB, a variety of methods may be implemented to determine which data packet to send next (e.g., the data packet from the oldest read command may be sent first) .
- Exemplary embodiments apply to memory systems constructed of one or more memory modules 110 that are connected to a memory controller 102 by a daisy chained memory channel 114 as depicted in FIG. 1.
- the memory modules 110 contain both a hub device 112 that buffers commands, address and data signals to and from the controller memory channel 114 as well as one or more memory devices 108 connected to the hub device 112.
- the downstream portion of the memory channel 114, the downstream channel 104 transmits write data and memory operation commands to the hub devices 112.
- the upstream portion of the controller channel 114, the upstream channel 106 returns requested read data (referred to herein as upstream data packets) .
- FIG. 2 depicts an alternate exemplary embodiment that includes a memory system constructed of one or more memory modules 110 connected to hub devices 112 that are further connected to a memory controller 102 by a daisy chained memory channel 114.
- the hub device 112 is not located on the memory module 110; instead the hub device 112 is in communication with the memory module 110.
- the memory modules 110 may be in communication with the hub devices 112 via multi-drop connections and/or point-to-point connections.
- Other hardware configurations are possible, for example exemplary embodiments may utilize only a single level of daisy chained hub devices 112 and/or memory modules 110.
- FIG. 1 depicts an alternate exemplary embodiment that includes a memory system constructed of one or more memory modules 110 connected to hub devices 112 that are further connected to a memory controller 102 by a daisy chained memory channel 114.
- the hub device 112 is not located on the memory module 110; instead the hub device 112 is in communication with the memory module 110.
- the memory modules 110 may be in
- the hub device 112 receives upstream data packets on the upstream channel 104 via the receiver logic 304 (also referred to herein as an upstream receiver) .
- the upstream data packets are data packets being sent to the controller 102 from a hub device 112 that is downstream from the receiving hub device 112.
- An upstream data packet can be sent to the driver logic 306 (also referred to herein as the upstream driver) to be driven towards the controller 102 on the upstream channel 106 or, if the upstream channel 106 is busy, the upstream data packet can be temporarily stored in the CCB 310 on the hub device 112.
- the destination of the upstream data packet is determined by the flow control logic 308 and implemented by sending a signal to the local data mutliplexor 312.
- CCBs 310 reside in the hub device 112 and safely capture upstream data packet transfers (via the receiver logic 304) that are shunted into the CCB 310 while the hub device 112 is merging its local data packets onto the upstream channel 106.
- Local data packets are data packets that are read from memory devices 108 attached to the memory module 110 being directed by the hub device 112. These memory devices 108 are also referred to herein as local storage devices.
- the data read from the local storage devices, the local data packets are formatted for return on an upstream controller interface via the upstream driver and stored in the CCB 310.
- the formatting includes serializing the local data packet into the proper frame format (e.g., see exemplary frame format depicted in FIG. 5) , and inserting values into the identification tag (sourced from the read request), first transfer field, and bus cyclical redundancy code (CRC) field.
- the formatting of the local data packet is performed as part of storing the local data packet into the CCB 310.
- a data packet When a data packet is received at the memory interface 302, it is stored into the CCB 310 while the local data packets are waiting to be merged onto the upstream channel 106 (via the driver logic 306) .
- the identification tag within the data packet allows the memory controller 102 to correlate a returned read data packet with its corresponding read data request command.
- the data packet also contains a small, easy to decode ⁇ start', or first transfer ( ⁇ ft' ) field (also referred to herein as a frame start indicator) delivered near the beginning of an upstream read data frame (data packets are formatted as read data frames) which indicates that a read data frame is present in the data packet. This is used by the flow control logic 308 in the hub device 112 to monitor the channel read data activity.
- the hub device 112 When there is data in the CCBs 310 from either a local read operation or from a previously shunted read data packet from a downstream hub device (the data packets in the CCB are referred to herein as stored data packets), the hub device 112 will merge it onto the upstream channel 106 via the driver logic 306 as soon as it is allowed. The hub device 112 merges local data onto the upstream channel 106 whenever the upstream channel 106 is idle, or immediately following the last transfer of a data packet that is currently in progress.
- Read data frames will never be bisected using this method, but read data frames that are in flight on the upstream channel 106 that have not yet arrived at a hub device's 112 local data multiplexer 312 may be preempted and shunted into the CCB 310. This allows gaps in read data on the upstream channel 106 to be minimized which increases bus efficiency and results in reduced average read data latency under real world work load conditions.
- the hub device 112 can be configured to send the read data packet corresponding to the earliest read command. This minimizes undue latency on read requests issued to hub devices 112 that are many daisy chain positions away from the memory controller 102.
- Other CCB 310 unload prio ⁇ tization algorithms may also be implemented.
- the identification tag field of the read data frame may contain a priority field. The priority field can be used to guide the unloading of the CCBs 310. Alternatively, priority information may be delivered as the read data is requested. Hub devices 112 can then compare the identification tag to previously recorded priority information to determine the location in the CCB 310 to send next.
- a method may also be employed that occasionally sends lower priority data before high priority data to ensure that low priority data is not completely stalled by requests that have been tagged with a higher priority.
- FIG. 4 is a process flow that is facilitated by the flow control logic 308 located in the hub device 112 in exemplary embodiments.
- the process depicted in FIG. 4 performs preemptive local data merge and may be implemented by a mechanism including hardware and/or software instructions such as a finite state machine in the flow control logic 308.
- the process starts at block 402 and is repeated, in exemplary embodiments, on a periodic basis (e.g., after each controller channel transfer, or upstream channel cycle).
- any local read data packets i.e., from memory devices 108 on memory modules 110 attached to the hub device 112 are loaded into the CCB 310. This insures that the flow control logic 308 is aware of and managing the upstream driving of local read data.
- the data is routed from the receiver logic 304 to the driver logic 306 at block 412.
- the routing is directed by the flow control logic 308 by setting the local data multiplexer 312 to send the upstream data packet to the driver logic 306 for driving the upstream data packet onto the upstream channel 106 towards the controller 102.
- Processing then continues at 414, where processing is sent back to block 404 at the next upstream channel cycle.
- block 408 is performed to determine if an upstream channel operation is in process (i.e., is an upstream data packet or a local read data packet in the middle of being driven onto the upstream channel 106 via the driver logic 306) . Processing continues at block 412 if an upstream channel operation is in process (i.e., the driver is busy) . At block 412, upstream read data packets are routed from the receiver logic 304 to the driver logic 306 by setting the local data multiplexer 312 to send the upstream data packet to the driver logic 306.
- processing continues at block 410 if an upstream channel operation is not in process (i.e., the driver is idle) and there is data in the CCB 310.
- data from the CCB 310 is driven onto the upstream channel 106 while any data packets received in the receiver logic 304 from the upstream channel 106 are shunted (stored) into the next available CCB 310 location.
- the shunting is performed by the flow control logic 308 directing the upstream data packets to be loaded into the CCB 310.
- Processing then continues at 414 which sends processing back to block 404 at the next upstream channel cycle.
- FIG. 5 is an exemplary read data frame format for upstream data packets and local read data packets on the upstream channel 106.
- the frame format depicted in FIG. 5 uses twenty-one signal lanes and each packet includes sixteen transfers. It includes a one bit first start indicator 502 and an identification tag 504, as well as 256 bits (32B) of read data 506 with a bus CRCs 508 for transmission error detection.
- Other combinations of signal lanes and transfer depths can be used to create frame formats that include a frame start indicator, read data identification tag and read data that are compatible with this invention.
- Exemplary embodiments pertain to a computer memory system constructed of daisy chained hub logic devices connected to, or contained upon, memory modules.
- the hubs are daisy chained on a memory controller channel and are further attached to memory devices on the memory modules.
- the memory controller issues requests for read data to the hubs which merge this read data from the memory modules onto the memory channel.
- the hubs are able to return read data at a time unpredicted by the memory controller, and at a time that may preempt a read request that had been issued earlier, without loosing or corrupting any of the read data returned on the channel to the memory controller.
- Exemplary embodiments may be utilized to optimize average read data latency by more fully utilizing the upstream channel.
- CCBs read data frame formats with identification tags and a preemptive data merge technique, indeterminate read data latency may be performed to more fully utilize the controller channel.
- the embodiments of the invention may be embodied in the form of computer-implemented processes and apparatuses for practicing those processes.
- Embodiments of the invention may also be embodied in the form of computer program code containing instructions embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other computer-readable storage medium, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention.
- the present invention can also be embodied in the form of computer program code, for example, whether stored in a storage medium, loaded into and/or executed by a computer, or transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via electromagnetic radiation, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention.
- computer program code segments configure the microprocessor to create specific logic circuits.
Abstract
Provided are a method and system for providing indeterminate read data latency in a memory system. The method includes determining whether a local data packet has been received. If a local data packet has been received, then the local data packet is stored into a buffer device. The method also includes determining whether the buffer device contains a data packet and determining whether an upstream driver for transmitting data packets to a memory controller via an upstream channel is idle. If the buffer contains a data packet and the upstream driver is idle, then the data packet is transmitted to the upstream driver. The method further includes determining whether an upstream data packet has been received. The upstream data packet is in a frame format that includes a frame start indicator and an identification tag for use by the memory controller in associating the upstream data packet with its corresponding read instruction. If an upstream data packet has been received and the upstream driver is not idle, then the upstream data packet is stored into the buffer device. If an upstream data packet has been received and the buffer device does not contain a data packet and the upstream driver is idle, then the upstream data packet is transmitted to the upstream driver. If the upstream driver is not idle, then any data packets in progress continue being transmitted to the upstream driver.
Description
METHOD AND SYSTEM ALLOWING FOR INDETERMINATE READ DATA LATENCY IN A MEMORY SYSTEM
FIELD OF THE INVENTION
This invention relates to memory systems and to methods and components that may be provided within a memory system. More particularly, this invention relates to the flow control of read data and the identification of read data returned to a memory controller by hub devices within a memory system.
BACKGROUND
A memory system implementing the invention may be comprised of hub devices connected to a memory controller by a daisy chained channel. The hub devices may be attached to, or reside upon, memory modules that contain memory devices.
Many high performance computing main memory systems use multiple fully buffered memory modules connected to a memory controller by one or more channels. The memory modules contain a hub device and multiple memory devices. The hub device fully buffers command, address and data signals between the memory controller and the memory devices. The flow of read data is controlled using either a leveled latency or position dependent latency technique. In both cases, the memory controller is able to predict the return time of read data requested from the memory modules and to schedule commands to avoid collisions as read data is merged onto the controller interface by each memory module.
In some cases, the memory controller is able to issue a read data delay adder along with the read command. This instructs the targeted hub device to add additional delay to the return of read data in order to simplify the issuing of commands and to avoid collisions. In all cases, the read data must be returned in the order in which it was requested. Further, the total read data latency must be completely predictable by the memory controller. During run time operations, these two restrictions result in additional gaps being added to packets of read data that are returned from the memory modules. This adds latency to the average read operation. In addition, hubs are not able to use non-predefined latency techniques (referred to hereafter as 'indeterminate' latency techniques) to return read data faster or slower than normal. These techniques
include, but are not limited to, caching read data locally, reading memory devices speculatively, independently managing memory device address pages, data compression, etc.
To optimize average read data latency under real workload conditions, and to enable advanced hub device capabilities, what is needed is a way to allow memory modules to return read data to the memory controller at an unpredicted time. This must be done in a way that does not corrupt read data and that allows the memory controller to identify each read data packet. Preventing data corruption by avoiding data collisions is especially complicated as hub devices merge local read data onto a cascaded memory controller channel.
SUMMARY OF THE INVENTION
A first aspect of the invention provides a method for avoiding limitation to predefined return data times, allowing for indeterminate (i.e. non-predefined) read data latency. In one embodiment, the method includes determining whether a local data packet has been received. If a local data packet has been received, then the local data packet is stored into a buffer device. The method also includes determining whether the buffer device contains a data packet and determining whether an upstream driver for transmitting data packets to a memory controller via an upstream channel is idle. If the buffer contains a data packet and the upstream driver is idle, then the data packet is transmitted to the upstream driver. The method further includes determining whether an upstream data packet has been received. The upstream data packet is in a frame format that includes a frame start indicator and an identification tag for use by the memory controller in associating the upstream data packet with its corresponding read instruction. If an upstream data packet has been received and the upstream driver is not idle, then the upstream data packet is stored into the buffer device. If an upstream data packet has been received and the buffer device does not contain a data packet and the upstream driver is idle, then the upstream data packet is transmitted to the upstream driver. If the upstream driver is not idle, then any data packets in progress continue being transmitted to the upstream driver.
Another aspect of the invention provides a hub device in a memory system. According to one embodiment, the hub device includes a device for receiving data packets, an upstream driver for transmitting data packets
to a memory controller via an upstream channel and a mechanism including instructions for facilitating indeterminate read data latency. The device for receiving data packets includes an upstream receiver for receiving upstream data packets from a downstream hub device and a memory interface for receiving local data packets from a local storage device. Each data packet is in a frame format that includes a frame start indicator and an identification tag for use by a memory controller in associating the data packet with its corresponding read instruction. The instructions on the mechanism facilitate determining if a local data packet has been received. If a local data packet has been received, then the local data packet is stored into a buffer device. The instructions also facilitate determining whether the buffer device contains a data packet and determining whether the upstream driver is idle. If the buffer contains a data packet and the upstream driver is idle, then the data packet is transmitted to the upstream driver. The instructions further facilitate determining whether an upstream data packet has been received. If an upstream data packet has been received and the upstream driver is not idle, then the upstream data packet is stored into the buffer device. If an upstream data packet has been received and the buffer device does not contain a data packet and the upstream driver is idle, then the upstream data packet is transmitted to the upstream driver. If the upstream driver is not idle, then any data packets in progress continue being transmitted to the upstream driver.
A further aspect of the invention provides a memory subsystem with one or more memory modules. In one embodiment, the memory modules include one or more memory devices connected to a memory controller by a daisy chained channel. The read data is returned to the memory controller using a frame format that includes an identification tag and frame start indicator. The memory system also includes one or more hub devices on the memory modules for buffering address, commands and data. The hub devices include controller channel buffers that are used in conjunction with a preemptive local data merge algorithm to minimize read data latency and enable indeterminate (i.e. non-predefined) read data return times to the memory controller.
Another aspect of the invention provides a memory system with one or more memory modules. In one embodiment, the memory modules include memory devices that are connected to a memory controller by a daisy chained channel. The read data is returned to the memory controller using a frame format that includes an identification tag and frame start indicator. The memory system also includes one or more hub devices connected to the
memory modules for buffering address, commands and data. The hub devices include controller channel buffers that are used in conjunction with a preemptive local data merge algorithm to minimize read data latency and enable indeterminate (i.e. non-predefined) read data return times to the memory controller.
BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments of the invention are described below in more detail, by way of example, with reference to the accompanying drawings in which like elements are numbered alike and in which:
FIG. 1 depicts an exemplary memory system with multiple levels of daisy chained memory modules with point-to-point connections;
FIG. 2 depicts an exemplary memory system with hub devices that are connected to a memory modules and to a memory controller by a daisy chained channel;
FIG. 3 depicts a hub logic device that may be utilized by exemplary embodiments ;
FIG. 4 is a exemplary process flow implemented by the hub logic device in exemplary embodiments; and
FIG. 5 is a read data format that may be utilized by exemplary embodiments .
DETAILED DESCRIPTION OF EMBODIMENTS
Exemplary embodiments utilize controller channel buffers (CCBs) , read data frame formats with identification tags and a preemptive data merge technique to enable minimized and indeterminate read data latency. Exemplary embodiments allow memory modules to return read data to a memory controller at an unpredicted time. Identification tag information is added to the read data packet to indicate the read command that the data is a result of, as well as the hub where the data was read. The identification tag information is utilized by the controller to match the read data packet to the read commands issued by the controller. By using the identification tag information, read data can be returned in an order that is different from the issue order of the corresponding read commands.
Exemplary embodiments also provide a preemptive data merge process to prevent data collisions on the upstream channel when implementing the indeterminate read data latency. A CCB is added to the hub device to temporarily store read data. When a memory device on the memory module
reads data, the data is transferred from the memory interface to the buffer. When the hub device detects that an upstream data packet (i.e., a data packet being sent to the controller from a hub device that is downstream from the detecting hub device) is not in the middle of being transferred into the detecting hub device via an upstream channel (it typically takes several transfers to send the entire data packet) , the detecting hub device checks to see if there is a read data packet in its CCB that is waiting to be sent upstream. If the hub device detects a read data packet in the CCB it drives the read data packet from the CCB onto the upstream data bus. In the meantime, if a new upstream data packet is received via the upstream data bus, the data packet is stored in the CCB on the hub device. In this manner, data packets coming upstream do not collide with data packets being sent upstream from the CCB on the hub device. In the case where there is more than one data packet in the CCB, a variety of methods may be implemented to determine which data packet to send next (e.g., the data packet from the oldest read command may be sent first) .
Exemplary embodiments apply to memory systems constructed of one or more memory modules 110 that are connected to a memory controller 102 by a daisy chained memory channel 114 as depicted in FIG. 1. The memory modules 110 contain both a hub device 112 that buffers commands, address and data signals to and from the controller memory channel 114 as well as one or more memory devices 108 connected to the hub device 112. The downstream portion of the memory channel 114, the downstream channel 104, transmits write data and memory operation commands to the hub devices 112. The upstream portion of the controller channel 114, the upstream channel 106, returns requested read data (referred to herein as upstream data packets) .
FIG. 2 depicts an alternate exemplary embodiment that includes a memory system constructed of one or more memory modules 110 connected to hub devices 112 that are further connected to a memory controller 102 by a daisy chained memory channel 114. In this embodiment, the hub device 112 is not located on the memory module 110; instead the hub device 112 is in communication with the memory module 110. As depicted in FIG. 2, the memory modules 110 may be in communication with the hub devices 112 via multi-drop connections and/or point-to-point connections. Other hardware configurations are possible, for example exemplary embodiments may utilize only a single level of daisy chained hub devices 112 and/or memory modules 110.
FIG. 3 depicts a hub device 112 with flow control logic 308 utilized by exemplary embodiments to perform the processing described herein. The hub device 112 and the components within the hub device 112 may be implemented in hardware and/or software. The hub device 112 receives upstream data packets on the upstream channel 104 via the receiver logic 304 (also referred to herein as an upstream receiver) . The upstream data packets are data packets being sent to the controller 102 from a hub device 112 that is downstream from the receiving hub device 112. An upstream data packet can be sent to the driver logic 306 (also referred to herein as the upstream driver) to be driven towards the controller 102 on the upstream channel 106 or, if the upstream channel 106 is busy, the upstream data packet can be temporarily stored in the CCB 310 on the hub device 112. The destination of the upstream data packet is determined by the flow control logic 308 and implemented by sending a signal to the local data mutliplexor 312.
In exemplary embodiments, CCBs 310, or buffer devices, reside in the hub device 112 and safely capture upstream data packet transfers (via the receiver logic 304) that are shunted into the CCB 310 while the hub device 112 is merging its local data packets onto the upstream channel 106.
Local data packets are data packets that are read from memory devices 108 attached to the memory module 110 being directed by the hub device 112. These memory devices 108 are also referred to herein as local storage devices. The data read from the local storage devices, the local data packets, are formatted for return on an upstream controller interface via the upstream driver and stored in the CCB 310. The formatting includes serializing the local data packet into the proper frame format (e.g., see exemplary frame format depicted in FIG. 5) , and inserting values into the identification tag (sourced from the read request), first transfer field, and bus cyclical redundancy code (CRC) field. In exemplary embodiments, the formatting of the local data packet is performed as part of storing the local data packet into the CCB 310.
When a data packet is received at the memory interface 302, it is stored into the CCB 310 while the local data packets are waiting to be merged onto the upstream channel 106 (via the driver logic 306) . The identification tag within the data packet allows the memory controller 102 to correlate a returned read data packet with its corresponding read data request command. The data packet also contains a small, easy to decode λstart', or first transfer ( λft' ) field (also referred to herein as a frame start indicator) delivered near the beginning of an upstream read
data frame (data packets are formatted as read data frames) which indicates that a read data frame is present in the data packet. This is used by the flow control logic 308 in the hub device 112 to monitor the channel read data activity.
When there is data in the CCBs 310 from either a local read operation or from a previously shunted read data packet from a downstream hub device (the data packets in the CCB are referred to herein as stored data packets), the hub device 112 will merge it onto the upstream channel 106 via the driver logic 306 as soon as it is allowed. The hub device 112 merges local data onto the upstream channel 106 whenever the upstream channel 106 is idle, or immediately following the last transfer of a data packet that is currently in progress. Read data frames will never be bisected using this method, but read data frames that are in flight on the upstream channel 106 that have not yet arrived at a hub device's 112 local data multiplexer 312 may be preempted and shunted into the CCB 310. This allows gaps in read data on the upstream channel 106 to be minimized which increases bus efficiency and results in reduced average read data latency under real world work load conditions.
When there are multiple read data packets present in the CCBs 310, the hub device 112 can be configured to send the read data packet corresponding to the earliest read command. This minimizes undue latency on read requests issued to hub devices 112 that are many daisy chain positions away from the memory controller 102. Other CCB 310 unload prioπtization algorithms may also be implemented. For example, the identification tag field of the read data frame may contain a priority field. The priority field can be used to guide the unloading of the CCBs 310. Alternatively, priority information may be delivered as the read data is requested. Hub devices 112 can then compare the identification tag to previously recorded priority information to determine the location in the CCB 310 to send next. A method may also be employed that occasionally sends lower priority data before high priority data to ensure that low priority data is not completely stalled by requests that have been tagged with a higher priority.
FIG. 4 is a process flow that is facilitated by the flow control logic 308 located in the hub device 112 in exemplary embodiments. The process depicted in FIG. 4 performs preemptive local data merge and may be implemented by a mechanism including hardware and/or software instructions such as a finite state machine in the flow control logic 308. The process
starts at block 402 and is repeated, in exemplary embodiments, on a periodic basis (e.g., after each controller channel transfer, or upstream channel cycle). At block 404 any local read data packets (i.e., from memory devices 108 on memory modules 110 attached to the hub device 112) in the memory interface 302 are loaded into the CCB 310. This insures that the flow control logic 308 is aware of and managing the upstream driving of local read data. At block 406, it is determined if there is data in the CCB 310. If there is no data in the CCB 310, then the data is routed from the receiver logic 304 to the driver logic 306 at block 412. The routing is directed by the flow control logic 308 by setting the local data multiplexer 312 to send the upstream data packet to the driver logic 306 for driving the upstream data packet onto the upstream channel 106 towards the controller 102. Processing then continues at 414, where processing is sent back to block 404 at the next upstream channel cycle.
If it is determined at block 406, that there is data in the CCB 310 then block 408 is performed to determine if an upstream channel operation is in process (i.e., is an upstream data packet or a local read data packet in the middle of being driven onto the upstream channel 106 via the driver logic 306) . Processing continues at block 412 if an upstream channel operation is in process (i.e., the driver is busy) . At block 412, upstream read data packets are routed from the receiver logic 304 to the driver logic 306 by setting the local data multiplexer 312 to send the upstream data packet to the driver logic 306. Alternatively, processing continues at block 410 if an upstream channel operation is not in process (i.e., the driver is idle) and there is data in the CCB 310. At block 410, data from the CCB 310 is driven onto the upstream channel 106 while any data packets received in the receiver logic 304 from the upstream channel 106 are shunted (stored) into the next available CCB 310 location. The shunting is performed by the flow control logic 308 directing the upstream data packets to be loaded into the CCB 310. Processing then continues at 414 which sends processing back to block 404 at the next upstream channel cycle.
FIG. 5 is an exemplary read data frame format for upstream data packets and local read data packets on the upstream channel 106. The frame format depicted in FIG. 5 uses twenty-one signal lanes and each packet includes sixteen transfers. It includes a one bit first start indicator 502 and an identification tag 504, as well as 256 bits (32B) of read data 506 with a bus CRCs 508 for transmission error detection. Other combinations of signal lanes and transfer depths can be used to create
frame formats that include a frame start indicator, read data identification tag and read data that are compatible with this invention.
Exemplary embodiments pertain to a computer memory system constructed of daisy chained hub logic devices connected to, or contained upon, memory modules. The hubs are daisy chained on a memory controller channel and are further attached to memory devices on the memory modules. The memory controller issues requests for read data to the hubs which merge this read data from the memory modules onto the memory channel. Using channel buffers and packet identification tags, the hubs are able to return read data at a time unpredicted by the memory controller, and at a time that may preempt a read request that had been issued earlier, without loosing or corrupting any of the read data returned on the channel to the memory controller.
Exemplary embodiments may be utilized to optimize average read data latency by more fully utilizing the upstream channel. Through the use of CCBs, read data frame formats with identification tags and a preemptive data merge technique, indeterminate read data latency may be performed to more fully utilize the controller channel.
As described above, the embodiments of the invention may be embodied in the form of computer-implemented processes and apparatuses for practicing those processes. Embodiments of the invention may also be embodied in the form of computer program code containing instructions embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other computer-readable storage medium, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention. The present invention can also be embodied in the form of computer program code, for example, whether stored in a storage medium, loaded into and/or executed by a computer, or transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via electromagnetic radiation, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention. When implemented on a general-purpose microprocessor, the computer program code segments configure the microprocessor to create specific logic circuits.
While the invention has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that
various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims. Moreover, the use of the terms first, second, etc. do not denote any order or importance, but rather the terms first, second, etc. are used to distinguish one element from another.
Claims
1. A method for supporting indeterminate read data latency, the method comprising : determining whether a local data packet has been received; if a local data packet has been received, then storing the local data packet into a buffer device; determining whether the buffer device contains a data packet; determining whether an upstream driver for transmitting data packets to a memory controller via an upstream channel is idle; if the buffer device contains a data packet and the upstream driver is idle, then transmitting the data packet to the upstream driver; determining whether an upstream data packet has been received, the upstream data packet in a frame format that includes a frame start indicator and an identification tag for use by the memory controller in associating the upstream data packet with its corresponding read instruction; if an upstream data packet has been received and the upstream driver is not idle, then storing the upstream data packet into the buffer device; if an upstream data packet has been received and the buffer device does not contain a data packet and the upstream driver is idle, then transmitting the upstream data packet to the upstream driver; and if the upstream driver is not idle, continuing to transmit any data packets that are in progress.
2. The method of claim 1 wherein the determining whether a local data packet has been received, the determining whether the buffer device contains a data packet, the determining whether an upstream driver is idle and the determining whether a data packet has been received are performed on a periodic basis.
3. The method of claim 2 wherein the periodic basis is once every upstream channel cycle.
4. The method of claim 1 wherein the buffer device contains a plurality of data packets and the data packet is selected based on a prioπtization algorithm.
5. The method of claim 4 wherein the prioπtization algorithm selects the data packet based on the age of the read instruction that corresponds to the data packet.
6. The method of claim 4 wherein the prioπtization algorithm selects the data packet based on a priority associated with the data packet.
7. The method of claim 1 wherein the frame format further includes a bus cyclical redundancy code (CRC) field.
8. The method of claim 7 wherein the storing the local data packet into a buffer device includes formatting the local data packet, the formatting including serializing the local data packet into the frame format and inserting values into the frame start indicator, the identification tag and the bus CRC.
9. A hub device in a memory system, the hub device comprising: a device for receiving data packets, the device including an upstream receiver for receiving upstream data packets from a downstream hub device and a memory interface for receiving local data packets from a local storage device, wherein each data packet is in a frame format that includes a frame start indicator and an identification tag for use by a memory controller in associating the data packet with its corresponding read instruction; an upstream driver for transmitting the data packets to the memory controller via an upstream channel; and a mechanism including instructions for facilitating: determining whether a local data packet has been received; if a local data packet has been received, then storing the local data packet into a buffer device; determining whether the buffer device contains a data packet; determining whether the upstream driver is idle; if the buffer device contains a data packet and the upstream driver is idle, then transmitting the data packet to the upstream driver; determining whether an upstream data packet has been received, the upstream data packet in a frame format that includes a frame start indicator and an identification tag for use by the memory controller in associating the upstream data packet with its corresponding read instruction; if an upstream data packet has been received and the upstream driver is not idle, then storing the upstream data packet into the buffer device; if an upstream data packet has been received and the buffer device does not contain a data packet and the upstream driver is idle, then transmitting the upstream data packet to the upstream driver; and if the upstream driver is not idle, continuing to transmit any data packets for which transmission is in progress.
10. The hub device of claim 9 wherein the upstream channel is a daisy chain channel.
11. The hub device of claim 9 wherein the hub device is physically located on a memory module.
12. The hub device of claim 9 further comprising the buffer device.
13. The hub device of claim 9 wherein the determining whether a local data packet has been received, the determining whether the buffer device contains a data packet, the determining whether an upstream driver is idle and the determining whether a data packet has been received are performed on a periodic basis.
14. The hub device of claim 13 wherein the periodic basis is once every upstream channel cycle.
15. The hub device of claim 9 wherein the buffer device contains a plurality of data packets and the data packet is selected based on a prioπtization algorithm.
16. The hub device of claim 15 wherein the prioπtization algorithm selects the data packet based on the age of the read instruction that corresponds to the data packet.
17. The hub device of claim 15 wherein the prioπtization algorithm selects the data packet based on a priority associated with the data packet .
18. A memory system comprising: one or more memory modules with one or more memory devices connected to a memory controller by a daisy chained channel, wherein the read data is returned to the memory controller using a frame format that includes an identification tag and frame start indicator; and
one or more hub devices on the memory modules for buffering address, commands and data, the hub devices including controller channel buffers used in conjunction with a preemptive local data merge algorithm to minimize read data latency and enable indeterminate read data return times to the memory controller.
19. The memory system of claim 18 including point-to-point links in the daisy chained channel.
20. The memory system of claim 18 wherein the hub device further includes a controller channel buffer unload prioπtization algorithm.
21. The memory system of claim 18 wherein the preemptive local data merge algorithm comprises: determining whether a local data packet has been received; if a local data packet has been received, then storing the local data packet into a buffer device located in the controller channel buffers; determining whether the buffer device contains a data packet; determining whether an upstream driver for transmitting data packets to the memory controller via an upstream channel is idle; if the buffer device contains a data packet and the upstream driver is idle, then transmitting the data packet to the upstream driver; determining whether an upstream data packet has been received; if an upstream data packet has been received and the upstream driver is not idle, then storing the upstream data packet into the buffer device; if an upstream data packet has been received and the buffer device does not contain a data packet and the upstream driver is idle, then transmitting the upstream data packet to the upstream driver; and if the upstream driver is not idle, continuing to transmit any data packets for which transmission is in progress.
22. A memory system comprising: one or more memory modules with one or more memory devices connected to a memory controller by a daisy chained channel, wherein the read data is returned to the memory controller using a frame format that includes an identification tag and frame start indicator; and one or more hub devices connected to the memory modules for buffering address, commands and data, the hub devices including controller channel buffers used in conjunction with a preemptive local data merge algorithm to minimize read data latency and enable indeterminate read data return times to the memory controller.
23. The memory system of claim 22 including point-to-point links in the daisy chained channel.
24. The memory system of claim 22 wherein the hub device further includes a controller channel buffer unload prioπtization algorithm.
25. The memory system of claim 22 wherein the preemptive local data merge algorithm comprises: determining whether a local data packet has been received; if a local data packet has been received, then storing the local data packet into a buffer device located in the controller channel buffers; determining whether the buffer device contains a data packet; determining whether an upstream driver for transmitting data packets to the memory controller via an upstream channel is idle; if the buffer device contains a data packet and the upstream driver is idle, then transmitting the data packet to the upstream driver; determining whether an upstream data packet has been received; if an upstream data packet has been received and the upstream driver is not idle, then storing the upstream data packet into the buffer device; if an upstream data packet has been received and the buffer device does not contain a data packet and the upstream driver is idle, then transmitting the upstream data packet to the upstream driver; and if the upstream driver is not idle, continuing to transmit any data packets for which transmission is in progress.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008541760A JP5186382B2 (en) | 2005-11-28 | 2006-11-28 | Method and system for enabling indeterminate read data latency in a memory system |
CN2006800412429A CN101300556B (en) | 2005-11-28 | 2006-11-28 | Method and system allowing for indeterminate read data latency in a memory system |
EP06819806A EP1958073A1 (en) | 2005-11-28 | 2006-11-28 | Method and system allowing for indeterminate read data latency in a memory system |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/289,193 | 2005-11-28 | ||
US11/289,193 US7685392B2 (en) | 2005-11-28 | 2005-11-28 | Providing indeterminate read data latency in a memory system |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2007060250A1 true WO2007060250A1 (en) | 2007-05-31 |
Family
ID=37698119
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2006/068984 WO2007060250A1 (en) | 2005-11-28 | 2006-11-28 | Method and system allowing for indeterminate read data latency in a memory system |
Country Status (6)
Country | Link |
---|---|
US (6) | US7685392B2 (en) |
EP (1) | EP1958073A1 (en) |
JP (1) | JP5186382B2 (en) |
CN (1) | CN101300556B (en) |
TW (1) | TWI399649B (en) |
WO (1) | WO2007060250A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011505036A (en) * | 2007-11-26 | 2011-02-17 | スパンション エルエルシー | Storage system and method |
Families Citing this family (51)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7296129B2 (en) * | 2004-07-30 | 2007-11-13 | International Business Machines Corporation | System, method and storage medium for providing a serialized memory interface with a bus repeater |
US7512762B2 (en) | 2004-10-29 | 2009-03-31 | International Business Machines Corporation | System, method and storage medium for a memory subsystem with positional read data latency |
US7331010B2 (en) | 2004-10-29 | 2008-02-12 | International Business Machines Corporation | System, method and storage medium for providing fault detection and correction in a memory subsystem |
US7299313B2 (en) | 2004-10-29 | 2007-11-20 | International Business Machines Corporation | System, method and storage medium for a memory subsystem command interface |
US7478259B2 (en) | 2005-10-31 | 2009-01-13 | International Business Machines Corporation | System, method and storage medium for deriving clocks in a memory system |
US7577039B2 (en) * | 2005-11-16 | 2009-08-18 | Montage Technology Group, Ltd. | Memory interface to bridge memory buses |
US7368950B2 (en) * | 2005-11-16 | 2008-05-06 | Montage Technology Group Limited | High speed transceiver with low power consumption |
US7558124B2 (en) * | 2005-11-16 | 2009-07-07 | Montage Technology Group, Ltd | Memory interface to bridge memory buses |
US7685392B2 (en) | 2005-11-28 | 2010-03-23 | International Business Machines Corporation | Providing indeterminate read data latency in a memory system |
JP5065618B2 (en) * | 2006-05-16 | 2012-11-07 | 株式会社日立製作所 | Memory module |
US7640386B2 (en) * | 2006-05-24 | 2009-12-29 | International Business Machines Corporation | Systems and methods for providing memory modules with multiple hub devices |
US7345900B2 (en) * | 2006-07-26 | 2008-03-18 | International Business Machines Corporation | Daisy chained memory system |
US7345901B2 (en) * | 2006-07-26 | 2008-03-18 | International Business Machines Corporation | Computer system having daisy chained self timed memory chips |
US7669086B2 (en) | 2006-08-02 | 2010-02-23 | International Business Machines Corporation | Systems and methods for providing collision detection in a memory system |
US7870459B2 (en) | 2006-10-23 | 2011-01-11 | International Business Machines Corporation | High density high reliability memory module with power gating and a fault tolerant address and command bus |
US7721140B2 (en) | 2007-01-02 | 2010-05-18 | International Business Machines Corporation | Systems and methods for improving serviceability of a memory system |
US20080298468A1 (en) * | 2007-06-04 | 2008-12-04 | Mediaphy Corporation | Error tagging for decoder |
US8332572B2 (en) | 2008-02-05 | 2012-12-11 | Spansion Llc | Wear leveling mechanism using a DRAM buffer |
US20100005218A1 (en) * | 2008-07-01 | 2010-01-07 | International Business Machines Corporation | Enhanced cascade interconnected memory system |
US7969985B1 (en) * | 2008-09-03 | 2011-06-28 | Motion Engineering, Inc. | Method and system for scheduling, transporting, and receiving inbound packets efficiently in networks with cyclic packet scheduling |
DE102008050102B4 (en) * | 2008-10-06 | 2010-11-04 | Phoenix Contact Gmbh & Co. Kg | Communication entity for communication via a bus-oriented communication network |
US20100122003A1 (en) * | 2008-11-10 | 2010-05-13 | Nec Laboratories America, Inc. | Ring-based high speed bus interface |
US8472199B2 (en) * | 2008-11-13 | 2013-06-25 | Mosaid Technologies Incorporated | System including a plurality of encapsulated semiconductor chips |
CN101425052B (en) * | 2008-12-04 | 2010-06-09 | 中国科学院计算技术研究所 | Method for implementing transactional memory |
US9123409B2 (en) | 2009-06-11 | 2015-09-01 | Micron Technology, Inc. | Memory device for a hierarchical memory architecture |
JP5372687B2 (en) * | 2009-09-30 | 2013-12-18 | ソニー株式会社 | Transmitting apparatus, transmitting method, receiving apparatus, and receiving method |
US8327052B2 (en) | 2009-12-23 | 2012-12-04 | Spansion Llc | Variable read latency on a serial memory bus |
US8549378B2 (en) | 2010-06-24 | 2013-10-01 | International Business Machines Corporation | RAIM system using decoding of virtual ECC |
US8898511B2 (en) | 2010-06-24 | 2014-11-25 | International Business Machines Corporation | Homogeneous recovery in a redundant memory system |
US8631271B2 (en) | 2010-06-24 | 2014-01-14 | International Business Machines Corporation | Heterogeneous recovery in a redundant memory system |
US8484529B2 (en) | 2010-06-24 | 2013-07-09 | International Business Machines Corporation | Error correction and detection in a redundant memory system |
TWI462103B (en) * | 2011-01-19 | 2014-11-21 | Mstar Semiconductor Inc | Controller and controlling method for memory and memory system |
US8522122B2 (en) | 2011-01-29 | 2013-08-27 | International Business Machines Corporation | Correcting memory device and memory channel failures in the presence of known memory device failures |
CN103164366A (en) * | 2011-12-09 | 2013-06-19 | 鸿富锦精密工业(深圳)有限公司 | Electronic equipment provided with universal input and output expander and signal detecting method |
US8880819B2 (en) | 2011-12-13 | 2014-11-04 | Micron Technology, Inc. | Memory apparatuses, computer systems and methods for ordering memory responses |
US8938656B2 (en) | 2012-09-14 | 2015-01-20 | Sandisk Technologies Inc. | Data storage device with intermediate ECC stage |
US9424314B2 (en) * | 2012-10-19 | 2016-08-23 | Oracle International Corporation | Method and apparatus for joining read requests |
US9081700B2 (en) * | 2013-05-16 | 2015-07-14 | Western Digital Technologies, Inc. | High performance read-modify-write system providing line-rate merging of dataframe segments in hardware |
CN105531766A (en) | 2013-10-15 | 2016-04-27 | 拉姆伯斯公司 | Load reduced memory module |
WO2015070245A1 (en) | 2013-11-11 | 2015-05-14 | Rambus Inc. | High capacity memory system using standard controller component |
USD733145S1 (en) * | 2014-03-14 | 2015-06-30 | Kingston Digital, Inc. | Memory module |
USD735201S1 (en) * | 2014-07-30 | 2015-07-28 | Kingston Digital, Inc. | Memory module |
CN112687304A (en) | 2014-12-19 | 2021-04-20 | 拉姆伯斯公司 | Dynamic Random Access Memory (DRAM) components for memory modules |
AT14695U1 (en) * | 2015-01-19 | 2016-04-15 | Bachmann Gmbh | Serial bus system with coupling modules |
KR102425470B1 (en) * | 2015-04-06 | 2022-07-27 | 에스케이하이닉스 주식회사 | Data storage device and operating method thereof |
CN107122134B (en) * | 2017-04-25 | 2020-01-03 | 杭州迪普科技股份有限公司 | Data reading method and device |
US10970239B2 (en) * | 2018-03-16 | 2021-04-06 | Intel Corporation | Hub circuit for a DIMM having multiple components that communicate with a host |
KR102242523B1 (en) * | 2018-04-16 | 2021-04-21 | 엘지전자 주식회사 | Apparatus and method for transmitting data stream in wireless power transmission system |
US11178055B2 (en) | 2019-06-14 | 2021-11-16 | Intel Corporation | Methods and apparatus for providing deterministic latency for communications interfaces |
US11258755B2 (en) * | 2019-09-19 | 2022-02-22 | GM Global Technology Operations LLC | Method and system for processing coherent data |
JP2023044544A (en) | 2021-09-17 | 2023-03-30 | キオクシア株式会社 | memory system |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050086441A1 (en) * | 2003-10-20 | 2005-04-21 | Meyer James W. | Arbitration system and method for memory responses in a hub-based memory system |
WO2005038660A2 (en) * | 2003-10-17 | 2005-04-28 | Micron Technology, Inc. | Method and apparatus for sending data from multiple sources over a communications bus |
US20050177677A1 (en) * | 2004-02-05 | 2005-08-11 | Jeddeloh Joseph M. | Arbitration system having a packet memory and method for memory responses in a hub-based memory system |
Family Cites Families (391)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US676389A (en) * | 1900-10-20 | 1901-06-11 | American Tool Works Co | Radial drill. |
NL220449A (en) | 1956-09-04 | |||
US3333253A (en) | 1965-02-01 | 1967-07-25 | Ibm | Serial-to-parallel and parallel-toserial buffer-converter using a core matrix |
US3395400A (en) | 1966-04-26 | 1968-07-30 | Bell Telephone Labor Inc | Serial to parallel data converter |
US4028675A (en) * | 1973-05-14 | 1977-06-07 | Hewlett-Packard Company | Method and apparatus for refreshing semiconductor memories in multi-port and multi-module memory system |
US3825904A (en) | 1973-06-08 | 1974-07-23 | Ibm | Virtual memory system |
US4135240A (en) * | 1973-07-09 | 1979-01-16 | Bell Telephone Laboratories, Incorporated | Protection of data file contents |
US4150428A (en) | 1974-11-18 | 1979-04-17 | Northern Electric Company Limited | Method for providing a substitute memory in a data processing system |
US4472780A (en) | 1981-09-28 | 1984-09-18 | The Boeing Company | Fly-by-wire lateral control system |
US4486826A (en) | 1981-10-01 | 1984-12-04 | Stratus Computer, Inc. | Computer peripheral control apparatus |
US4475194A (en) | 1982-03-30 | 1984-10-02 | International Business Machines Corporation | Dynamic replacement of defective memory words |
US4641263A (en) | 1982-05-17 | 1987-02-03 | Digital Associates Corporation | Controller system or emulating local parallel minicomputer/printer interface and transferring serial data to remote line printer |
US4479214A (en) | 1982-06-16 | 1984-10-23 | International Business Machines Corporation | System for updating error map of fault tolerant memory |
US4486739A (en) | 1982-06-30 | 1984-12-04 | International Business Machines Corporation | Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code |
JPS59153353A (en) | 1983-02-22 | 1984-09-01 | Nec Corp | Data transmission system |
US4833605A (en) * | 1984-08-16 | 1989-05-23 | Mitsubishi Denki Kabushiki Kaisha | Cascaded information processing module having operation unit, parallel port, and serial port for concurrent data transfer and data processing |
US4683555A (en) * | 1985-01-22 | 1987-07-28 | Texas Instruments Incorporated | Serial accessed semiconductor memory with reconfigureable shift registers |
US4740916A (en) * | 1985-12-19 | 1988-04-26 | International Business Machines Corporation | Reconfigurable contiguous address space memory system including serially connected variable capacity memory modules and a split address bus |
US4723120A (en) | 1986-01-14 | 1988-02-02 | International Business Machines Corporation | Method and apparatus for constructing and operating multipoint communication networks utilizing point-to point hardware and interfaces |
US4704717A (en) * | 1986-07-22 | 1987-11-03 | Prime Computer, Inc. | Receive message processor for a solicited message packet transfer system |
ATE60845T1 (en) * | 1986-10-16 | 1991-02-15 | Siemens Ag | METHOD AND ARRANGEMENT FOR SUPPLYING A CLOCKING LINE WITH ONE OF TWO CLOCKING SIGNALS DEPENDING ON THE LEVEL OF ONE OF THE TWO CLOCKING SIGNALS. |
JPS63231550A (en) | 1987-03-19 | 1988-09-27 | Hitachi Ltd | Multiple virtual space control system |
US4803485A (en) * | 1987-03-23 | 1989-02-07 | Amp Incorporated | Lan communication system and medium adapter for use therewith |
US4782487A (en) | 1987-05-15 | 1988-11-01 | Digital Equipment Corporation | Memory test method and apparatus |
US4943984A (en) * | 1988-06-24 | 1990-07-24 | International Business Machines Corporation | Data processing system parallel data bus having a single oscillator clocking apparatus |
US4964129A (en) | 1988-12-21 | 1990-10-16 | Bull Hn Information Systems Inc. | Memory controller with error logging |
US4964130A (en) | 1988-12-21 | 1990-10-16 | Bull Hn Information Systems Inc. | System for determining status of errors in a memory subsystem |
EP0386506A3 (en) | 1989-03-06 | 1991-09-25 | International Business Machines Corporation | Low cost symbol error correction coding and decoding |
JP3038781B2 (en) * | 1989-04-21 | 2000-05-08 | 日本電気株式会社 | Memory access control circuit |
US5053947A (en) | 1989-09-29 | 1991-10-01 | Allegro Microsystems, Inc. | Extended multistation bus system and method |
US5279813A (en) | 1989-10-26 | 1994-01-18 | Colgate-Palmolive Company | Plaque inhibition with antiplaque oral composition dispensed from container having polymeric material in contact and compatible with the composition |
US5206946A (en) * | 1989-10-27 | 1993-04-27 | Sand Technology Systems Development, Inc. | Apparatus using converters, multiplexer and two latches to convert SCSI data into serial data and vice versa |
JP2724893B2 (en) * | 1989-12-28 | 1998-03-09 | 三菱電機株式会社 | Semiconductor integrated circuit device |
IL96808A (en) * | 1990-04-18 | 1996-03-31 | Rambus Inc | Integrated circuit i/o using a high performance bus interface |
US5517626A (en) | 1990-05-07 | 1996-05-14 | S3, Incorporated | Open high speed bus for microcomputer system |
GB2246494B (en) | 1990-05-25 | 1994-08-31 | Silicon Systems Inc | Method and apparatus for serial communications |
EP0463973A3 (en) | 1990-06-29 | 1993-12-01 | Digital Equipment Corp | Branch prediction in high performance processor |
CA2045789A1 (en) | 1990-06-29 | 1991-12-30 | Richard Lee Sites | Granularity hint for translation buffer in high performance processor |
US5530941A (en) | 1990-08-06 | 1996-06-25 | Ncr Corporation | System and method for prefetching data from a main computer memory into a cache memory |
US5357621A (en) | 1990-09-04 | 1994-10-18 | Hewlett-Packard Company | Serial architecture for memory module control |
US5522064A (en) * | 1990-10-01 | 1996-05-28 | International Business Machines Corporation | Data processing apparatus for dynamically setting timings in a dynamic memory system |
US5287531A (en) * | 1990-10-31 | 1994-02-15 | Compaq Computer Corp. | Daisy-chained serial shift register for determining configuration of removable circuit boards in a computer system |
US5214747A (en) * | 1990-12-24 | 1993-05-25 | Eastman Kodak Company | Segmented neural network with daisy chain control |
JP2999845B2 (en) | 1991-04-25 | 2000-01-17 | 沖電気工業株式会社 | Double speed control method for serial access memory |
FR2683924B1 (en) * | 1991-11-18 | 1997-01-03 | Bull Sa | INTEGRATED MEMORY, ITS MANAGEMENT METHOD AND RESULTING COMPUTER SYSTEM. |
US5347270A (en) * | 1991-12-27 | 1994-09-13 | Mitsubishi Denki Kabushiki Kaisha | Method of testing switches and switching circuit |
US5387911A (en) * | 1992-02-21 | 1995-02-07 | Gleichert; Marc C. | Method and apparatus for transmitting and receiving both 8B/10B code and 10B/12B code in a switchable 8B/10B transmitter and receiver |
US5715407A (en) * | 1992-03-06 | 1998-02-03 | Rambus, Inc. | Process and apparatus for collision detection on a parallel bus by monitoring a first line of the bus during even bus cycles for indications of overlapping packets |
US5375127A (en) | 1992-03-25 | 1994-12-20 | Ncr Corporation | Method and apparatus for generating Reed-Soloman error correcting code across multiple word boundaries |
US5265212A (en) | 1992-04-01 | 1993-11-23 | Digital Equipment Corporation | Sharing of bus access among multiple state machines with minimal wait time and prioritization of like cycle types |
EP0567707A1 (en) * | 1992-04-30 | 1993-11-03 | International Business Machines Corporation | Implementation of column redundancy in a cache memory architecture |
US5270964A (en) | 1992-05-19 | 1993-12-14 | Sun Microsystems, Inc. | Single in-line memory module |
US5410545A (en) | 1992-07-28 | 1995-04-25 | Digital Equipment Corporation | Long-term storage of controller performance |
JPH08500687A (en) * | 1992-08-10 | 1996-01-23 | モノリシック・システム・テクノロジー・インコーポレイテッド | Fault-tolerant high speed bus devices and interfaces for wafer scale integration |
US5594925A (en) | 1993-01-05 | 1997-01-14 | Texas Instruments Incorporated | Method and apparatus determining order and identity of subunits by inputting bit signals during first clock period and reading configuration signals during second clock period |
US5544309A (en) | 1993-04-22 | 1996-08-06 | International Business Machines Corporation | Data processing system with modified planar for boundary scan diagnostics |
US5531135A (en) * | 1993-06-11 | 1996-07-02 | Volkswagon Ag | Pedal arrangement for a motor vehicle |
JP3489147B2 (en) | 1993-09-20 | 2004-01-19 | 株式会社日立製作所 | Data transfer method |
DE69422678T2 (en) | 1993-10-12 | 2001-02-22 | Matsushita Electric Ind Co Ltd | Encryption system, encryption device and decryption device |
SE502576C2 (en) | 1993-11-26 | 1995-11-13 | Ellemtel Utvecklings Ab | Fault tolerant queuing system |
US5845310A (en) * | 1993-12-15 | 1998-12-01 | Hewlett-Packard Co. | System and methods for performing cache latency diagnostics in scalable parallel processing architectures including calculating CPU idle time and counting number of cache misses |
US5822749A (en) | 1994-07-12 | 1998-10-13 | Sybase, Inc. | Database system with methods for improving query performance with cache optimization strategies |
JPH0887451A (en) | 1994-09-09 | 1996-04-02 | Internatl Business Mach Corp <Ibm> | Method for control of address conversion and address conversion manager |
US5611055A (en) * | 1994-09-27 | 1997-03-11 | Novalink Technologies | Method and apparatus for implementing a PCMCIA auxiliary port connector for selectively communicating with peripheral devices |
US5475690A (en) | 1994-11-10 | 1995-12-12 | Digital Equipment Corporation | Delay compensated signal propagation |
US6170047B1 (en) * | 1994-11-16 | 2001-01-02 | Interactive Silicon, Inc. | System and method for managing system memory and/or non-volatile memory using a memory controller with integrated compression and decompression capabilities |
US6002411A (en) | 1994-11-16 | 1999-12-14 | Interactive Silicon, Inc. | Integrated video and memory controller with data processing and graphical processing capabilities |
US5513135A (en) * | 1994-12-02 | 1996-04-30 | International Business Machines Corporation | Synchronous memory packaged in single/dual in-line memory module and method of fabrication |
JP3467880B2 (en) | 1994-12-26 | 2003-11-17 | ソニー株式会社 | Clock signal generator |
US5881154A (en) | 1995-01-17 | 1999-03-09 | Kokusai Denshin Denwa Co., Ltd. | Data scramble transmission system |
US5629685A (en) | 1995-02-23 | 1997-05-13 | International Business Machines Corporation | Segmentable addressable modular communication network hubs |
US6446224B1 (en) | 1995-03-03 | 2002-09-03 | Fujitsu Limited | Method and apparatus for prioritizing and handling errors in a computer system |
IN188196B (en) * | 1995-05-15 | 2002-08-31 | Silicon Graphics Inc | |
US5546023A (en) | 1995-06-26 | 1996-08-13 | Intel Corporation | Daisy chained clock distribution scheme |
US5852617A (en) | 1995-12-08 | 1998-12-22 | Samsung Electronics Co., Ltd. | Jtag testing of buses using plug-in cards with Jtag logic mounted thereon |
US5754804A (en) | 1996-01-30 | 1998-05-19 | International Business Machines Corporation | Method and system for managing system bus communications in a data processing system |
JPH09231130A (en) | 1996-02-26 | 1997-09-05 | Mitsubishi Electric Corp | Micro computer |
US5764155A (en) * | 1996-04-03 | 1998-06-09 | General Electric Company | Dynamic data exchange server |
JP3710198B2 (en) * | 1996-04-18 | 2005-10-26 | 沖電気工業株式会社 | STM-N signal error correction encoding / decoding method, STM-N signal error correction encoding circuit, and STM-N signal error correction decoding circuit |
US5661677A (en) * | 1996-05-15 | 1997-08-26 | Micron Electronics, Inc. | Circuit and method for on-board programming of PRD Serial EEPROMS |
US5917760A (en) | 1996-09-20 | 1999-06-29 | Sldram, Inc. | De-skewing data signals in a memory system |
US5930359A (en) | 1996-09-23 | 1999-07-27 | Motorola, Inc. | Cascadable content addressable memory and system |
JPH10173122A (en) * | 1996-12-06 | 1998-06-26 | Mitsubishi Electric Corp | Memory module |
US20020103988A1 (en) | 1996-12-18 | 2002-08-01 | Pascal Dornier | Microprocessor with integrated interfaces to system memory and multiplexed input/output bus |
US5926838A (en) * | 1997-03-19 | 1999-07-20 | Micron Electronics | Interface for high speed memory |
US5870320A (en) | 1997-06-23 | 1999-02-09 | Sun Microsystems, Inc. | Method for reducing a computational result to the range boundaries of a signed 16-bit integer in case of overflow |
US6138213A (en) * | 1997-06-27 | 2000-10-24 | Advanced Micro Devices, Inc. | Cache including a prefetch way for storing prefetch cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line |
US6292903B1 (en) * | 1997-07-09 | 2001-09-18 | International Business Machines Corporation | Smart memory interface |
US6011732A (en) | 1997-08-20 | 2000-01-04 | Micron Technology, Inc. | Synchronous clock generator including a compound delay-locked loop |
US6128746A (en) | 1997-08-26 | 2000-10-03 | International Business Machines Corporation | Continuously powered mainstore for large memory subsystems |
US6230236B1 (en) | 1997-08-28 | 2001-05-08 | Nortel Networks Corporation | Content addressable memory system with cascaded memories and self timed signals |
JP3445476B2 (en) | 1997-10-02 | 2003-09-08 | 株式会社東芝 | Semiconductor memory system |
US6378018B1 (en) * | 1997-10-10 | 2002-04-23 | Intel Corporation | Memory device and system including a low power interface |
US6347354B1 (en) * | 1997-10-10 | 2002-02-12 | Rambus Incorporated | Apparatus and method for maximizing information transfers over limited interconnect resources |
US6085276A (en) | 1997-10-24 | 2000-07-04 | Compaq Computers Corporation | Multi-processor computer system having a data switch with simultaneous insertion buffers for eliminating arbitration interdependencies |
US6851036B1 (en) | 1997-11-06 | 2005-02-01 | Renesas Technology Corp. | Method and apparatus for controlling external devices through address translation buffer |
US5973591A (en) | 1997-11-19 | 1999-10-26 | Schwartz; David | Electronic signaling system |
US5917780A (en) * | 1997-12-03 | 1999-06-29 | Daniel Robbins | Watch having a multiplicity of band attachment positions and wristband for use therewith |
US6018817A (en) | 1997-12-03 | 2000-01-25 | International Business Machines Corporation | Error correcting code retrofit method and apparatus for multiple memory configurations |
US5995988A (en) * | 1997-12-04 | 1999-11-30 | Xilinx, Inc. | Configurable parallel and bit serial load apparatus |
WO1999030240A1 (en) | 1997-12-05 | 1999-06-17 | Intel Corporation | Memory system including a memory module having a memory module controller |
US6145028A (en) | 1997-12-11 | 2000-11-07 | Ncr Corporation | Enhanced multi-pathing to an array of storage devices |
US7373440B2 (en) * | 1997-12-17 | 2008-05-13 | Src Computers, Inc. | Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format |
US5987555A (en) | 1997-12-22 | 1999-11-16 | Compaq Computer Corporation | Dynamic delayed transaction discard counter in a bus bridge of a computer system |
US5995998A (en) | 1998-01-23 | 1999-11-30 | Sun Microsystems, Inc. | Method, apparatus and computer program product for locking interrelated data structures in a multi-threaded computing environment |
US6044483A (en) | 1998-01-29 | 2000-03-28 | International Business Machines Corporation | Error propagation operating mode for error correcting code retrofit apparatus |
US7024518B2 (en) | 1998-02-13 | 2006-04-04 | Intel Corporation | Dual-port buffer-to-memory interface |
US6198304B1 (en) | 1998-02-23 | 2001-03-06 | Xilinx, Inc. | Programmable logic device |
US6096091A (en) * | 1998-02-24 | 2000-08-01 | Advanced Micro Devices, Inc. | Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip |
US6185718B1 (en) | 1998-02-27 | 2001-02-06 | International Business Machines Corporation | Memory card design with parity and ECC for non-parity and non-ECC systems |
US5959914A (en) | 1998-03-27 | 1999-09-28 | Lsi Logic Corporation | Memory controller with error correction memory test application |
US6643745B1 (en) | 1998-03-31 | 2003-11-04 | Intel Corporation | Method and apparatus for prefetching data into cache |
US5870325A (en) * | 1998-04-14 | 1999-02-09 | Silicon Graphics, Inc. | Memory system with multiple addressing and control busses |
US6173382B1 (en) | 1998-04-28 | 2001-01-09 | International Business Machines Corporation | Dynamic configuration of memory module using modified presence detect data |
US6003121A (en) | 1998-05-18 | 1999-12-14 | Intel Corporation | Single and multiple channel memory detection and sizing |
US6216247B1 (en) | 1998-05-29 | 2001-04-10 | Intel Corporation | 32-bit mode for a 64-bit ECC capable memory subsystem |
DE69817333T2 (en) | 1998-06-05 | 2004-06-09 | International Business Machines Corp. | Method and device for loading command codes into a memory and for connecting these command codes |
EP0964526B1 (en) | 1998-06-08 | 2003-09-03 | Texas Instruments Incorporated | Data forwarding for communication of serial and parallel data |
JPH11353228A (en) * | 1998-06-10 | 1999-12-24 | Mitsubishi Electric Corp | Memory module system |
US6170059B1 (en) * | 1998-07-10 | 2001-01-02 | International Business Machines Corporation | Tracking memory modules within a computer system |
US6260127B1 (en) * | 1998-07-13 | 2001-07-10 | Compaq Computer Corporation | Method and apparatus for supporting heterogeneous memory in computer systems |
US6505305B1 (en) | 1998-07-16 | 2003-01-07 | Compaq Information Technologies Group, L.P. | Fail-over of multiple memory blocks in multiple memory modules in computer system |
US6021076A (en) | 1998-07-16 | 2000-02-01 | Rambus Inc | Apparatus and method for thermal regulation in memory subsystems |
US6496540B1 (en) | 1998-07-22 | 2002-12-17 | International Business Machines Corporation | Transformation of parallel interface into coded format with preservation of baud-rate |
US6158040A (en) | 1998-07-29 | 2000-12-05 | Neomagic Corp. | Rotated data-aligmnent in wade embedded DRAM for page-mode column ECC in a DVD controller |
US6272609B1 (en) | 1998-07-31 | 2001-08-07 | Micron Electronics, Inc. | Pipelined memory controller |
JP4083302B2 (en) | 1998-08-12 | 2008-04-30 | 株式会社東芝 | Video scrambling / descrambling device |
US6587912B2 (en) | 1998-09-30 | 2003-07-01 | Intel Corporation | Method and apparatus for implementing multiple memory buses on a memory module |
US5995405A (en) | 1998-10-27 | 1999-11-30 | Micron Technology, Inc. | Memory module with flexible serial presence detect configuration |
US6226729B1 (en) | 1998-11-03 | 2001-05-01 | Intel Corporation | Method and apparatus for configuring and initializing a memory device and a memory channel |
US20020124195A1 (en) | 1998-11-04 | 2002-09-05 | Puthiya K. Nizar | Method and apparatus for power management in a memory subsystem |
US6349390B1 (en) | 1999-01-04 | 2002-02-19 | International Business Machines Corporation | On-board scrubbing of soft errors memory module |
US6233639B1 (en) | 1999-01-04 | 2001-05-15 | International Business Machines Corporation | Memory card utilizing two wire bus |
JP3275867B2 (en) | 1999-01-26 | 2002-04-22 | 日本電気株式会社 | Scan test circuit, semiconductor integrated circuit including scan test circuit, and semiconductor integrated circuit test board mounted with scan test circuit |
US6357018B1 (en) | 1999-01-26 | 2002-03-12 | Dell Usa, L.P. | Method and apparatus for determining continuity and integrity of a RAMBUS channel in a computer system |
JP3484093B2 (en) | 1999-02-01 | 2004-01-06 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Associative memory |
US6115278A (en) * | 1999-02-09 | 2000-09-05 | Silicon Graphics, Inc. | Memory system with switching for data isolation |
US6341315B1 (en) | 1999-02-26 | 2002-01-22 | Crossroads Systems, Inc. | Streaming method and system for fiber channel network devices |
US6564329B1 (en) * | 1999-03-16 | 2003-05-13 | Linkup Systems Corporation | System and method for dynamic clock generation |
US6460107B1 (en) * | 1999-04-29 | 2002-10-01 | Intel Corporation | Integrated real-time performance monitoring facility |
JP3512678B2 (en) | 1999-05-27 | 2004-03-31 | 富士通株式会社 | Cache memory control device and computer system |
US6393528B1 (en) | 1999-06-30 | 2002-05-21 | International Business Machines Corporation | Optimized cache allocation algorithm for multiple speculative requests |
US6507592B1 (en) * | 1999-07-08 | 2003-01-14 | Cisco Cable Products And Solutions A/S (Av) | Apparatus and a method for two-way data communication |
US6425044B1 (en) | 1999-07-13 | 2002-07-23 | Micron Technology, Inc. | Apparatus for providing fast memory decode using a bank conflict table |
US6839393B1 (en) * | 1999-07-14 | 2005-01-04 | Rambus Inc. | Apparatus and method for controlling a master/slave system via master device synchronization |
US7017020B2 (en) * | 1999-07-16 | 2006-03-21 | Broadcom Corporation | Apparatus and method for optimizing access to memory |
US6792495B1 (en) | 1999-07-27 | 2004-09-14 | Intel Corporation | Transaction scheduling for a bus system |
US7155016B1 (en) | 1999-08-20 | 2006-12-26 | Paradyne Corporation | Communication device and method for using non-self-synchronizing scrambling in a communication system |
US6549971B1 (en) * | 1999-08-26 | 2003-04-15 | International Business Machines Corporation | Cascaded differential receiver circuit |
US6594713B1 (en) | 1999-09-10 | 2003-07-15 | Texas Instruments Incorporated | Hub interface unit and application unit interfaces for expanded direct memory access processor |
US6484271B1 (en) | 1999-09-16 | 2002-11-19 | Koninklijke Philips Electronics N.V. | Memory redundancy techniques |
US6393512B1 (en) | 1999-09-27 | 2002-05-21 | Ati International Srl | Circuit and method for detecting bank conflicts in accessing adjacent banks |
US6467013B1 (en) | 1999-09-30 | 2002-10-15 | Intel Corporation | Memory transceiver to couple an additional memory channel to an existing memory channel |
US6262493B1 (en) * | 1999-10-08 | 2001-07-17 | Sun Microsystems, Inc. | Providing standby power to field replaceable units for electronic systems |
US6889284B1 (en) | 1999-10-19 | 2005-05-03 | Intel Corporation | Method and apparatus for supporting SDRAM memory |
US6493843B1 (en) | 1999-10-28 | 2002-12-10 | Hewlett-Packard Company | Chipkill for a low end server or workstation |
US6584576B1 (en) | 1999-11-12 | 2003-06-24 | Kingston Technology Corporation | Memory system using complementary delay elements to reduce rambus module timing skew |
US6513091B1 (en) * | 1999-11-12 | 2003-01-28 | International Business Machines Corporation | Data routing using status-response signals |
US6557069B1 (en) * | 1999-11-12 | 2003-04-29 | International Business Machines Corporation | Processor-memory bus architecture for supporting multiple processors |
US6526469B1 (en) | 1999-11-12 | 2003-02-25 | International Business Machines Corporation | Bus architecture employing varying width uni-directional command bus |
JP2001167077A (en) | 1999-12-09 | 2001-06-22 | Nec Kofu Ltd | Data access method for network system, network system and recording medium |
US6601149B1 (en) * | 1999-12-14 | 2003-07-29 | International Business Machines Corporation | Memory transaction monitoring system and user interface |
US6487627B1 (en) | 1999-12-22 | 2002-11-26 | Intel Corporation | Method and apparatus to manage digital bus traffic |
US6499090B1 (en) * | 1999-12-28 | 2002-12-24 | Intel Corporation | Prioritized bus request scheduling mechanism for processing devices |
US6307789B1 (en) * | 1999-12-28 | 2001-10-23 | Intel Corporation | Scratchpad memory |
US6609171B1 (en) * | 1999-12-29 | 2003-08-19 | Intel Corporation | Quad pumped bus architecture and protocol |
US6408398B1 (en) | 1999-12-29 | 2002-06-18 | Intel Corporation | Method and apparatus for detecting time domains on a communication channel |
KR100575864B1 (en) | 1999-12-30 | 2006-05-03 | 주식회사 하이닉스반도체 | Rambus dram |
US6910146B2 (en) | 1999-12-31 | 2005-06-21 | Intel Corporation | Method and apparatus for improving timing margin in an integrated circuit as determined from recorded pass/fail indications for relative phase settings |
US7266634B2 (en) | 2000-01-05 | 2007-09-04 | Rambus Inc. | Configurable width buffered module having flyby elements |
US6502161B1 (en) | 2000-01-05 | 2002-12-31 | Rambus Inc. | Memory system including a point-to-point linked memory subsystem |
US6845472B2 (en) | 2000-01-25 | 2005-01-18 | Hewlett-Packard Development Company, L.P. | Memory sub-system error cleansing |
US6219288B1 (en) * | 2000-03-03 | 2001-04-17 | International Business Machines Corporation | Memory having user programmable AC timings |
US6631439B2 (en) | 2000-03-08 | 2003-10-07 | Sun Microsystems, Inc. | VLIW computer processing architecture with on-chip dynamic RAM |
JP4569913B2 (en) | 2000-03-10 | 2010-10-27 | エルピーダメモリ株式会社 | Memory module |
JP2001290697A (en) | 2000-04-06 | 2001-10-19 | Hitachi Ltd | Information-processing system |
US6704842B1 (en) * | 2000-04-12 | 2004-03-09 | Hewlett-Packard Development Company, L.P. | Multi-processor system with proactive speculative data transfer |
US7269765B1 (en) | 2000-04-13 | 2007-09-11 | Micron Technology, Inc. | Method and apparatus for storing failing part locations in a module |
JP2001297535A (en) | 2000-04-14 | 2001-10-26 | Sony Corp | Data recording method, data recording device, data reproducing method, data reproducing device and recording medium |
US6546359B1 (en) * | 2000-04-24 | 2003-04-08 | Sun Microsystems, Inc. | Method and apparatus for multiplexing hardware performance indicators |
US6721944B2 (en) | 2000-05-31 | 2004-04-13 | Sun Microsystems, Inc. | Marking memory elements based upon usage of accessed information during speculative execution |
US7039755B1 (en) | 2000-05-31 | 2006-05-02 | Advanced Micro Devices, Inc. | Method and apparatus for powering down the CPU/memory controller complex while preserving the self refresh state of memory in the system |
US6461013B1 (en) | 2000-06-02 | 2002-10-08 | Richard L. Simon | Door knob lighting assembly |
US6748518B1 (en) | 2000-06-06 | 2004-06-08 | International Business Machines Corporation | Multi-level multiprocessor speculation mechanism |
US6697919B2 (en) * | 2000-06-10 | 2004-02-24 | Hewlett-Packard Development Company, L.P. | System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system |
US6622217B2 (en) | 2000-06-10 | 2003-09-16 | Hewlett-Packard Development Company, L.P. | Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system |
US6415376B1 (en) | 2000-06-16 | 2002-07-02 | Conexant Sytems, Inc. | Apparatus and method for issue grouping of instructions in a VLIW processor |
US6791555B1 (en) | 2000-06-23 | 2004-09-14 | Micron Technology, Inc. | Apparatus and method for distributed memory control in a graphics processing system |
US6611905B1 (en) * | 2000-06-29 | 2003-08-26 | International Business Machines Corporation | Memory interface with programable clock to output time based on wide range of receiver loads |
US6587112B1 (en) * | 2000-07-10 | 2003-07-01 | Hewlett-Packard Development Company, L.P. | Window copy-swap using multi-buffer hardware support |
US6446174B1 (en) | 2000-07-11 | 2002-09-03 | Intel Corporation | Computer system with dram bus |
US6977979B1 (en) | 2000-08-31 | 2005-12-20 | Hewlett-Packard Development Company, L.P. | Enhanced clock forwarding data recovery |
US6738836B1 (en) * | 2000-08-31 | 2004-05-18 | Hewlett-Packard Development Company, L.P. | Scalable efficient I/O port protocol |
US6487102B1 (en) | 2000-09-18 | 2002-11-26 | Intel Corporation | Memory module having buffer for isolating stacked memory devices |
US6553450B1 (en) * | 2000-09-18 | 2003-04-22 | Intel Corporation | Buffer to multiply memory interface |
US6317352B1 (en) | 2000-09-18 | 2001-11-13 | Intel Corporation | Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules |
US6625687B1 (en) | 2000-09-18 | 2003-09-23 | Intel Corporation | Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing |
US6625685B1 (en) | 2000-09-20 | 2003-09-23 | Broadcom Corporation | Memory controller with programmable configuration |
US6532525B1 (en) * | 2000-09-29 | 2003-03-11 | Ati Technologies, Inc. | Method and apparatus for accessing memory |
JP2004517386A (en) | 2000-10-06 | 2004-06-10 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | Method and apparatus |
US6636875B1 (en) | 2000-10-25 | 2003-10-21 | International Business Machines Corporation | System and method for synchronizing related data elements in disparate storage systems |
US7068683B1 (en) * | 2000-10-25 | 2006-06-27 | Qualcomm, Incorporated | Method and apparatus for high rate packet data and low delay data transmissions |
US6611902B2 (en) | 2000-11-13 | 2003-08-26 | Matsushita Electric Industrial Co., Ltd. | Information processor and information processing method |
US6285172B1 (en) | 2000-11-13 | 2001-09-04 | Texas Instruments Incorporated | Digital phase-locked loop circuit with reduced phase jitter frequency |
US6978419B1 (en) | 2000-11-15 | 2005-12-20 | Justsystem Corporation | Method and apparatus for efficient identification of duplicate and near-duplicate documents and text spans using high-discriminability text fragments |
US6898726B1 (en) | 2000-11-15 | 2005-05-24 | Micron Technology, Inc. | Memory system that sets a predetermined phase relationship between read and write clock signals at a bus midpoint for a plurality of spaced device locations |
US6590827B2 (en) * | 2000-11-21 | 2003-07-08 | Via Technologies, Inc. | Clock device for supporting multiplicity of memory module types |
US6510100B2 (en) * | 2000-12-04 | 2003-01-21 | International Business Machines Corporation | Synchronous memory modules and memory systems with selectable clock termination |
US6993612B2 (en) | 2000-12-07 | 2006-01-31 | Micron Technology, Inc. | Arbitration method for a source strobed bus |
US6834355B2 (en) | 2000-12-15 | 2004-12-21 | Intel Corporation | Circuit in which the time delay of an input clock signal is dependent only on its logic phase width and a ratio of capacitances |
US6751684B2 (en) * | 2000-12-21 | 2004-06-15 | Jonathan M. Owen | System and method of allocating bandwidth to a plurality of devices interconnected by a plurality of point-to-point communication links |
US6934785B2 (en) * | 2000-12-22 | 2005-08-23 | Micron Technology, Inc. | High speed interface with looped bus |
US6622227B2 (en) | 2000-12-27 | 2003-09-16 | Intel Corporation | Method and apparatus for utilizing write buffers in memory control/interface |
US6493250B2 (en) | 2000-12-28 | 2002-12-10 | Intel Corporation | Multi-tier point-to-point buffered memory interface |
TW527537B (en) * | 2001-01-03 | 2003-04-11 | Leadtek Research Inc | Conversion device of SDR and DDR, and interface card, motherboard and memory module interface using the same |
US6832329B2 (en) | 2001-02-08 | 2004-12-14 | International Business Machines Corporation | Cache thresholding method, apparatus, and program for predictive reporting of array bit line or driver failures |
US6445624B1 (en) | 2001-02-23 | 2002-09-03 | Micron Technology, Inc. | Method of synchronizing read timing in a high speed memory system |
JP3888070B2 (en) | 2001-02-23 | 2007-02-28 | 株式会社ルネサステクノロジ | Logic circuit module having power consumption control interface and storage medium storing the module |
US20020124201A1 (en) | 2001-03-01 | 2002-09-05 | International Business Machines Corporation | Method and system for log repair action handling on a logically partitioned multiprocessing system |
US6874102B2 (en) | 2001-03-05 | 2005-03-29 | Stratus Technologies Bermuda Ltd. | Coordinated recalibration of high bandwidth memories in a multiprocessor computer |
US6754762B1 (en) * | 2001-03-05 | 2004-06-22 | Honeywell International Inc. | Redundant bus switching |
US6658523B2 (en) | 2001-03-13 | 2003-12-02 | Micron Technology, Inc. | System latency levelization for read data |
US6882082B2 (en) * | 2001-03-13 | 2005-04-19 | Micron Technology, Inc. | Memory repeater |
US6678811B2 (en) * | 2001-04-07 | 2004-01-13 | Hewlett-Packard Development Company, L.P. | Memory controller with 1X/MX write capability |
US6625702B2 (en) | 2001-04-07 | 2003-09-23 | Hewlett-Packard Development Company, L.P. | Memory controller with support for memory modules comprised of non-homogeneous data width RAM devices |
US6721185B2 (en) | 2001-05-01 | 2004-04-13 | Sun Microsystems, Inc. | Memory module having balanced data I/O contacts pads |
US6779075B2 (en) | 2001-05-15 | 2004-08-17 | Leadtek Research Inc. | DDR and QDR converter and interface card, motherboard and memory module interface using the same |
US6766389B2 (en) | 2001-05-18 | 2004-07-20 | Broadcom Corporation | System on a chip for networking |
CA2447555A1 (en) | 2001-06-04 | 2002-12-12 | Nct Group, Inc. | System and method for increasing the effective bandwidth of a communications network |
US20030090879A1 (en) * | 2001-06-14 | 2003-05-15 | Doblar Drew G. | Dual inline memory module |
US6760817B2 (en) | 2001-06-21 | 2004-07-06 | International Business Machines Corporation | Method and system for prefetching utilizing memory initiated prefetch write operations |
US20030033463A1 (en) * | 2001-08-10 | 2003-02-13 | Garnett Paul J. | Computer system storage |
US6681292B2 (en) | 2001-08-27 | 2004-01-20 | Intel Corporation | Distributed read and write caching implementation for optimized input/output applications |
US20040098549A1 (en) | 2001-10-04 | 2004-05-20 | Dorst Jeffrey R. | Apparatus and methods for programmable interfaces in memory controllers |
US6965952B2 (en) * | 2001-10-15 | 2005-11-15 | Intel Corporation | Bus framer |
US7248585B2 (en) | 2001-10-22 | 2007-07-24 | Sun Microsystems, Inc. | Method and apparatus for a packet classifier |
US6594748B1 (en) | 2001-11-09 | 2003-07-15 | Lsi Logic Corporation | Methods and structure for pipelined read return control in a shared RAM controller |
DE10155449A1 (en) | 2001-11-12 | 2003-05-28 | Infineon Technologies Ag | Memory reconfiguration method |
US6675280B2 (en) * | 2001-11-30 | 2004-01-06 | Intel Corporation | Method and apparatus for identifying candidate virtual addresses in a content-aware prefetcher |
JP4063533B2 (en) | 2001-12-10 | 2008-03-19 | 日本碍子株式会社 | Flexible wiring board |
US7385993B2 (en) * | 2001-12-21 | 2008-06-10 | International Business Machines Corporation | Queue scheduling mechanism in a data packet transmission system |
US6792516B2 (en) | 2001-12-28 | 2004-09-14 | Intel Corporation | Memory arbiter with intelligent page gathering logic |
US7389387B2 (en) | 2001-12-31 | 2008-06-17 | Intel Corporation | Distributed memory module cache writeback |
US6865646B2 (en) | 2001-12-31 | 2005-03-08 | Intel Corporation | Segmented distributed memory module cache |
US6925534B2 (en) | 2001-12-31 | 2005-08-02 | Intel Corporation | Distributed memory module cache prefetch |
US6799241B2 (en) | 2002-01-03 | 2004-09-28 | Intel Corporation | Method for dynamically adjusting a memory page closing policy |
US6775747B2 (en) * | 2002-01-03 | 2004-08-10 | Intel Corporation | System and method for performing page table walks on speculative software prefetch operations |
KR100454126B1 (en) | 2002-01-15 | 2004-10-26 | 삼성전자주식회사 | Information processing system with separated clock line structure |
US7227949B2 (en) | 2002-01-31 | 2007-06-05 | Texas Instruments Incorporated | Separate self-synchronizing packet-based scrambler having replay variation |
JP3925234B2 (en) * | 2002-02-18 | 2007-06-06 | ソニー株式会社 | Data communication system, data communication management device and method, and computer program |
GB2386441B (en) | 2002-03-12 | 2006-09-27 | Advanced Risc Mach Ltd | Bus interface selection by page table attributes |
US7000077B2 (en) * | 2002-03-14 | 2006-02-14 | Intel Corporation | Device/host coordinated prefetching storage system |
DE10215362A1 (en) | 2002-04-08 | 2003-10-30 | Infineon Technologies Ag | Integrated memory with a memory cell array with several memory banks and circuit arrangement with an integrated memory |
US6918068B2 (en) | 2002-04-08 | 2005-07-12 | Harris Corporation | Fault-tolerant communications system and associated methods |
US6948091B2 (en) | 2002-05-02 | 2005-09-20 | Honeywell International Inc. | High integrity recovery from multi-bit data failures |
KR101069778B1 (en) * | 2002-05-10 | 2011-10-05 | 인터디지탈 테크날러지 코포레이션 | System and method for prioritization of retransmission of protocol data units to assist radio-link-control retransmission |
US7376146B2 (en) * | 2002-05-16 | 2008-05-20 | Intel Corporation | Bus conversion device, system and method |
US6807650B2 (en) | 2002-06-03 | 2004-10-19 | International Business Machines Corporation | DDR-II driver impedance adjustment control algorithm and interface circuits |
US7133972B2 (en) | 2002-06-07 | 2006-11-07 | Micron Technology, Inc. | Memory hub with internal cache and/or memory access prediction |
US7203318B2 (en) | 2002-06-17 | 2007-04-10 | M/A-Com Private Radio Systems, Inc. | Secure transmission system for a digital trunked radio system |
DE60311467T2 (en) | 2002-06-21 | 2007-11-08 | Hymo Corp. | DISPERSION OF WATER-SOLUBLE POLYMER, METHOD OF MANUFACTURING THEREOF AND USE METHOD THEREFOR |
TW559694B (en) | 2002-06-21 | 2003-11-01 | Via Tech Inc | Method and system of calibrating the control delay time |
US7212548B2 (en) * | 2002-06-21 | 2007-05-01 | Adtran, Inc. | Multiple T1 channel inverse multiplexing method and apparatus |
US6832286B2 (en) | 2002-06-25 | 2004-12-14 | Hewlett-Packard Development Company, L.P. | Memory auto-precharge |
US7047384B2 (en) | 2002-06-27 | 2006-05-16 | Intel Corporation | Method and apparatus for dynamic timing of memory interface signals |
US6996766B2 (en) | 2002-06-28 | 2006-02-07 | Sun Microsystems, Inc. | Error detection/correction code which detects and corrects a first failing component and optionally a second failing component |
US6741096B2 (en) | 2002-07-02 | 2004-05-25 | Lsi Logic Corporation | Structure and methods for measurement of arbitration performance |
US6854043B2 (en) * | 2002-07-05 | 2005-02-08 | Hewlett-Packard Development Company, L.P. | System and method for multi-modal memory controller system operation |
JP4159415B2 (en) | 2002-08-23 | 2008-10-01 | エルピーダメモリ株式会社 | Memory module and memory system |
KR101027590B1 (en) * | 2002-08-16 | 2011-04-06 | 톰슨 라이센싱 | Download optimization in the presence of multicast data |
US6820181B2 (en) * | 2002-08-29 | 2004-11-16 | Micron Technology, Inc. | Method and system for controlling memory accesses to memory modules having a memory hub architecture |
JP2004093462A (en) | 2002-09-02 | 2004-03-25 | Oki Electric Ind Co Ltd | Semiconductor integrated circuit and its testing method |
KR20040021485A (en) | 2002-09-04 | 2004-03-10 | 삼성전자주식회사 | Memory control apparatus and method of controlling memory access capable of selecting page mode in order to reduce memory access time |
US20040054864A1 (en) | 2002-09-13 | 2004-03-18 | Jameson Neil Andrew | Memory controller |
US20040078615A1 (en) * | 2002-10-17 | 2004-04-22 | Intel Corporation (A Delaware Corporation) | Multi-module system, distribution circuit and their methods of operation |
DE10248672B4 (en) * | 2002-10-18 | 2016-02-11 | Robert Bosch Gmbh | Method for transmitting data on a bus |
US7313583B2 (en) | 2002-10-22 | 2007-12-25 | Broadcom Corporation | Galois field arithmetic unit for use within a processor |
US6963516B2 (en) | 2002-11-27 | 2005-11-08 | International Business Machines Corporation | Dynamic optimization of latency and bandwidth on DRAM interfaces |
US6996639B2 (en) | 2002-12-10 | 2006-02-07 | Intel Corporation | Configurably prefetching head-of-queue from ring buffers |
US20040117588A1 (en) | 2002-12-12 | 2004-06-17 | International Business Machines Corporation | Access request for a data processing system having no system memory |
US7093076B2 (en) | 2002-12-12 | 2006-08-15 | Samsung Electronics, Co., Ltd. | Memory system having two-way ring topology and memory device and memory module for ring-topology memory system |
US6978416B2 (en) | 2002-12-19 | 2005-12-20 | International Business Machines Corporation | Error correction with low latency for bus structures |
US6944084B2 (en) | 2002-12-31 | 2005-09-13 | Intel Corporation | Memory system that measures power consumption |
US6879468B2 (en) | 2003-01-08 | 2005-04-12 | Shin-Etsu Chemical Co., Ltd. | Magnetic head actuator having an improved microactuator oscillatably supported by metallic micro-beams |
US7308524B2 (en) | 2003-01-13 | 2007-12-11 | Silicon Pipe, Inc | Memory chain |
US7047370B1 (en) | 2003-01-14 | 2006-05-16 | Cisco Technology, Inc. | Full access to memory interfaces via remote request |
US7096407B2 (en) | 2003-02-18 | 2006-08-22 | Hewlett-Packard Development Company, L.P. | Technique for implementing chipkill in a memory system |
US7216276B1 (en) * | 2003-02-27 | 2007-05-08 | Marvell International Ltd. | Apparatus and method for testing and debugging an integrated circuit |
US6922658B2 (en) | 2003-03-31 | 2005-07-26 | International Business Machines Corporation | Method and system for testing the validity of shared data in a multiprocessing system |
US7234099B2 (en) | 2003-04-14 | 2007-06-19 | International Business Machines Corporation | High reliability memory module with a fault tolerant address and command bus |
US7086949B2 (en) | 2003-05-08 | 2006-08-08 | Logitech Europe S.A. | Convertible single-turn to multi-turn gaming steering wheel utilizing sliding stops |
JP4836794B2 (en) | 2003-05-13 | 2011-12-14 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | A system including a host connected to a plurality of memory modules via a serial memory interconnect |
US7320100B2 (en) | 2003-05-20 | 2008-01-15 | Cray Inc. | Apparatus and method for memory with bit swapping on the fly and testing |
TW200427224A (en) | 2003-05-21 | 2004-12-01 | Myson Century Inc | Clock multiplier |
US7127629B2 (en) | 2003-06-03 | 2006-10-24 | Intel Corporation | Redriving a data signal responsive to either a sampling clock signal or stable clock signal dependent on a mode signal |
US7165153B2 (en) | 2003-06-04 | 2007-01-16 | Intel Corporation | Memory channel with unidirectional links |
US7260685B2 (en) | 2003-06-20 | 2007-08-21 | Micron Technology, Inc. | Memory hub and access method having internal prefetch buffers |
US7428644B2 (en) | 2003-06-20 | 2008-09-23 | Micron Technology, Inc. | System and method for selective memory module power management |
DE10330812B4 (en) | 2003-07-08 | 2006-07-06 | Infineon Technologies Ag | Semiconductor memory module |
US20050022091A1 (en) | 2003-07-21 | 2005-01-27 | Holman Thomas J. | Method, system, and apparatus for adjacent-symbol error correction and detection code |
CN1272712C (en) * | 2003-07-23 | 2006-08-30 | 威盛电子股份有限公司 | Method for determining delay time written into memry and its device |
KR100500454B1 (en) | 2003-07-28 | 2005-07-12 | 삼성전자주식회사 | Memory module test system and memory module evaluation system |
US7844801B2 (en) | 2003-07-31 | 2010-11-30 | Intel Corporation | Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors |
DE10335978B4 (en) | 2003-08-06 | 2006-02-16 | Infineon Technologies Ag | Hub module for connecting one or more memory modules |
US7210059B2 (en) | 2003-08-19 | 2007-04-24 | Micron Technology, Inc. | System and method for on-board diagnostics of memory modules |
US7136958B2 (en) | 2003-08-28 | 2006-11-14 | Micron Technology, Inc. | Multiple processor system and method including multiple memory hub modules |
US20050050237A1 (en) | 2003-08-28 | 2005-03-03 | Jeddeloh Joseph M. | Memory module and method having on-board data search capabilities and processor-based system using such memory modules |
US7194593B2 (en) | 2003-09-18 | 2007-03-20 | Micron Technology, Inc. | Memory hub with integrated non-volatile memory |
US20050080581A1 (en) | 2003-09-22 | 2005-04-14 | David Zimmerman | Built-in self test for memory interconnect testing |
US7197594B2 (en) | 2003-09-23 | 2007-03-27 | Infineon Technologies Flash Gmbh & Co. Kg | Circuit, system and method for encoding data to be stored on a non-volatile memory array |
US7124329B2 (en) | 2003-09-26 | 2006-10-17 | International Business Machines Corporation | Implementing memory failure analysis in a data processing system |
US7334159B1 (en) | 2003-09-29 | 2008-02-19 | Rockwell Automation Technologies, Inc. | Self-testing RAM system and method |
US7386765B2 (en) | 2003-09-29 | 2008-06-10 | Intel Corporation | Memory device having error checking and correction |
US20050071707A1 (en) | 2003-09-30 | 2005-03-31 | Hampel Craig E. | Integrated circuit with bi-modal data strobe |
US7139965B2 (en) | 2003-10-08 | 2006-11-21 | Hewlett-Packard Development Company, L.P. | Bus device that concurrently synchronizes source synchronous data while performing error detection and correction |
US7433258B2 (en) | 2003-10-10 | 2008-10-07 | Datasecure Llc. | Posted precharge and multiple open-page RAM architecture |
US20050086424A1 (en) | 2003-10-21 | 2005-04-21 | Infineon Technologies North America Corp. | Well-matched echo clock in memory system |
US7234070B2 (en) | 2003-10-27 | 2007-06-19 | Micron Technology, Inc. | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding |
US7113418B2 (en) | 2003-11-04 | 2006-09-26 | Hewlett-Packard Development Company, L.P. | Memory systems and methods |
US7177211B2 (en) | 2003-11-13 | 2007-02-13 | Intel Corporation | Memory channel test fixture and method |
US7447953B2 (en) * | 2003-11-14 | 2008-11-04 | Intel Corporation | Lane testing with variable mapping |
US7206962B2 (en) | 2003-11-25 | 2007-04-17 | International Business Machines Corporation | High reliability memory subsystem using data error correcting code symbol sliced command repowering |
US7073010B2 (en) * | 2003-12-02 | 2006-07-04 | Super Talent Electronics, Inc. | USB smart switch with packet re-ordering for interleaving among multiple flash-memory endpoints aggregated as a single virtual USB endpoint |
US7752470B2 (en) | 2003-12-03 | 2010-07-06 | International Business Machines Corporation | Method and system for power management including device controller-based device use evaluation and power-state control |
US7155623B2 (en) | 2003-12-03 | 2006-12-26 | International Business Machines Corporation | Method and system for power management including local bounding of device group power consumption |
US20050138267A1 (en) | 2003-12-23 | 2005-06-23 | Bains Kuljit S. | Integral memory buffer and serial presence detect capability for fully-buffered memory modules |
US7171591B2 (en) | 2003-12-23 | 2007-01-30 | International Business Machines Corporation | Method and apparatus for encoding special uncorrectable errors in an error correction code |
TWI237767B (en) | 2003-12-23 | 2005-08-11 | High Tech Comp Corp | Serial/parallel data transformer module and related computer systems |
JP4085389B2 (en) | 2003-12-24 | 2008-05-14 | 日本電気株式会社 | Multiprocessor system, consistency control device and consistency control method in multiprocessor system |
US7216196B2 (en) * | 2003-12-29 | 2007-05-08 | Micron Technology, Inc. | Memory hub and method for memory system performance monitoring |
US7197670B2 (en) | 2003-12-31 | 2007-03-27 | Intel Corporation | Methods and apparatuses for reducing infant mortality in semiconductor devices utilizing static random access memory (SRAM) |
US7321979B2 (en) * | 2004-01-22 | 2008-01-22 | International Business Machines Corporation | Method and apparatus to change the operating frequency of system core logic to maximize system memory bandwidth |
US7181584B2 (en) | 2004-02-05 | 2007-02-20 | Micron Technology, Inc. | Dynamic command and/or address mirroring system and method for memory modules |
US7363436B1 (en) | 2004-02-26 | 2008-04-22 | Integrated Device Technology, Inc. | Collision detection in a multi-port memory system |
US7114109B2 (en) | 2004-03-11 | 2006-09-26 | International Business Machines Corporation | Method and apparatus for customizing and monitoring multiple interfaces and implementing enhanced fault tolerance and isolation features |
US7257683B2 (en) * | 2004-03-24 | 2007-08-14 | Micron Technology, Inc. | Memory arbitration system and method having an arbitration packet protocol |
US7120723B2 (en) | 2004-03-25 | 2006-10-10 | Micron Technology, Inc. | System and method for memory hub-based expansion bus |
US7200832B2 (en) | 2004-03-26 | 2007-04-03 | Lsi Logic Corp | Macro cell for integrated circuit physical layer interface |
US7213082B2 (en) | 2004-03-29 | 2007-05-01 | Micron Technology, Inc. | Memory hub and method for providing memory sequencing hints |
US20050220232A1 (en) * | 2004-03-31 | 2005-10-06 | Nokia Corporation | Circuit arrangement and a method to transfer data on a 3-level pulse amplitude modulation (PAM-3) channel |
US9047094B2 (en) | 2004-03-31 | 2015-06-02 | Icera Inc. | Apparatus and method for separate asymmetric control processing and data path processing in a dual path processor |
US7724750B2 (en) * | 2004-04-01 | 2010-05-25 | Nokia Corporation | Expedited data transmission in packet based network |
US20050235072A1 (en) * | 2004-04-17 | 2005-10-20 | Smith Wilfred A | Data storage controller |
TWI267870B (en) | 2004-05-10 | 2006-12-01 | Hynix Semiconductor Inc | Semiconductor memory device for controlling output timing of data depending on frequency variation |
US7162567B2 (en) | 2004-05-14 | 2007-01-09 | Micron Technology, Inc. | Memory hub and method for memory sequencing |
US7222213B2 (en) | 2004-05-17 | 2007-05-22 | Micron Technology, Inc. | System and method for communicating the synchronization status of memory modules during initialization of the memory modules |
US7304905B2 (en) | 2004-05-24 | 2007-12-04 | Intel Corporation | Throttling memory in response to an internal temperature of a memory device |
US7363419B2 (en) | 2004-05-28 | 2008-04-22 | Micron Technology, Inc. | Method and system for terminating write commands in a hub-based memory system |
US20060010339A1 (en) | 2004-06-24 | 2006-01-12 | Klein Dean A | Memory system and method having selective ECC during low power refresh |
US7500123B2 (en) | 2004-06-28 | 2009-03-03 | Ati Technologies Ulc | Apparatus and method for reducing power consumption in a graphics processing device |
US7318130B2 (en) | 2004-06-29 | 2008-01-08 | Intel Corporation | System and method for thermal throttling of memory modules |
US20060004953A1 (en) * | 2004-06-30 | 2006-01-05 | Vogt Pete D | Method and apparatus for increased memory bandwidth |
US20060036826A1 (en) | 2004-07-30 | 2006-02-16 | International Business Machines Corporation | System, method and storage medium for providing a bus speed multiplier |
US7224595B2 (en) | 2004-07-30 | 2007-05-29 | International Business Machines Corporation | 276-Pin buffered memory module with enhanced fault tolerance |
US7539800B2 (en) | 2004-07-30 | 2009-05-26 | International Business Machines Corporation | System, method and storage medium for providing segment level sparing |
US7296129B2 (en) | 2004-07-30 | 2007-11-13 | International Business Machines Corporation | System, method and storage medium for providing a serialized memory interface with a bus repeater |
US7091890B1 (en) | 2004-08-17 | 2006-08-15 | Xilinx, Inc. | Multi-purpose source synchronous interface circuitry |
US7404118B1 (en) | 2004-09-02 | 2008-07-22 | Sun Microsystems, Inc. | Memory error analysis for determining potentially faulty memory components |
US7260661B2 (en) * | 2004-09-03 | 2007-08-21 | Intel Corporation | Processing replies to request packets in an advanced switching context |
US8621304B2 (en) * | 2004-10-07 | 2013-12-31 | Hewlett-Packard Development Company, L.P. | Built-in self-test system and method for an integrated circuit |
US7360027B2 (en) * | 2004-10-15 | 2008-04-15 | Intel Corporation | Method and apparatus for initiating CPU data prefetches by an external agent |
US20060095679A1 (en) * | 2004-10-28 | 2006-05-04 | Edirisooriya Samantha J | Method and apparatus for pushing data into a processor cache |
US7331010B2 (en) | 2004-10-29 | 2008-02-12 | International Business Machines Corporation | System, method and storage medium for providing fault detection and correction in a memory subsystem |
US7334070B2 (en) | 2004-10-29 | 2008-02-19 | International Business Machines Corporation | Multi-channel memory architecture for daisy chained arrangements of nodes with bridging between memory channels |
US20060112238A1 (en) | 2004-11-23 | 2006-05-25 | Sujat Jamil | Techniques for pushing data to a processor cache |
US7404133B2 (en) | 2004-12-12 | 2008-07-22 | Hewlett-Packard Development Company, L.P. | Error detection and correction employing modulation symbols satisfying predetermined criteria |
US20060161733A1 (en) * | 2005-01-19 | 2006-07-20 | Emulex Design & Manufacturing Corporation | Host buffer queues |
US20060168407A1 (en) | 2005-01-26 | 2006-07-27 | Micron Technology, Inc. | Memory hub system and method having large virtual page size |
US20060195631A1 (en) | 2005-01-31 | 2006-08-31 | Ramasubramanian Rajamani | Memory buffers for merging local data from memory modules |
JP4516458B2 (en) * | 2005-03-18 | 2010-08-04 | 株式会社日立製作所 | Failover cluster system and failover method |
US7481526B2 (en) | 2005-03-31 | 2009-01-27 | Fujifilm Corporation | Image forming apparatus |
US7861055B2 (en) | 2005-06-07 | 2010-12-28 | Broadcom Corporation | Method and system for on-chip configurable data ram for fast memory and pseudo associative caches |
US20070016698A1 (en) * | 2005-06-22 | 2007-01-18 | Vogt Pete D | Memory channel response scheduling |
US20070005922A1 (en) * | 2005-06-30 | 2007-01-04 | Swaminathan Muthukumar P | Fully buffered DIMM variable read latency |
US20070025304A1 (en) * | 2005-07-26 | 2007-02-01 | Rangsan Leelahakriengkrai | System and method for prioritizing transmission legs for precaching data |
US7328381B2 (en) * | 2005-08-01 | 2008-02-05 | Micron Technology, Inc. | Testing system and method for memory modules having a memory hub architecture |
US7319340B2 (en) | 2005-08-01 | 2008-01-15 | Micron Technology, Inc. | Integrated circuit load board and method having on-board test circuit |
US7865570B2 (en) | 2005-08-30 | 2011-01-04 | Illinois Institute Of Technology | Memory server |
US7430145B2 (en) | 2005-09-16 | 2008-09-30 | Hewlett-Packard Development Company, L.P. | System and method for avoiding attempts to access a defective portion of memory |
US20070165457A1 (en) | 2005-09-30 | 2007-07-19 | Jin-Ki Kim | Nonvolatile memory system |
US7496777B2 (en) | 2005-10-12 | 2009-02-24 | Sun Microsystems, Inc. | Power throttling in a memory system |
US7685392B2 (en) | 2005-11-28 | 2010-03-23 | International Business Machines Corporation | Providing indeterminate read data latency in a memory system |
US7386771B2 (en) | 2006-01-06 | 2008-06-10 | International Business Machines Corporation | Repair of memory hard failures during normal operation, using ECC and a hard fail identifier circuit |
US7353316B2 (en) | 2006-03-24 | 2008-04-01 | Micron Technology, Inc. | System and method for re-routing signals between memory system components |
US7636813B2 (en) | 2006-05-22 | 2009-12-22 | International Business Machines Corporation | Systems and methods for providing remote pre-fetch buffers |
JP5388406B2 (en) | 2006-06-20 | 2014-01-15 | キヤノン株式会社 | Memory system |
US20080010566A1 (en) | 2006-06-21 | 2008-01-10 | Chang Tsung-Yung Jonathan | Disabling portions of memory with non-deterministic errors |
US20080162807A1 (en) | 2006-12-29 | 2008-07-03 | Rothman Michael A | Method and apparatus for redundant memory arrays |
US7877666B2 (en) | 2006-12-30 | 2011-01-25 | Intel Corporation | Tracking health of integrated circuit structures |
US8041989B2 (en) | 2007-06-28 | 2011-10-18 | International Business Machines Corporation | System and method for providing a high fault tolerant memory system |
US20090003335A1 (en) * | 2007-06-29 | 2009-01-01 | International Business Machines Corporation | Device, System and Method of Fragmentation of PCI Express Packets |
-
2005
- 2005-11-28 US US11/289,193 patent/US7685392B2/en not_active Expired - Fee Related
-
2006
- 2006-11-23 TW TW095143452A patent/TWI399649B/en not_active IP Right Cessation
- 2006-11-28 CN CN2006800412429A patent/CN101300556B/en not_active Expired - Fee Related
- 2006-11-28 WO PCT/EP2006/068984 patent/WO2007060250A1/en active Application Filing
- 2006-11-28 JP JP2008541760A patent/JP5186382B2/en not_active Expired - Fee Related
- 2006-11-28 EP EP06819806A patent/EP1958073A1/en not_active Withdrawn
-
2007
- 2007-04-17 US US11/736,196 patent/US20070183331A1/en not_active Abandoned
- 2007-08-22 US US11/843,271 patent/US8151042B2/en not_active Expired - Fee Related
- 2007-08-22 US US11/843,150 patent/US8145868B2/en not_active Expired - Fee Related
-
2012
- 2012-02-16 US US13/397,819 patent/US8327105B2/en not_active Expired - Fee Related
- 2012-02-16 US US13/397,827 patent/US8495328B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005038660A2 (en) * | 2003-10-17 | 2005-04-28 | Micron Technology, Inc. | Method and apparatus for sending data from multiple sources over a communications bus |
US20050086441A1 (en) * | 2003-10-20 | 2005-04-21 | Meyer James W. | Arbitration system and method for memory responses in a hub-based memory system |
US20050177677A1 (en) * | 2004-02-05 | 2005-08-11 | Jeddeloh Joseph M. | Arbitration system having a packet memory and method for memory responses in a hub-based memory system |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011505036A (en) * | 2007-11-26 | 2011-02-17 | スパンション エルエルシー | Storage system and method |
JP2011505037A (en) * | 2007-11-26 | 2011-02-17 | スパンション エルエルシー | Read data buffering system and method |
JP2011505038A (en) * | 2007-11-26 | 2011-02-17 | スパンション エルエルシー | How to set parameters and determine latency in a chained device system |
US8732360B2 (en) | 2007-11-26 | 2014-05-20 | Spansion Llc | System and method for accessing memory |
US8874810B2 (en) | 2007-11-26 | 2014-10-28 | Spansion Llc | System and method for read data buffering wherein analyzing policy determines whether to decrement or increment the count of internal or external buffers |
US8930593B2 (en) | 2007-11-26 | 2015-01-06 | Spansion Llc | Method for setting parameters and determining latency in a chained device system |
Also Published As
Publication number | Publication date |
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CN101300556A (en) | 2008-11-05 |
US20120151171A1 (en) | 2012-06-14 |
US20070286199A1 (en) | 2007-12-13 |
TWI399649B (en) | 2013-06-21 |
JP5186382B2 (en) | 2013-04-17 |
US8327105B2 (en) | 2012-12-04 |
CN101300556B (en) | 2010-05-19 |
US20070183331A1 (en) | 2007-08-09 |
TW200739353A (en) | 2007-10-16 |
EP1958073A1 (en) | 2008-08-20 |
JP2009517725A (en) | 2009-04-30 |
US8151042B2 (en) | 2012-04-03 |
US8145868B2 (en) | 2012-03-27 |
US7685392B2 (en) | 2010-03-23 |
US20070286078A1 (en) | 2007-12-13 |
US20120151172A1 (en) | 2012-06-14 |
US20070160053A1 (en) | 2007-07-12 |
US8495328B2 (en) | 2013-07-23 |
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