WO2007059085A3 - Small and power-efficient cache that can provide data for background dma devices while the processor is in a low-power state - Google Patents

Small and power-efficient cache that can provide data for background dma devices while the processor is in a low-power state Download PDF

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Publication number
WO2007059085A3
WO2007059085A3 PCT/US2006/044095 US2006044095W WO2007059085A3 WO 2007059085 A3 WO2007059085 A3 WO 2007059085A3 US 2006044095 W US2006044095 W US 2006044095W WO 2007059085 A3 WO2007059085 A3 WO 2007059085A3
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WO
WIPO (PCT)
Prior art keywords
microprocessor
cache
power
mini
power state
Prior art date
Application number
PCT/US2006/044095
Other languages
French (fr)
Other versions
WO2007059085A2 (en
Inventor
Laurent R Moll
Yu-Quin Cheng
Peter N Glaskowsky
Seungyoon Peter Song
Original Assignee
Montalvo Systems Inc
Laurent R Moll
Yu-Quin Cheng
Peter N Glaskowsky
Seungyoon Peter Song
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/351,058 external-priority patent/US7412570B2/en
Application filed by Montalvo Systems Inc, Laurent R Moll, Yu-Quin Cheng, Peter N Glaskowsky, Seungyoon Peter Song filed Critical Montalvo Systems Inc
Priority to CN2006800507749A priority Critical patent/CN101356510B/en
Priority to EP06827787A priority patent/EP1958070A2/en
Publication of WO2007059085A2 publication Critical patent/WO2007059085A2/en
Publication of WO2007059085A3 publication Critical patent/WO2007059085A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G06F1/3225—Monitoring of peripheral devices of memory devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6042—Allocation of cache space to multiple users or processors
    • G06F2212/6046—Using a specific cache allocation policy other than replacement policy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data. The microprocessor implements one or more processors having associated cache systems (such as various arrangements of first-, second-, and higher-level caches).
PCT/US2006/044095 2005-11-15 2006-11-14 Small and power-efficient cache that can provide data for background dma devices while the processor is in a low-power state WO2007059085A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2006800507749A CN101356510B (en) 2005-11-15 2006-11-14 Small and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power state
EP06827787A EP1958070A2 (en) 2005-11-15 2006-11-14 Small and power-efficient cache that can provide data for background dma devices while the processor is in a low-power state

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
US73673605P 2005-11-15 2005-11-15
US73663205P 2005-11-15 2005-11-15
US60/736,736 2005-11-15
US60/736,632 2005-11-15
US76122006P 2006-01-23 2006-01-23
US60/761,220 2006-01-23
US76192506P 2006-01-25 2006-01-25
US60/761,925 2006-01-25
US11/351,058 US7412570B2 (en) 2005-11-15 2006-02-09 Small and power-efficient cache that can provide data for background DNA devices while the processor is in a low-power state
US11/351,058 2006-02-09
US11/559,069 2006-11-13
US11/559,069 US7958312B2 (en) 2005-11-15 2006-11-13 Small and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power state

Publications (2)

Publication Number Publication Date
WO2007059085A2 WO2007059085A2 (en) 2007-05-24
WO2007059085A3 true WO2007059085A3 (en) 2007-08-09

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PCT/US2006/044095 WO2007059085A2 (en) 2005-11-15 2006-11-14 Small and power-efficient cache that can provide data for background dma devices while the processor is in a low-power state

Country Status (4)

Country Link
US (1) US7958312B2 (en)
EP (1) EP1958070A2 (en)
TW (1) TWI349198B (en)
WO (1) WO2007059085A2 (en)

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Also Published As

Publication number Publication date
TWI349198B (en) 2011-09-21
US20070186057A1 (en) 2007-08-09
TW200809496A (en) 2008-02-16
EP1958070A2 (en) 2008-08-20
US7958312B2 (en) 2011-06-07
WO2007059085A2 (en) 2007-05-24

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