WO2007038656A1 - Semiconductor device including a front side strained superlattice layer and a back side stress layer and associated methods - Google Patents
Semiconductor device including a front side strained superlattice layer and a back side stress layer and associated methods Download PDFInfo
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- WO2007038656A1 WO2007038656A1 PCT/US2006/037791 US2006037791W WO2007038656A1 WO 2007038656 A1 WO2007038656 A1 WO 2007038656A1 US 2006037791 W US2006037791 W US 2006037791W WO 2007038656 A1 WO2007038656 A1 WO 2007038656A1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
- H01L29/151—Compositional structures
- H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7849—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being provided under the channel
Definitions
- SEMICONDUCTOR DEVICE INCLUDING A FRONT SIDE STRAINED SUPERLATTICE LAYER AND A BACK SIDE STRESS LAYER AND
- the present invention relates to the field of semiconductors, and, more particularly, to semiconductors having enhanced properties based upon energy band engineering and associated methods .
- 6,472,685 B2 to Takagi discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an n-channel MOSFET is asserted to have a higher mobility.
- U.S. Patent No. 4,937,204 to Ishibashi et al discloses a superlattice in which a plurality of layers, less than eight monolayers, and containing a fraction or a binary compound semiconductor layers, are alternately and epitaxially grown.
- U.S. Patent No. 5,357,119 to Wang et al discloses a Si-Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice.
- U.S. Patent No. 5,683,934 to Candelaria discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material substitutionalIy present in the silicon lattice at a percentage that places the channel layer under tensile stress.
- U.S. Patent No. 5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barriers. Each barrier region consists of alternate layers of SiO 2 /Si with a thickness generally in a range of two to six monolayers. A much thicker section of silicon is sandwiched between the barriers.
- An article entitled "Phenomena in silicon nanostructure devices" also to Tsu and published online September 6, 2000 by Applied Physics and Materials Science & Processing, pp. 391-402 discloses a semiconductor-atomic superlattice (SAS) of silicon and oxygen. The Si/0 superlattice is disclosed as useful in a silicon quantum and light-emitting devices.
- SAS semiconductor-atomic superlattice
- a green electromuminescence diode structure was constructed and tested. Current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS.
- the disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms, and CO molecules. The silicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial with a fairly low defect density.
- One SAS structure included a 1.1 nm thick silicon portion that is about eight atomic layers of silicon, and another structure had twice this thickness of silicon.
- An article to Luo et al. entitled “Chemical Design of Direct-Gap Light-Emitting Silicon” published in Physical Review Letters, Vol. 89, No. 7 (August 12, 2002) further discusses the light emitting SAS structures of Tsu.
- the application discloses that material parameters, for example, the location of band minima, effective mass, etc., can be tailored to yield new aperiodic materials with desirable band-structure characteristics.
- Other parameters such as electrical conductivity, thermal conductivity and dielectric permittivity or magnetic permeability are disclosed as also possible to be designed into the material .
- Greater mobility may increase device speed and/or reduce device power consumption. With greater mobility, device performance can also be maintained despite the continued shift to smaller devices and new device configurations.
- a semiconductor device which may include a semiconductor substrate having front and back surfaces, a strained superlattice layer adjacent the front surface of the semiconductor substrate and comprising a plurality of stacked groups of layers, and a stress layer on the back surface of the substrate and comprising a material different than the semiconductor substrate. More particularly, each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
- the stress layer may be an oxide, a nitride, another superlattice, etc.
- the semiconductor device may further include regions for causing transport of charge carriers through the strained superlattice layer in a parallel direction relative to the stacked groups of layers.
- the strained superlattice layer may have a compressive strain as well as a tensile strain.
- each base semiconductor portion may include silicon, and each non-semiconductor monolayer may include oxygen. More generally, each base semiconductor portion may include a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II- VI semiconductors, and each non-semiconductor monolayer may include a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon- oxygen. Furthermore, adjacent base semiconductor portions of the superlattice may be chemically bound together. Also, each non-semiconductor monolayer may be a single monolayer thick. Additionally, the strained superlattice layer may further include a base semiconductor cap layer on an uppermost group of layers.
- the semiconductor substrate may comprise a monocrystalline silicon substrate, for example. Also by way of example, the semiconductor substrate may have a thickness of less than about 700 microns.
- FIG. 1 is a schematic cross-sectional view of a semiconductor device in accordance with the present invention including a strained superlattice and a stress layer.
- FIG. 2 is a greatly enlarged schematic cross- sectional view of the superlattice as shown in FIG. 1.
- FIG. 3 is a perspective schematic atomic diagram of a portion of the superlattice shown in FIG. 1.
- FIG. 4 is a greatly enlarged schematic cross- sectional view of another embodiment of a superlattice that may be used in the device of FIG. 1.
- FIG. 5A is a graph of the calculated band structure from the gamma point (G) for both bulk silicon as in the prior art, and for the 4/1 Si/O superlattice as shown in FIGS. 1-3.
- FIG. 5B is a graph of the calculated band structure from the Z point for both bulk silicon as in the prior art, and for the 4/1 Si/O superlattice as shown in FIGS. 1-3.
- FIG. 5C is a graph of the calculated band structure from both the gamma and Z points for both bulk silicon as in the prior art, and for the 5/1/3/1 Si/0 superlattice as shown in PIG. 4.
- FIGS. 6 and 7 are schematic cross-sectional views illustrating steps for forming the stress layer and strained superlattice of the device of FIG. 1.
- the present invention relates to controlling the properties of semiconductor materials at the atomic or molecular level to achieve improved performance within semiconductor devices. Further, the invention relates to the identification, creation, and use of improved materials for use in the conduction paths of semiconductor devices.
- f is the Fermi-Dirac distribution
- E F is the Fermi energy
- T is the temperature
- E(k,n) is the energy of an electron in the state corresponding to wave vector k and the n th energy band
- the indices i and j refer to Cartesian coordinates x, y and z
- the integrals are taken over the Brillouin zone (B. Z.)
- the summations are taken over bands with energies above and below the Fermi energy for electrons and holes respectively.
- Applicants' definition of the conductivity reciprocal effective mass tensor is such that a tensorial component of the conductivity of the material is greater for greater values of the corresponding component of the conductivity reciprocal effective mass tensor.
- the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically for a preferred direction of charge carrier transport.
- the inverse of the appropriate tensor element is referred to as the conductivity effective mass.
- the conductivity effective mass for electrons/holes as described above and calculated in the direction of intended carrier transport is used to distinguish improved materials.
- a strained superlattice 25 material for a channel region in a MOSFET device A planar MOSFET 20 including the strained superlattice 25 in accordance with the invention is now first described with reference to FIG. 1.
- the materials identified herein could be used in many different types of semiconductor devices, such as discrete devices and/or integrated circuits.
- another application in which the strained superlattice 25 may be used is in FINFETs, as further described in U.S. Application Serial No. 11/426,969, which is assigned to the present Assignee and is hereby incorporated herein in its entirety by reference.
- the illustrated MOSFET 20 includes a semiconductor substrate 21, a stress layer 26 on a back surface of the substrate (i.e., below the substrate in FIG. 1) , source and drain regions 22, 23, and the strained superlattice layer 25 on a front surface of the substrate (i.e., above, the substrate in FIG. 1) between the source and drain regions. More particularly, the substrate 21 may be implanted with an appropriate dopant (s) to provide the source and drain regions 22, 23, as will be appreciated by those skilled in the art. It should be noted that while the superlattice 25 is in contact with the front surface of the semiconductor substrate in the illustrated example, this need not be the case in all embodiments.
- an insulating layer may be positioned between the semiconductor substrate 21 and the superlattice 25, as will be appreciated by those skilled in the art .
- the stress layer 26 may include a different material than the substrate 21 to thereby impart preferential strain on the substrate which, in turn, imparts the desired strain on the superlattice 25, as will be appreciated by those skilled in the art .
- the substrate 21 may be a monocrystalline silicon substrate
- the stress layer 26 may be an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride) , another semiconductor, or it may be another superlattice.
- the stress layer 26 including a different material than the substrate 21 it is meant that that (a) the stress layer may include at least one material not significantly present in the substrate (oxygen, nitrogen, etc.), although the substrate and stress layer could both include common materials such as silicon, etc., or (b) that the substrate and stress layers may be different materials (e.g., a silicon substrate and a germanium stress layer) .
- the substrate 21 and stress layer 26 either a tensile or a compressive strain may be induced in the superlattice 25, as will be appreciated by those skilled in the art.
- compositions of the substrate 21 and stress layer 26 may be chosen to induce a compressive strain in the superlattice layer 25 that may advantageously provide further mobility enhancement of the superlattice in P-channel FET devices, for example.
- a low pressure chemical vapor deposition (LPCVD) or plasma enhanced CVD (PECVD) film or layer 30, which in the illustrated embodiment is a superlattice film, is deposited under appropriate conditions (temperature, pressure, thickness) for the given materials on the back surface of the substrate 21 (e.g., a single crystal (monocrystalline) silicon wafer) to advantageously cause desired strain in the wafer during manufacture of the semiconductor device 20 (FIG. 6) .
- the wafer or substrate 21 may have a thickness of less than about 700 microns.
- the strain imparted by the stress layer 26 may either be compressive or tensile, depending upon the given materials and deposition conditions, as noted above. Again, inducing desired strain in this manner allows the silicon lattice on the front (i.e., the top side opposite the film 30) surface of the wafer 21 to either expand or contract appropriately.
- this lattice parameter change may potentially be adjusted by the desired amount to allow a semiconductor superlattice 25, such as those described below, to be epitaxially grown on the front surface of the substrate 21 with improved lattice parameter match between the superlattice and the underlying silicon surface (FIG. 7) .
- a semiconductor superlattice 25 such as those described below
- the use of the stress layer 30 may advantageously increase the critical thickness of the epitaxial growth due to the pre- engineered lattice parameter of the underlying silicon surface. As such, this may also allow for thicker superlattices 25 that have reduced incidence of crystalline defects as well as atomically smoother surfaces, compared to superlattices grown directly on bulk silicon wafers.
- Source/drain suicide layers 30, 31 and source/drain contacts 32, 33 illustratively overlie the source/drain regions 22, 23, as will be appreciated by those skilled in the art.
- a gate 35 illustratively includes a gate insulating layer 37 adjacent the channel provided by the strained superlattice layer 25, and a gate electrode layer 36 on the gate layer. Sidewall spacers 40, 41 are also provided in the illustrated MOSFET 20.
- the semiconductor device such as the illustrated MOSFET 20, enjoys a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present.
- the superlattice 25 may further have a substantially direct energy bandgap that may be particularly advantageous for opto-electronic devices, for example, such as those set forth in the co-pending application entitled INTEGRATED CIRCUIT COMPRISING AN ACTIVE OPTICAL DEVICE HAVING AN ENERGY BAND ENGINEERED SUPERLATTICE, U.S. Patent Application Serial No. 10/936,903, which is assigned to the present Assignee and is hereby incorporated herein in its entirety by reference.
- the source/drain regions 22, 23 and gate 35 of the MOSFET 20 may be considered as regions for causing the transport of charge carriers through the strained superlattice layer 25 in a parallel direction relative to the layers of the stacked groups 45a-45n, as will be discussed further below. That is, the channel of the device is defined within the superlattice 25. Other such regions are also contemplated by the present invention.
- the superlattice 25 may advantageously act as an interface for the gate dielectric layer 37.
- the channel region may be defined in the lower portion of the strained superlattice 25 (although some of the channel may also be defined in the semiconductor material below the superlattice) , while the upper portion thereof insulates the channel from the dielectric layer 37.
- the channel may be defined solely in the substrate 21, and the strained superlattice layer 25 may be included merely as an insulation/interface layer, for example .
- the superlattice 25 as a dielectric interface layer may be particularly appropriate where relatively high-K gate dielectric materials are used.
- the superlattice 25 may advantageously provide reduced scattering and, thus, enhanced mobility with respect to prior art insulation layers (e.g., silicon oxides) typically used for high-K dielectric interfaces.
- use of the superlattice 25 as an insulator for applications with high-K dielectrics may result in smaller overall thicknesses, and thus improved device capacitance. This is because the superlattice 25 may be formed in relatively small thicknesses yet still provide desired insulating properties, as discussed further in co-pending U.S. Application Serial No.
- the materials or structures are in the form of a superlattice 25 whose structure is controlled at the atomic or molecular level and may be formed using known techniques of atomic or molecular layer deposition.
- the superlattice 25 includes a plurality of layer groups 45a- 45n arranged in stacked relation, as perhaps best understood with specific reference to the schematic cross-sectional view of FIG. 2.
- an intermediate annealing process as described in co-pending U.S. Application Serial No. 11/136,834, which is assigned to the present Assignee and is hereby incorporated herein in its entirety by reference, may also be used to advantageously reduce defects and provide smother layer surfaces during fabrication.
- Each group of layers 45a-45n of the superlattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining a respective base semiconductor portion 46a-46n and an energy band-modifying layer 50 thereon.
- the energy band- modifying layers 50 are indicated by stippling in FIG. 2 for clarity of explanation.
- the energy-band modifying layer 50 illustratively comprises one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. That is, opposing base semiconductor monolayers 46 in adjacent groups of layers 45a-45n are chemically bound together. For example, in the case of silicon monolayers 46, some of the silicon atoms in the upper or top semiconductor monolayer of the group of monolayers 46a will be covalently bonded with silicon atoms in the lower or bottom monolayer of the group 46b, as seen in FIG. 3. This allows the crystal lattice to continue through the groups of layers despite the presence of the non-semiconductor monolayer (s) (e.g., oxygen monolayer (s) ) .
- s non-semiconductor monolayer
- more than one such monolayer may be possible.
- reference herein to a non-semiconductor or semiconductor monolayer means that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material, such as semiconductor, may not necessarily exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.
- the semiconductor device such as the illustrated MOSFET 20 enjoys a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present.
- the superlattice 25 may further have a substantially direct energy bandgap that may be particularly advantageous for opto-electronic devices, for example, as described in further detail below.
- all of the above- described properties of the superlattice 25 need not be utilized in every application.
- the superlattice 25 may only be used for its dopant blocking/insulation properties or its enhanced mobility, or it may be used for both in other applications, as will be appreciated by those skilled in the art .
- more than one non- semiconductor monolayer may be present in the energy band modifying layer 50.
- the number of non- semiconductor monolayers in the energy band-modifying layer 50 may preferably be less than about five monolayers to thereby provide the desired energy band- modifying properties.
- the superlattice 25 also illustratively includes a cap layer 52 on an upper layer group 45n.
- the cap layer 52 may comprise a plurality of base semiconductor monolayers 46.
- the cap layer 52 may have between 2 to 100 monolayers of the base semiconductor, and, more preferably between 10 to 50 monolayers.
- Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II -VI semiconductors.
- Group IV semiconductors also includes Group IV-IV semiconductors as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example.
- Each energy band-modifying layer 50 may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon- oxygen, for example.
- the non-semiconductor is also desirably thermally stable through deposition of a next layer to thereby facilitate manufacturing.
- the non-semiconductor may be another inorganic or organic element or compound that is compatible with the given semiconductor processing as will be appreciated by those skilled in the art.
- the term monolayer is meant to include a single atomic layer and also a single molecular layer.
- the energy band- modifying layer 50 provided by a single monolayer is also meant to include a monolayer wherein not all of the possible sites are occupied, as noted above.
- a 4/1 repeating structure is illustrated for silicon as the base semiconductor material , and oxygen as the energy band-modifying material. Only half of the possible sites for oxygen are occupied.
- this one half occupation would not necessarily be the case, as will be appreciated by those skilled in the art. Indeed it can be seen even in this schematic diagram, that individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane as will also be appreciated by those of skill in the art of atomic deposition. By way of example, a preferred occupation range is from about one-eighth to one-half of the possible oxygen sites being full, although other numbers may be used in certain embodiments. [0052] Silicon and oxygen are currently widely used in conventional semiconductor processing, and, hence, manufacturers will be readily able to use these materials as described herein. Atomic or monolayer deposition is also now widely used. Accordingly, semiconductor devices incorporating the superlattice 25 may be readily adopted and implemented as will be appreciated by those skilled in the art .
- the number of silicon monolayers should desirably be seven or less so that the energy band of the superlattice is common or relatively uniform throughout to achieve the desired advantages.
- more than seven silicon layers may be used in some embodiments.
- the 4/1 repeating structure shown in FIGS. 2 and 3, for Si/O has been modeled to indicate an enhanced mobility for electrons and holes in the X direction.
- the calculated conductivity effective mass for electrons is 0.26 and for the 4/1 SiO superlattice in the X direction it is 0.12 resulting in a ratio of 0.46.
- the calculation for holes yields values of 0.36 for bulk silicon and 0.16 for the 4/1 Si/O superlattice resulting in a ratio of 0.44.
- other devices may benefit from a more uniform increase in mobility in any direction parallel to the groups of layers. It may also be beneficial to have an increased mobility for both electrons or holes, or just one of these types of charge carriers as will be appreciated by those skilled in the art.
- the lower conductivity effective mass for the 4/1 Si/0 embodiment of the superlattice 25 may be less than two-thirds the conductivity effective mass than would otherwise occur, and this applies for both electrons and holes.
- the superlattice 25 may further comprise at least one type of conductivity dopant therein as will also be appreciated by those skilled in the art. It may be especially appropriate to dope at least a portion of the superlattice 25 if the superlattice is to provide some or all of the channel.
- the superlattice 25 or portions thereof may also remain substantially undoped in some embodiments, as described further in U.S. Application Serial No. 11/136,757, which is assigned to the present Assignee and is hereby incorporated herein in its entirety by reference .
- FIG. 4 another embodiment of a superlattice 25' in accordance with the invention having different properties is now described.
- a repeating pattern of 3/1/5/1 is illustrated. More particularly, the lowest base semiconductor portion 46a' has three monolayers, and the second lowest base semiconductor portion 46b' has five monolayers. This pattern repeats throughout the superlattice 25' .
- the energy band-modifying layers 50 ' may each include a single monolayer.
- the enhancement of charge carrier mobility is independent of orientation in the plane of the layers.
- all of the base semiconductor portions of a superlattice may be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick. In still other embodiments, all of the base semiconductor portions may be a different number of monolayers thick.
- DFT Density Functional Theory
- FIG. 5A shows the calculated band structure from the gamma point (G) for both bulk silicon (represented by continuous lines) and for the 4/1 Si/0 superlattice 25 as shown in FIGS. 1-3 (represented by dotted lines) .
- the directions refer to the unit cell of the 4/1 Si/0 structure and not to the conventional unit cell of Si, although the (001) direction in the figure does correspond to the (001) direction of the conventional unit cell of Si, and, hence, shows the expected location of the Si conduction band minimum.
- the (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell.
- the bands of Si on the figure are folded to represent them on the appropriate reciprocal lattice directions for the 4/1 Si/0 structure.
- the conduction band minimum for the 4/1 Si/O structure is located at the gamma point in contrast to bulk silicon (Si) , whereas the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction which we refer to as the Z point.
- the greater curvature of the conduction band minimum for the 4/1 Si/O structure compared to the curvature of the conduction band minimum for Si owing to the band splitting due to the perturbation introduced by the additional oxygen layer.
- FIG. 5B shows the calculated band structure from the Z point for both bulk silicon (continuous lines) and for the 4/1 Si/O superlattice 25 (dotted lines) . This figure illustrates the enhanced curvature of the valence band in the (100) direction.
- FIG. 5C shows the calculated band structure from the both the gamma and Z point for both bulk silicon (continuous lines) and for the 5/1/3/1 Si/O structure of the superlattice 25' of FIG. 4 (dotted lines) . Due to the symmetry of the 5/1/3/1 Si/O structure, the calculated band structures in the (100) and (010) directions are equivalent. Thus the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e. perpendicular to the (001) stacking direction. Note that in the 5/1/3/1 Si/O example the conduction band minimum and the valence band maximum are both at or close to the Z point .
Abstract
Description
Claims
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CA002623549A CA2623549A1 (en) | 2005-09-26 | 2006-09-26 | Semiconductor device including a front side strained superlattice layer and a back side stress layer and associated methods |
JP2008532508A JP2009510727A (en) | 2005-09-26 | 2006-09-26 | Semiconductor device having strained superlattice layer on the front side, stress layer on the back side, and related method |
AU2006294552A AU2006294552A1 (en) | 2005-09-26 | 2006-09-26 | Semiconductor device including a front side strained superlattice layer and a back side stress layer and associated methods |
EP06825194A EP1941548A1 (en) | 2005-09-26 | 2006-09-26 | Semiconductor device including a front side strained superlattice layer and a back side stress layer and associated methods |
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US72058205P | 2005-09-26 | 2005-09-26 | |
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US11/534,796 | 2006-09-25 | ||
US11/534,796 US20070063185A1 (en) | 2003-06-26 | 2006-09-25 | Semiconductor device including a front side strained superlattice layer and a back side stress layer |
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EP (1) | EP1941548A1 (en) |
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FR2934716B1 (en) * | 2008-07-31 | 2010-09-10 | Commissariat Energie Atomique | SEMICONDUCTOR MATERIAL ELECTROLUMINESCENT DIODE AND MANUFACTURING METHOD THEREOF |
CN106104805B (en) * | 2013-11-22 | 2020-06-16 | 阿托梅拉公司 | Vertical semiconductor device including a superlattice punch-through stop layer stack and related methods |
WO2015077580A1 (en) | 2013-11-22 | 2015-05-28 | Mears Technologies, Inc. | Semiconductor devices including superlattice depletion layer stack and related methods |
WO2015191561A1 (en) | 2014-06-09 | 2015-12-17 | Mears Technologies, Inc. | Semiconductor devices with enhanced deterministic doping and related methods |
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WO2016187042A1 (en) | 2015-05-15 | 2016-11-24 | Atomera Incorporated | Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods |
US9721790B2 (en) | 2015-06-02 | 2017-08-01 | Atomera Incorporated | Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control |
US9558939B1 (en) | 2016-01-15 | 2017-01-31 | Atomera Incorporated | Methods for making a semiconductor device including atomic layer structures using N2O as an oxygen source |
US11094818B2 (en) * | 2019-04-23 | 2021-08-17 | Atomera Incorporated | Method for making a semiconductor device including a superlattice and an asymmetric channel and related methods |
US11862717B2 (en) * | 2021-08-24 | 2024-01-02 | Globalfoundries U.S. Inc. | Lateral bipolar transistor structure with superlattice layer and method to form same |
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US20070063185A1 (en) | 2007-03-22 |
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AU2006294552A1 (en) | 2007-04-05 |
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