WO2007031937A3 - Power management for buses in cmos circuits - Google Patents

Power management for buses in cmos circuits Download PDF

Info

Publication number
WO2007031937A3
WO2007031937A3 PCT/IB2006/053217 IB2006053217W WO2007031937A3 WO 2007031937 A3 WO2007031937 A3 WO 2007031937A3 IB 2006053217 W IB2006053217 W IB 2006053217W WO 2007031937 A3 WO2007031937 A3 WO 2007031937A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
buses
power management
cmos circuits
circuits
Prior art date
Application number
PCT/IB2006/053217
Other languages
French (fr)
Other versions
WO2007031937A2 (en
Inventor
Tim Pontius
Swati Saxena
Neal Wingen
Niranjan Ap
Original Assignee
Nxp Bv
Tim Pontius
Swati Saxena
Neal Wingen
Niranjan Ap
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=37865343&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2007031937(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Nxp Bv, Tim Pontius, Swati Saxena, Neal Wingen, Niranjan Ap filed Critical Nxp Bv
Priority to JP2008529769A priority Critical patent/JP2009508202A/en
Priority to EP06795991A priority patent/EP1927042A2/en
Priority to CN2006800333022A priority patent/CN101263441B/en
Priority to US12/066,113 priority patent/US8099614B2/en
Publication of WO2007031937A2 publication Critical patent/WO2007031937A2/en
Publication of WO2007031937A3 publication Critical patent/WO2007031937A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3253—Power saving in bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

The invention relates to a controlled shut-down of an electronic circuit or circuits such that the electrical power consumption of that circuit or circuits is minimized and that each said circuit is at a status which is a pre-determined state (42; 52) of that said circuit wherein all of its own control and messaging signals are taken to their zero level. The present invention claimed relates to the methodology of entering said circuit into this pre¬ determined state (42;52); where all said signal and messaging lines are taken to zero; thereby reducing power consumption within an electronic circuit when its status is defined as being shut-down or standby.
PCT/IB2006/053217 2005-09-12 2006-09-11 Power management for buses in cmos circuits WO2007031937A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2008529769A JP2009508202A (en) 2005-09-12 2006-09-11 Bus power management in CMOS circuits
EP06795991A EP1927042A2 (en) 2005-09-12 2006-09-11 Power management for buses in cmos circuits
CN2006800333022A CN101263441B (en) 2005-09-12 2006-09-11 Power management for buses in CMOS circuits
US12/066,113 US8099614B2 (en) 2005-09-12 2006-09-11 Power management for buses in cmos circuits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US71673005P 2005-09-12 2005-09-12
US60/716,730 2005-09-12

Publications (2)

Publication Number Publication Date
WO2007031937A2 WO2007031937A2 (en) 2007-03-22
WO2007031937A3 true WO2007031937A3 (en) 2007-10-11

Family

ID=37865343

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2006/053217 WO2007031937A2 (en) 2005-09-12 2006-09-11 Power management for buses in cmos circuits

Country Status (5)

Country Link
US (1) US8099614B2 (en)
EP (1) EP1927042A2 (en)
JP (1) JP2009508202A (en)
CN (1) CN101263441B (en)
WO (1) WO2007031937A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1394342B1 (en) * 2009-06-15 2012-06-06 St Microelectronics Srl "ENERGY SAVING IN ON-CHIP SYSTEMS"
DE102009043451A1 (en) * 2009-09-29 2011-04-21 Infineon Technologies Ag Circuitry, network-on-chip and method of transmitting information

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000065428A1 (en) * 1999-04-26 2000-11-02 Mediaq, Inc. A method and apparatus to power up an integrated device from a low power state
EP1383032A2 (en) * 2002-06-26 2004-01-21 Broadcom Corporation Method and apparatus for the conditional enablement of PCI power management
US20040151149A1 (en) * 2003-02-04 2004-08-05 Samsung Electronics Co., Ltd. Media access controller with power-save mode
US20040153678A1 (en) * 2003-02-05 2004-08-05 Infineon Technologies North America Corp. Microprocessor idle mode management system

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62117408A (en) * 1985-11-18 1987-05-28 Casio Comput Co Ltd Auto-tuning device
US6448812B1 (en) * 1998-06-11 2002-09-10 Infineon Technologies North America Corp. Pull up/pull down logic for holding a defined value during power down mode
US6360284B1 (en) * 1999-01-13 2002-03-19 Compaq Information Technologies Group, L.P. System for protecting output drivers connected to a powered-off load
GB2357601B (en) * 1999-12-23 2004-03-31 Ibm Remote power control
EP1204017B1 (en) 2000-11-03 2007-04-11 STMicroelectronics S.r.l. Device and method for selectively powering down integrated circuit blocks
US6774735B2 (en) 2002-01-17 2004-08-10 Intel Corporation Low power self-biasing oscillator circuit
US6765433B1 (en) * 2003-03-20 2004-07-20 Atmel Corporation Low power implementation for input signals of integrated circuits

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000065428A1 (en) * 1999-04-26 2000-11-02 Mediaq, Inc. A method and apparatus to power up an integrated device from a low power state
EP1383032A2 (en) * 2002-06-26 2004-01-21 Broadcom Corporation Method and apparatus for the conditional enablement of PCI power management
US20040151149A1 (en) * 2003-02-04 2004-08-05 Samsung Electronics Co., Ltd. Media access controller with power-save mode
US20040153678A1 (en) * 2003-02-05 2004-08-05 Infineon Technologies North America Corp. Microprocessor idle mode management system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1927042A2 *

Also Published As

Publication number Publication date
JP2009508202A (en) 2009-02-26
WO2007031937A2 (en) 2007-03-22
CN101263441B (en) 2012-07-04
US20080256377A1 (en) 2008-10-16
US8099614B2 (en) 2012-01-17
EP1927042A2 (en) 2008-06-04
CN101263441A (en) 2008-09-10

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