WO2007030527A3 - Photomask for the fabrication of a dual damascene structure and method for forming the same - Google Patents

Photomask for the fabrication of a dual damascene structure and method for forming the same Download PDF

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Publication number
WO2007030527A3
WO2007030527A3 PCT/US2006/034697 US2006034697W WO2007030527A3 WO 2007030527 A3 WO2007030527 A3 WO 2007030527A3 US 2006034697 W US2006034697 W US 2006034697W WO 2007030527 A3 WO2007030527 A3 WO 2007030527A3
Authority
WO
WIPO (PCT)
Prior art keywords
dual damascene
damascene structure
photomask
fabrication
forming
Prior art date
Application number
PCT/US2006/034697
Other languages
French (fr)
Other versions
WO2007030527A2 (en
Inventor
Susan S Macdonald
Original Assignee
Toppan Photomasks Inc
Susan S Macdonald
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Photomasks Inc, Susan S Macdonald filed Critical Toppan Photomasks Inc
Priority to US12/064,454 priority Critical patent/US20100215909A1/en
Priority to JP2008530164A priority patent/JP2009523312A/en
Publication of WO2007030527A2 publication Critical patent/WO2007030527A2/en
Publication of WO2007030527A3 publication Critical patent/WO2007030527A3/en

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76817—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics using printing or stamping techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

A photomask for the fabrication of dual damascene structures and a method for forming the same are provided. A method for fabricating a multilayer step-and-print lithography (SFIL) template includes providing a blank having a substrate, a metallization layer and a first resist layer. A metal layer pattern of a dual damascene structure is formed in the substrate at a first depth using a lithography system. The first resist layer is removed from the blank and a second resist later is applied. The lithography system is used to form a via layer pattern of the dual damascene structure at the first depth while the first pattern is simultaneously etched to a second depth. The first and second patterns correspond to features to be formed in multiple layers of a device using an SFIL process.
PCT/US2006/034697 2005-09-07 2006-09-06 Photomask for the fabrication of a dual damascene structure and method for forming the same WO2007030527A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/064,454 US20100215909A1 (en) 2005-09-15 2006-09-06 Photomask for the Fabrication of a Dual Damascene Structure and Method for Forming the Same
JP2008530164A JP2009523312A (en) 2005-09-07 2006-09-06 Photomask for manufacturing dual damascene structure and method of forming the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US71462705P 2005-09-07 2005-09-07
US60/714,627 2005-09-07

Publications (2)

Publication Number Publication Date
WO2007030527A2 WO2007030527A2 (en) 2007-03-15
WO2007030527A3 true WO2007030527A3 (en) 2009-04-30

Family

ID=37836413

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/034697 WO2007030527A2 (en) 2005-09-07 2006-09-06 Photomask for the fabrication of a dual damascene structure and method for forming the same

Country Status (3)

Country Link
JP (1) JP2009523312A (en)
CN (1) CN101505974A (en)
WO (1) WO2007030527A2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4684984B2 (en) * 2005-12-07 2011-05-18 キヤノン株式会社 Semiconductor device manufacturing method and article manufacturing method
DE102006030267B4 (en) * 2006-06-30 2009-04-16 Advanced Micro Devices, Inc., Sunnyvale Nano embossing technique with increased flexibility in terms of adjustment and shaping of structural elements
FR2942738B1 (en) 2009-03-03 2016-04-15 Commissariat A L'energie Atomique METHOD FOR MANUFACTURING A MOLD FOR NANO-PRINTING LITHOGRAPHY
FR2942739B1 (en) 2009-03-03 2011-05-13 Commissariat Energie Atomique METHOD FOR MANUFACTURING A MOLD FOR NANO-PRINTING LITHOGRAPHY
KR101711646B1 (en) 2009-12-11 2017-03-03 엘지디스플레이 주식회사 Mathod for forming mold for imprinting and method for forming pattern using mold for imprinting
JP5349404B2 (en) * 2010-05-28 2013-11-20 株式会社東芝 Pattern formation method
US9034233B2 (en) 2010-11-30 2015-05-19 Infineon Technologies Ag Method of processing a substrate
CN102650822B (en) * 2011-02-24 2015-03-11 中芯国际集成电路制造(上海)有限公司 Double patterned nano-imprinting module and method for producing same
JP5681552B2 (en) * 2011-04-15 2015-03-11 株式会社フジクラ Imprint mold manufacturing method and imprint mold
JP6066793B2 (en) * 2013-03-25 2017-01-25 京セラクリスタルデバイス株式会社 Piezoelectric element wafer forming method
KR102614850B1 (en) * 2016-10-05 2023-12-18 삼성전자주식회사 Method of manufacuturing semiconductor device
KR20180045354A (en) 2016-10-25 2018-05-04 엘지디스플레이 주식회사 Imprint mold and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030205658A1 (en) * 2002-05-01 2003-11-06 Molecular Imprints, Inc. Methods of inspecting a lithography template
US20030232252A1 (en) * 2002-06-18 2003-12-18 Mancini David P. Multi-tiered lithographic template and method of formation and use
US20040033424A1 (en) * 2002-08-15 2004-02-19 Talin Albert Alec Lithographic template and method of formation and use
US20040224261A1 (en) * 2003-05-08 2004-11-11 Resnick Douglas J. Unitary dual damascene process using imprint lithography

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3415335B2 (en) * 1995-08-11 2003-06-09 大日本印刷株式会社 Method for manufacturing multi-stage etching type substrate
JP3821069B2 (en) * 2002-08-01 2006-09-13 株式会社日立製作所 Method for forming structure by transfer pattern
TW200507175A (en) * 2003-06-20 2005-02-16 Matsushita Electric Ind Co Ltd Pattern forming method, and manufacturing method for semiconductor device
JP4726789B2 (en) * 2003-09-29 2011-07-20 インターナショナル・ビジネス・マシーンズ・コーポレーション Production method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030205658A1 (en) * 2002-05-01 2003-11-06 Molecular Imprints, Inc. Methods of inspecting a lithography template
US20030232252A1 (en) * 2002-06-18 2003-12-18 Mancini David P. Multi-tiered lithographic template and method of formation and use
US20040033424A1 (en) * 2002-08-15 2004-02-19 Talin Albert Alec Lithographic template and method of formation and use
US20040224261A1 (en) * 2003-05-08 2004-11-11 Resnick Douglas J. Unitary dual damascene process using imprint lithography

Also Published As

Publication number Publication date
JP2009523312A (en) 2009-06-18
WO2007030527A2 (en) 2007-03-15
CN101505974A (en) 2009-08-12

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