WO2007025521A2 - Verfahren zur herstellung eines halbleiterbauelements mit einer planaren kontaktierung und halbleiterbauelement - Google Patents
Verfahren zur herstellung eines halbleiterbauelements mit einer planaren kontaktierung und halbleiterbauelement Download PDFInfo
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- WO2007025521A2 WO2007025521A2 PCT/DE2006/001513 DE2006001513W WO2007025521A2 WO 2007025521 A2 WO2007025521 A2 WO 2007025521A2 DE 2006001513 W DE2006001513 W DE 2006001513W WO 2007025521 A2 WO2007025521 A2 WO 2007025521A2
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- Prior art keywords
- insulating layer
- component
- glass coating
- substrate
- glass
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 239000011521 glass Substances 0.000 claims abstract description 49
- 238000000576 coating method Methods 0.000 claims abstract description 48
- 239000011248 coating agent Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000012876 topography Methods 0.000 claims abstract description 6
- 238000001465 metallisation Methods 0.000 claims description 16
- 229920000642 polymer Polymers 0.000 claims description 15
- 239000005388 borosilicate glass Substances 0.000 claims description 5
- 238000003486 chemical etching Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000005488 sandblasting Methods 0.000 claims description 3
- 230000005693 optoelectronics Effects 0.000 claims 4
- 238000003475 lamination Methods 0.000 claims 1
- 238000003754 machining Methods 0.000 claims 1
- 238000007747 plating Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 4
- 230000005855 radiation Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 230000000930 thermomechanical effect Effects 0.000 description 4
- 230000032683 aging Effects 0.000 description 3
- 230000007613 environmental effect Effects 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- 229910010165 TiCu Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920006254 polymer film Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000306 component Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000000869 ion-assisted deposition Methods 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
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- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Definitions
- the present invention relates to a method according to the preamble of claim 1 and to a semiconductor device produced by the method.
- planar connection technology which is also referred to as SiPLIT technology includes a uniformly laminated over the topography fie foil in a predetermined layer thickness, the components and forms an insulating layer.
- the basic concept of a flat design with planar connection technology allows versatile, application-specific design options by using an insulating film.
- it should have an insulating layer which is resistant to aging, largely uninfluenced by environmental influences and, in conjunction with light sources, enables a high light yield.
- a semiconductor component in particular a semiconductor structure having a surface structure or topography generated on a substrate by means of electronic components, an electronic component or a plurality of electronic components are applied to a substrate and an insulating layer is applied to the substrate by means of the at least one component generated topography applied.
- contacting openings in the insulating layer are produced at contacting locations of the at least one electronic component, the insulating layer and the contacting locations are metallized planarly in the contacting openings and the metallization is structured to produce electrical connections, the insulating layer having a glass coating.
- hermetic coverage of the substrate formed structure of one or more electronic devices, particularly a structure of one or more LEDs, may be created such that the structure is not exposed to environmental influences is.
- Another advantage is the high transparency, so that a high light output is possible in conjunction with light sources. Since a glass coating has high UV stability against ultraviolet radiation, the aging resistance of the structure is improved over conventional films.
- the glass coating allows a comparatively high thermal-mechanical stability.
- the coefficient of thermal expansion CTE (coefficient of thermal expansion) of the glass coating is preferably adapted to that of the at least one component and / or the substrate.
- the coefficient of thermal expansion of the glass coating preferably has a value between 5 * 10 -7 K "1 and including 30 * 10 -7 K '1.
- the glass coating is characterized by a high chemical-physical stability.
- the insulating layer may consist entirely of the glass coating.
- the Glass coating borosilicate glass on.
- the glass coating can be made entirely of borosilicate glass.
- the glass can be alkaline. It can also be made up of several glass layers.
- a polymer coating is first applied to the components and / or the substrate and then the insulating layer, wherein a thermo-mechanical decoupling of the insulating layer is provided by the device and substrate surfaces.
- the polymer coating is preferably highly elastic so that thermo-mechanical stresses are compensated.
- differences in the coefficients of expansion (CTE) of the glass coating and component and substrate surfaces can be compensated by means of the polymer coating. This is particularly advantageous for semiconductor devices in which a strong heating of the device occurs during operation, such as in high-power LEDS.
- the polymer coating in this case reduces the risk of breakage of the glass layer due to mechanical stresses that may occur due to high temperature differences between the quiescent state and the operating state of the device.
- the insulating layer can have juxtaposed glass coatings and polymer layers.
- the insulating layer can be effectively adapted to the respective functions of the components.
- a glass coating is advantageous for LED chips, in particular for LED chips, in which at least part of the emitted radiation has wavelengths in the ultraviolet spectral range, since a glass coating has improved radiation stability compared to polymer layers.
- one or more on the substrate disposed LED chips are provided with an insulating layer of glass, while the substrate and / or one or more further arranged on the substrate components are provided with an insulating layer of a polymer.
- the glass coating is arranged only in the electrically active region of a component.
- an electrically active region for example, an LED chip
- the light-emitting region is assumed here.
- the glass coating can be applied to the surface and the side edges of an LED chip.
- the glass coating hermetically encapsulates at least one electrical component, in particular an LED chip.
- the glass coating has a thickness in the range of 5 to 500 microns.
- the glass coating is applied by means of physical vapor deposition (PVD) and / or plasma ion assisted deposition (PIAD), in particular electron-beam PVD-PIAD.
- PVD physical vapor deposition
- PIAD plasma ion assisted deposition
- the glass coating is structured by means of a lift-off method.
- contact openings are produced by means of laser processing, chemical etching, dry etching or sandblasting.
- the metallization is carried out by means of a seed layer (seed layer), for example of TiW and / or TiCu.
- seed layer for example of TiW and / or TiCu.
- a thin metallic layer is applied to the insulating layer by means of sputtering.
- CVD, PVD or electrolytic methods can be used.
- structuring of the metallization is carried out by means of a photographic process.
- FIG. 1 shows a schematic representation of a cross section through a first exemplary embodiment of a semiconductor component according to the invention
- Figure 2 is a schematic representation of a cross section through a second embodiment of a semiconductor device according to the invention.
- Figure 3 is a schematic representation of a cross section through a third embodiment of a semiconductor device according to the invention.
- FIG. 1 shows a semiconductor component in which an LED chip 2 is arranged on a substrate 1.
- the substrate 1 can For example, a wafer, a printed circuit board (PCB) and / or a flexible material.
- PCB printed circuit board
- an insulating layer 3 made of a glass, for example a thin borosilicate glass layer, is applied. This serves as a hermetic waste 'cover for the LED chip 2 and the substrate 1.
- the glass coating 3 so protects the LED chip 2 and the substrate 1 is advantageous from environmental influences such as especially moisture, dirt, or UV radiation.
- the insulating layer 3 further acts as electrical insulation between portions of the LED chip 2, in particular the side edges of the LED chip 2, and electrical connections 4, which serve for the planar electrical contacting of the LED chip.
- a planar contacting means a wireless contacting by means of a structured metallization layer, which forms the electrical connections 4.
- no bonding wire is used for contacting the LED chip 2.
- the insulating layer 3 in particular prevents a short circuit of the LED chip 2, which would otherwise occur in the case of a direct application of the metallization 4 on the side edges of the LED chip 2.
- the thin glass coating 3 is preferably produced by a PVD or PIAD method.
- the insulating layer 3 can be structured by a lift-off technique.
- openings 5 for producing planar contact plating are preferably created by laser processing, chemical etching, dry etching and / or sandblasting. Other methods are also conceivable.
- the formation of the electrical connections 4 on the insulating layer 3 preferably takes place by the application and structuring of a metallization layer.
- a thin seed layer for example of TiCu or TiW, is preferably applied to the insulating layer.
- the structuring of the metallization can be done for example by means of a photolithographic process.
- a radiation exit surface 11 of the LED chip is recessed by the metallization 4.
- the glass coating 3 is advantageously highly transparent for the radiation emitted by the LED chip 2.
- a first terminal contact 8 of the LED chip 2 is connected to a rear-side contact 6 on the side of the substrate 1 facing away from the LED chip 2.
- a second terminal contact 9 of the LED chip 2 is connected to a front side contact 7 on the component 2 facing the front side of the substrate 1.
- other variants of the contacting are conceivable.
- the encapsulation of the LED chip 2 with borosilicate glass as a hermetic cover and as a dielectric is particularly suitable for a planar connection and construction technique, as described for example in the patent application WO 03/030247 A2.
- the insulating layer has subregions of a glass coating 3 and a polymer layer 10 arranged side by side. The surface and the side flanks of the LED chip 2 are provided with the glass coating 3, while portions of the substrate 1 are insulated from the electrical connections 4 by a polymer layer 10.
- the second embodiment corresponds to the first embodiment, in particular with respect to the advantageous embodiments described in connection with FIG.
- a polymer layer 10 has been applied to the surface structure applied to the substrate, which contains the LED chip 2.
- the polymer coating is preferably highly elastic to compensate for thermo-mechanical stresses.
- the polymer layer 10 is preferably applied to the substrate and the LED chip 2 by means of a PIAD method. Due to the comparatively low process temperature at the component to be coated, the PIAD method is advantageous if, prior to application of the glass coating 3, a polymer layer 10 is applied which could degrade at high temperatures.
- the third embodiment corresponds to the first embodiment, in particular with respect to the advantageous embodiments described in connection with FIG. 1.
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP06791327A EP1920462A2 (de) | 2005-08-30 | 2006-08-30 | Verfahren zur herstellung eines halbleiterbauelements mit einer planaren kontaktierung und halbleiterbauelement |
US11/991,197 US7859005B2 (en) | 2005-08-30 | 2006-08-30 | Method for the production of a semiconductor component comprising a planar contact, and semiconductor component |
JP2008528330A JP5215853B2 (ja) | 2005-08-30 | 2006-08-30 | プレーナ形のコンタクト形成部を備えた半導体素子の作製方法および半導体素子 |
CN2006800318234A CN101253623B (zh) | 2005-08-30 | 2006-08-30 | 用于制造具有平面接触的半导体器件的方法以及半导体器件 |
KR1020087003687A KR101295606B1 (ko) | 2005-08-30 | 2006-08-30 | 평면 접점을 포함하는 반도체 소자의 제조 방법 및 반도체소자 |
Applications Claiming Priority (2)
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DE102005041099A DE102005041099A1 (de) | 2005-08-30 | 2005-08-30 | LED-Chip mit Glasbeschichtung und planarer Aufbau- und Verbindungstechnik |
DE102005041099.5 | 2005-08-30 |
Publications (2)
Publication Number | Publication Date |
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WO2007025521A2 true WO2007025521A2 (de) | 2007-03-08 |
WO2007025521A3 WO2007025521A3 (de) | 2007-05-03 |
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PCT/DE2006/001513 WO2007025521A2 (de) | 2005-08-30 | 2006-08-30 | Verfahren zur herstellung eines halbleiterbauelements mit einer planaren kontaktierung und halbleiterbauelement |
Country Status (8)
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US (1) | US7859005B2 (de) |
EP (1) | EP1920462A2 (de) |
JP (1) | JP5215853B2 (de) |
KR (1) | KR101295606B1 (de) |
CN (1) | CN101253623B (de) |
DE (1) | DE102005041099A1 (de) |
TW (1) | TWI313075B (de) |
WO (1) | WO2007025521A2 (de) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
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DE102007033288A1 (de) * | 2007-07-17 | 2009-01-22 | Siemens Ag | Elektronisches Bauelement und Vorrichtung mit hoher Isolationsfestigkeit sowie Verfahren zu deren Herstellung |
WO2009079978A1 (de) * | 2007-12-20 | 2009-07-02 | Osram Opto Semiconductors Gmbh | Optoelektronisches bauelement |
JP2011507198A (ja) * | 2007-12-21 | 2011-03-03 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | オプトエレクトロニクス部品およびその製造方法 |
WO2011026456A1 (de) * | 2009-09-03 | 2011-03-10 | Osram Opto Semiconductors Gmbh | Optoelektronisches modul aufweisend zumindest einen ersten halbleiterkörper mit einer strahlungsaustrittsseite und einer isolationsschicht und verfahren zu dessen herstellung |
WO2011032853A1 (de) * | 2009-09-18 | 2011-03-24 | Osram Opto Semiconductors Gmbh | Optoelektronisches modul |
DE102008048423B4 (de) * | 2007-09-24 | 2015-05-28 | Infineon Technologies Ag | Verfahren zum Herstellen eines Integrierten Schaltungsbauelements |
Families Citing this family (9)
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DE102008015551A1 (de) * | 2008-03-25 | 2009-10-01 | Osram Opto Semiconductors Gmbh | Optoelektronisches Bauelement mit planarer Kontaktierung und Verfahren zu dessen Herstellung |
CN102456803A (zh) * | 2010-10-20 | 2012-05-16 | 展晶科技(深圳)有限公司 | 发光二极管封装结构 |
US9437756B2 (en) | 2013-09-27 | 2016-09-06 | Sunpower Corporation | Metallization of solar cells using metal foils |
US10529646B2 (en) | 2015-04-24 | 2020-01-07 | Amosense Co., Ltd. | Methods of manufacturing a ceramic substrate and ceramic substrates |
KR101856107B1 (ko) * | 2015-04-24 | 2018-05-09 | 주식회사 아모센스 | 세라믹 기판 제조 방법 및 이 제조방법으로 제조된 세라믹 기판 |
KR101856106B1 (ko) * | 2015-04-24 | 2018-05-09 | 주식회사 아모센스 | 세라믹 기판 제조 방법 및 이 제조방법으로 제조된 세라믹 기판 |
KR101856109B1 (ko) * | 2015-04-24 | 2018-05-09 | 주식회사 아모센스 | 세라믹 기판 제조 방법 및 이 제조방법으로 제조된 세라믹 기판 |
KR101856108B1 (ko) * | 2015-04-24 | 2018-05-09 | 주식회사 아모센스 | 세라믹 기판 제조 방법 및 이 제조방법으로 제조된 세라믹 기판 |
KR102563421B1 (ko) * | 2016-07-19 | 2023-08-07 | 주식회사 아모센스 | 세라믹 기판 제조 방법 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4017340A (en) * | 1975-08-04 | 1977-04-12 | General Electric Company | Semiconductor element having a polymeric protective coating and glass coating overlay |
WO2003030247A2 (de) * | 2001-09-28 | 2003-04-10 | Siemens Aktiengesellschaft | Verfahren zum kontaktieren elektrischer kontaktflächen eines substrats und vorrichtung aus einem substrat mit elektrischen kontaktflächen |
EP1313146A2 (de) * | 2001-11-08 | 2003-05-21 | Tyco Electronics Corporation | Monolithisch integrierter Schaltkreis mit pin-Diode und Schottky-Diode und Herstellungsverfahren hierfür |
US6881980B1 (en) * | 2004-06-17 | 2005-04-19 | Chunghwa Picture Tubes, Ltd. | Package structure of light emitting diode |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0437067A (ja) * | 1990-05-31 | 1992-02-07 | Canon Inc | 半導体素子用電極及び該電極を有する半導体装置及びその製造方法 |
JP3246929B2 (ja) * | 1991-11-11 | 2002-01-15 | 電気化学工業株式会社 | マトリックス回路基板及び表示板 |
JPH07131075A (ja) * | 1993-10-28 | 1995-05-19 | Kyocera Corp | 画像装置 |
JP3009091B2 (ja) * | 1994-11-15 | 2000-02-14 | 日亜化学工業株式会社 | 青色発光ダイオード |
JP3641122B2 (ja) * | 1997-12-26 | 2005-04-20 | ローム株式会社 | 半導体発光素子、半導体発光モジュール、およびこれらの製造方法 |
US6319757B1 (en) * | 1998-07-08 | 2001-11-20 | Caldus Semiconductor, Inc. | Adhesion and/or encapsulation of silicon carbide-based semiconductor devices on ceramic substrates |
JP4724924B2 (ja) * | 2001-02-08 | 2011-07-13 | ソニー株式会社 | 表示装置の製造方法 |
DE10351397A1 (de) * | 2003-10-31 | 2005-06-16 | Osram Opto Semiconductors Gmbh | Lumineszenzdiodenchip |
DE10353679A1 (de) * | 2003-11-17 | 2005-06-02 | Siemens Ag | Kostengünstige, miniaturisierte Aufbau- und Verbindungstechnik für LEDs und andere optoelektronische Module |
-
2005
- 2005-08-30 DE DE102005041099A patent/DE102005041099A1/de not_active Ceased
-
2006
- 2006-08-30 KR KR1020087003687A patent/KR101295606B1/ko not_active IP Right Cessation
- 2006-08-30 CN CN2006800318234A patent/CN101253623B/zh not_active Expired - Fee Related
- 2006-08-30 WO PCT/DE2006/001513 patent/WO2007025521A2/de active Application Filing
- 2006-08-30 US US11/991,197 patent/US7859005B2/en not_active Expired - Fee Related
- 2006-08-30 EP EP06791327A patent/EP1920462A2/de not_active Withdrawn
- 2006-08-30 JP JP2008528330A patent/JP5215853B2/ja not_active Expired - Fee Related
- 2006-08-30 TW TW095131944A patent/TWI313075B/zh not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4017340A (en) * | 1975-08-04 | 1977-04-12 | General Electric Company | Semiconductor element having a polymeric protective coating and glass coating overlay |
WO2003030247A2 (de) * | 2001-09-28 | 2003-04-10 | Siemens Aktiengesellschaft | Verfahren zum kontaktieren elektrischer kontaktflächen eines substrats und vorrichtung aus einem substrat mit elektrischen kontaktflächen |
EP1313146A2 (de) * | 2001-11-08 | 2003-05-21 | Tyco Electronics Corporation | Monolithisch integrierter Schaltkreis mit pin-Diode und Schottky-Diode und Herstellungsverfahren hierfür |
US6881980B1 (en) * | 2004-06-17 | 2005-04-19 | Chunghwa Picture Tubes, Ltd. | Package structure of light emitting diode |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102007033288A1 (de) * | 2007-07-17 | 2009-01-22 | Siemens Ag | Elektronisches Bauelement und Vorrichtung mit hoher Isolationsfestigkeit sowie Verfahren zu deren Herstellung |
DE102008048423B4 (de) * | 2007-09-24 | 2015-05-28 | Infineon Technologies Ag | Verfahren zum Herstellen eines Integrierten Schaltungsbauelements |
WO2009079978A1 (de) * | 2007-12-20 | 2009-07-02 | Osram Opto Semiconductors Gmbh | Optoelektronisches bauelement |
JP2011507285A (ja) * | 2007-12-20 | 2011-03-03 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | オプトエレクトロニクス素子 |
US8476667B2 (en) | 2007-12-20 | 2013-07-02 | Osram Opto Semiconductors Gmbh | Optoelectronic component |
JP2011507198A (ja) * | 2007-12-21 | 2011-03-03 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | オプトエレクトロニクス部品およびその製造方法 |
US8513682B2 (en) | 2007-12-21 | 2013-08-20 | Osram Opto Semiconductors Gmbh | Optoelectronic component and production method for an optoelectronic component |
WO2011026456A1 (de) * | 2009-09-03 | 2011-03-10 | Osram Opto Semiconductors Gmbh | Optoelektronisches modul aufweisend zumindest einen ersten halbleiterkörper mit einer strahlungsaustrittsseite und einer isolationsschicht und verfahren zu dessen herstellung |
US8847247B2 (en) | 2009-09-03 | 2014-09-30 | Osram Opto Semiconductors Gmbh | Optoelectronic module comprising at least one first semiconductor body having a radiation outlet side and an insulation layer and method for the production thereof |
WO2011032853A1 (de) * | 2009-09-18 | 2011-03-24 | Osram Opto Semiconductors Gmbh | Optoelektronisches modul |
Also Published As
Publication number | Publication date |
---|---|
JP5215853B2 (ja) | 2013-06-19 |
CN101253623A (zh) | 2008-08-27 |
JP2009506558A (ja) | 2009-02-12 |
TW200715621A (en) | 2007-04-16 |
CN101253623B (zh) | 2010-05-19 |
KR20080039904A (ko) | 2008-05-07 |
WO2007025521A3 (de) | 2007-05-03 |
EP1920462A2 (de) | 2008-05-14 |
US7859005B2 (en) | 2010-12-28 |
KR101295606B1 (ko) | 2013-08-12 |
DE102005041099A1 (de) | 2007-03-29 |
US20090278157A1 (en) | 2009-11-12 |
TWI313075B (en) | 2009-08-01 |
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