WO2007024656A3 - Architecture and method for testing of an integrated circuit device - Google Patents

Architecture and method for testing of an integrated circuit device Download PDF

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Publication number
WO2007024656A3
WO2007024656A3 PCT/US2006/032268 US2006032268W WO2007024656A3 WO 2007024656 A3 WO2007024656 A3 WO 2007024656A3 US 2006032268 W US2006032268 W US 2006032268W WO 2007024656 A3 WO2007024656 A3 WO 2007024656A3
Authority
WO
WIPO (PCT)
Prior art keywords
testing
integrated circuit
test
architecture
circuit device
Prior art date
Application number
PCT/US2006/032268
Other languages
French (fr)
Other versions
WO2007024656A2 (en
WO2007024656A9 (en
Inventor
Adrian E Ong
Original Assignee
Inapac Technology Inc
Adrian E Ong
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inapac Technology Inc, Adrian E Ong filed Critical Inapac Technology Inc
Publication of WO2007024656A2 publication Critical patent/WO2007024656A2/en
Publication of WO2007024656A9 publication Critical patent/WO2007024656A9/en
Publication of WO2007024656A3 publication Critical patent/WO2007024656A3/en

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31723—Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318511—Wafer Test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]

Abstract

In one embodiment, the present invention provides a platform of hardware and/or software that enables the complete access and reliable testing of multiple integrated circuit (IC) devices (20, 30) within a package. This platform may include a testing component (10) (e.g., test circuits, test pads, shared pads, etc.), one or more probe cards and related hardware, wafer probe program, load board and related hardware of external test equipment, and software and routines for final test programs.
PCT/US2006/032268 2005-08-19 2006-08-18 Architecture and method for testing of an integrated circuit device WO2007024656A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/207,518 2005-08-19
US11/207,518 US7444575B2 (en) 2000-09-21 2005-08-19 Architecture and method for testing of an integrated circuit device

Publications (3)

Publication Number Publication Date
WO2007024656A2 WO2007024656A2 (en) 2007-03-01
WO2007024656A9 WO2007024656A9 (en) 2007-04-12
WO2007024656A3 true WO2007024656A3 (en) 2009-05-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/032268 WO2007024656A2 (en) 2005-08-19 2006-08-18 Architecture and method for testing of an integrated circuit device

Country Status (3)

Country Link
US (1) US7444575B2 (en)
TW (1) TW200724950A (en)
WO (1) WO2007024656A2 (en)

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US20050289428A1 (en) 2005-12-29

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