WO2007002324A2 - An integrated memory core and memory interface circuit - Google Patents

An integrated memory core and memory interface circuit Download PDF

Info

Publication number
WO2007002324A2
WO2007002324A2 PCT/US2006/024360 US2006024360W WO2007002324A2 WO 2007002324 A2 WO2007002324 A2 WO 2007002324A2 US 2006024360 W US2006024360 W US 2006024360W WO 2007002324 A2 WO2007002324 A2 WO 2007002324A2
Authority
WO
WIPO (PCT)
Prior art keywords
memory
integrated circuit
interface
memory device
set forth
Prior art date
Application number
PCT/US2006/024360
Other languages
French (fr)
Other versions
WO2007002324A3 (en
Inventor
Suresh N. Rajan
Original Assignee
Metaram, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Metaram, Inc. filed Critical Metaram, Inc.
Priority to KR1020147005128A priority Critical patent/KR101463375B1/en
Priority to KR1020087001812A priority patent/KR101318116B1/en
Priority to GB0800734A priority patent/GB2441726B/en
Priority to DE112006001810T priority patent/DE112006001810T5/en
Priority to KR1020137004006A priority patent/KR101377305B1/en
Priority to JP2008518401A priority patent/JP2008544437A/en
Publication of WO2007002324A2 publication Critical patent/WO2007002324A2/en
Publication of WO2007002324A3 publication Critical patent/WO2007002324A3/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1694Configuration of memory controller to different memory types
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076Timing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4093Input/output [I/O] data interface arrangements, e.g. data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4096Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24Accessing extra cells, e.g. dummy cells or redundant cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012Marginal testing, e.g. race, voltage or current testing of timing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045Read-write mode select circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/12Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10Aspects relating to interfaces of memory device to external buses
    • G11C2207/107Serial-parallel conversion of data or prefetch
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22Control and timing of internal memory operations
    • G11C2207/2254Calibration

Definitions

  • the present invention is directed toward the field of building custom memory systems cost-effectively for a wide range of markets.
  • DRAM Dynamic Random Access Memory
  • Mb/$ Cost-effectiveness
  • Specialty memory is typically memory that is not used by the PC main memory but is memory that is designed for one or more niche markets.
  • the PC graphics market uses
  • GDDR Graphics Dual Data Rate DRAM.
  • FCRAM Fast Cycle RAM
  • RLDRAM Reduced Latency
  • DRAM DRAM
  • Legacy memory is typically memory that was used in the past but is not used in that particular market segment now.
  • SDRAM Synchronous DRAM
  • PC main memory ⁇ 1997 to -2001 but is no longer used today for PC main memory. Instead, most cellular phones and handheld (or mobile) devices use SDRAM today.
  • a memory device comprises a first integrated circuit die.
  • the first integrated circuit die comprises a memory core, with a plurality of memory cells, and a first interface circuit for accessing the memory cells of the memory core.
  • the first interface circuit provides reading, writing, activating, pre-charging and refreshing operations to the memory cells.
  • a second integrated circuit die electrically coupled to the first integrated circuit die, comprises a second interface circuit for accessing the memory core via the first interface circuit and for interfacing the memory core to an external circuit.
  • the second interface circuit may comprise a synchronous interface to an external bus.
  • the memory device has two separate die: one for the memory core and a second as an external interface.
  • the memory core includes a plurality of memory banks for partitioning the memory cells.
  • a multiplexer coupled to the memory banks, selects data from one or more of the memory banks.
  • the multiplexer is located generally near an edge of the first integrated circuit die.
  • the first integrated circuit die further comprises data input/output ("I/O") pads and a plurality of bond wires that couple the multiplexer to the I/O pads.
  • the I/O pads are located essentially adjacent to the multiplexer near an edge of the first integrated circuit die so as to minimize distance of the bond wires.
  • a distributed-bank architecture is used to configure the memory device.
  • the memory cells are partitioned into memory banks.
  • the memory banks comprise a plurality of sub-arrays across the physical sections of the memory core such that a physical section of the memory cells comprises a plurality of sub-arrays associated with different memory banks.
  • a multiplexer selects a memory bank from a physical section.
  • the first and second integrated circuit dies are housed in separate packages. In other embodiments, the first and second integrated circuit dies are housed in the same package.
  • FIG 1 is a block diagram illustrating a conventional DRAM chip.
  • FIG. 2 illustrates a typical organization of a 4-bank modern SDRAM.
  • FIG. 3 is a block diagram illustrating one embodiment of banks arranged in sub- arrays.
  • FIG. 4 illustrates a block diagram of an interface and multiple banks in a DRAM.
  • FIG. 5 is a block diagram illustrating a DRAM chip with an interface removed.
  • FIG. 6 illustrates one embodiment for a center bonded DRAM core chip.
  • FIG. 7 illustrates one embodiment for an edge bonded DRAM core chip.
  • FIG. 8 illustrates one embodiment for a concentrated-bank architecture.
  • FIG. 9 illustrates one embodiment for a distributed-bank architecture.
  • FIG. 10 illustrates one embodiment for a quadrant in a distributed-bank architecture DRAM core chip.
  • FIG. 11 is block diagram illustrating one embodiment of a distributed-bank architecture universal DRAM core chip.
  • FIG 12 is a block diagram illustrating a distributed-bank architecture DRAM core chip configured to support DDR2 speeds.
  • FIG. 13 is a block diagram illustrating a distributed-bank architecture DRAM core chip configured to support DDR speeds and external bus widths from 17 to 32 bits.
  • FIG. 14 is a block diagram illustrating a distributed-bank architecture DRAM core chip configured to support DDR speeds and external bus widths from 9 to 16 bits.
  • FIG. 15 is a block diagram illustrating a distributed-bank architecture DRAM core chip configured to support DDR speeds and external bus widths from 1 to 8 bits.
  • FIG. 16 illustrates one embodiment for a portion of a DRAM core chip that includes a decoder for selecting a mode of operation.
  • FIG 17a is a block diagram illustrating the relationship between the internal data bus rate and the external data bus rate for 4n pre-fetching.
  • FIG. 17b is a block diagram illustrating the relationship between the internal data bus rate and the external data bus rate for burst mode with a length of 4n.
  • FIG. 18 is a block diagram illustrating an example multi-chip memory implementation.
  • FIG. 19 illustrates techniques for stacking two DRAM core chips behind a single interface chip.
  • xl6 denotes the external data width
  • xl6 256Mb DDR SDRAM xl6 256Mb DDR2 SDRAM
  • control logic block which implements the protocol, among other functions
  • width of the data that is accessed per column address and in the data I/O section.
  • the core timing parameters are typically specified in absolute units of time (seconds) rather than in terms of clock periods.
  • the Micron 256Mb DDR2 SDRAM data sheet lists the following core timing parameters:
  • Micron 256Mb DDR SDRAM data sheet identifies the following timing specifications:
  • the Micron 256Mb SDRAM data sheet discloses the following specifications:
  • One embodiment of the invention comprises a multi- chip implementation, wherein one or more DRAM core chips are attached to an interface chip.
  • the interface chip sits between the host electronic system and the DRAM core chips, hi other words, the interface chip can be thought of as a "wrapper" that surrounds the DRAM core chips.
  • the partitioning of the conventional DRAM into DRAM core chip and interface chip should preferably be done is such a way that that the functions and circuits that are relatively constant across many different architectures are retained in the DRAM core chip while the functions and circuits that vary between the different architectures are moved to the interface chip.
  • the DRAM core chip can be designed to be suitable for a large number of markets (i.e. a "universal core").
  • the interface chip can now be designed to meet the exact needs of a market, and even the exact needs of individual customers in that market.
  • the proposed solution enables the design of an interface chip to meet the exact needs of Nokia for the cell phone market and another interface chip to meet the exact needs of Motorola for the cell phone market.
  • the DRAM core chip In order to accommodate the needs of the different markets, the DRAM core chip must be capable of operating across a wide range of frequencies, be capable of supporting high data rates, and must be low cost.
  • the DRAM core chip is asynchronous, wide, and operates at its natural speed.
  • the natural speed is between 5ns to 10ns per column access, which is equivalent to lOOMHz to 200MHz synchronous operation. That is, a modern DRAM core can keep up with an external memory bus or interface that runs at a speed from lOOMHz to 200MHz.
  • n bits can be fetched from the DRAM core once every clock cycle. In fact, this is how SDRAMs operate.
  • Newer synchronous DRAMs run at higher clock speeds.
  • JEDEC defines the DDR SDRAM specification with external data rates of 200MHz 5 266MHz, 333MHz, and 400MHz.
  • An even newer specification called DDR2 SDRAM has been defined with external data rates of 400MHz, 533MHz, 667MHz, and 800MHz.
  • Effort is currently underway in JEDEC to define a DDR3 SDRAM specification that spans data rates from 800MHz to 1600MHz.
  • GDDR, GDDR2, and GDDR3 SDRAMs typically run faster than the DDR, DDR2, and DDR3 SDRAMs.
  • the DRAM industry has adopted a technique called "pre-fetching."
  • FIG. 1 is a block diagram illustrating a conventional DRAM chip.
  • a DRAM chip 100 comprises a DRAM core 110, Internal Data Bus 120, DRAM interface 130 and External data bus 140.
  • TABLE 4 shows the concept of pre-fetching for a DRAM chip.
  • the universal DRAM core chip must be sufficiently wide enough to support the data rates required by many different markets. Obviously there is a limit to how wide the universal DRAM core chip can be before it starts to negatively impact the cost of the chip, hi general, if the width of the DRAM core chip is so large so as to make either the core chip or the interface chip pad limited (especially the core chip), the cost of this solution would be very high.
  • Modern DRAMs also feature multiple banks.
  • a bank is a section of the DRAM core that can be accessed independently.
  • the DRAM core is broken up into banks that can be active simultaneously. Within each bank, only one row can be open at any given time.
  • Most DRAMs up to 512Mb densities are organized into 4 banks.
  • IGb (and possibly, up to 4Gb) DRAMs are organized into 8 banks but only 4 banks can be activated within a specific time window. This is dictated by power and thermal considerations. So, the universal DRAM core chip must be capable of supporting multiple banks.
  • a xl6 256Mb SDRAM may have 4 banks, each of which is 64Mb.
  • Each bank can be conceptualized as consisting of 16 sub-arrays, each sub-array being a 8192 x 512 matrix of memory cells. That is, each sub-array has 8192 or 8k rows and 512 columns. So, when a bank is accessed, a particular row is accessed (activated) in each of the 16 sub-arrays in the bank. The row is determined by the row address. After the 16 rows are activated, a particular bit in each row is selected. The bit is specified by the column address. So, on each access to a bank, 16 bits are accessed.
  • FIG. 2 illustrates a typical organization of a 4-bank modem SDRAM.
  • the memory cells are arranged into four banks: bank 0 (220), bank 1 (210), bank 2 (230) and bank 3 (240).
  • Each bank has associated word line drivers (275, 280, 285 and 290) and sense amplifiers (255, 260, 265 and 270).
  • the banks are selected through use of MUX 250.
  • the banks are organized in sub-arrays.
  • FIG. 3 is a block diagram illustrating one embodiment of banks arranged in sub-arrays. For this embodiment, each bank has 16 sub-arrays (each sub-array being 8K x 512) because the DRAM is organized as a xl6 memory.
  • the xl6 256Mb DDR SDRAM is organized similar to the xl6 256Mb SDRAM with some changes to the memory core. The more important changes to the core organization are: Each bank has 32 sub-arrays; and
  • the reason for having 32 sub-arrays is that DDR SDRAM memory uses a pre-fetching of 2n. Since this is a xl6 DDR memory, 32 bits must be accessed from each bank for a read or write operation.
  • pre-fetching can be done in a number of ways.
  • a memory array that is organized as a P x Q matrix that needs to support 2n pre-fetching.
  • One approach is to divide the P x Q array into two arrays (i.e. two P x Q/2 arrays) and access both arrays in parallel, so that we get 2 bits per column address.
  • Another approach is to not split the array but modify the column decoder so that 2 bits are selected for each column address (in other words, the least significant bit of the column address is not used).
  • the xl ⁇ 256Mb DDR2 SDRAM is organized similar to the xl6 256Mb SDRAM (and the xl6 256Mb DDR SDRAM). The following identify some of the changes to the memory core:
  • a MUX multiplexer / de-multiplexer
  • This MUX is typically in the middle of the DRAM chip.
  • FIG. 4 illustrates a block diagram of an interface and multiple banks in a DRAM.
  • bank 0 410
  • bank 1 420
  • bank 2 430
  • bank 3 440
  • DDR SDRAM 2n
  • DDR2 SDRAM 4n
  • DDR3 SDRAM proposed
  • m 8n
  • the data MUX is typically part of the interface.
  • FIG. 5 is a block diagram illustrating a DRAM chip with an interface removed.
  • bank 0 (510), bank 1 (520), bank 2 (530) and bank 3 (540) are coupled to VO pads 550, 560, 570 and 580, respectively. If we look at only the data pins and ignored the address, command, power and ground pins, we can see that the number of data signals that have to go off-chip between the DRAM core chip and the interface chip is 4m.
  • some part or all of the multiplexing of the data I/O from the banks is done in the core chip itself.
  • FIG. 6 illustrates one embodiment for a center bonded DRAM core chip.
  • integrated circuit 600 includes bank 0 (610), bank 1 (620), bank 2 (630) and bank 3 (640) coupled to MUX 650.
  • MUX 650 is connected to substrate bonding pads 670 via bond wires 680 through I/O pads 660.
  • bond wires 680 that connect I/O pads 660 on the DRAM core die to the substrate bonding pads 670 become quite long. Long bond wires have significant inductance and limit the speed at which the memory chip can operate.
  • FIG. 7 illustrates one embodiment for an edge bonded DRAM core chip.
  • integrated circuit 700 includes bank 0 (710), bank 1 (720), bank 2 (730) and bank 3 (740). I/O pads
  • bond wires 780 located on the silicon die 705, are connected to the substrate bonding pads 760 via bond wires 780.
  • the number of data I/O pads will be equal to 4m as illustrated previously.
  • the other option is to route the data bits from each bank to a centrally located MUX (as shown in FIG. 6) and then route the signals from the other side of the MUX to the periphery of the die.
  • this means that the data signals will have to traverse the die twice - once from the bank to the central MUX and once from the central MUX to the periphery.
  • This increases routing complexity may possibly require an extra metal layer on the die (higher cost), and adds to the latency of the memory core.
  • an inventive "Distributed-Bank" architecture is used.
  • a bank is distributed (or spread) across all 4 quadrants instead of concentrating a bank in only one quadrant.
  • data MUXs located in all 4 quadrants, select the appropriate bank, and the data signals corresponding to the selected bank can be easily routed to the periphery of the chip.
  • FIG. 8 illustrates one embodiment for a concentrated-bank architecture.
  • a xl6, 4-bank, 256Mb DDR2 SDRAM core is used.
  • any type of DRAM, with different external data widths, different number of banks, different density, and different amount of pre-fetching may be used without deviating from the spirit or scope of the invention.
  • each bank (810, 820, 830 and 840) in a xl6, 4-bank, 256Mb DDR2 SDRAM consists of 64 sub-arrays, with each sub-array organized as a 8192 x 128 array of memory cells.
  • FIG. 9 illustrates one embodiment for a distributed-bank architecture.
  • the DRAM core chip is divided into four quadrants (910, 920, 930 and 940). Each quadrant includes a portion of a bank.
  • FIG. 10 illustrates one embodiment for a quadrant in a distributed-bank architecture DRAM core chip.
  • local data MUXs are located in each quadrant to select one of the four banks.
  • FIG. 11 is block diagram illustrating one embodiment of a distributed-bank architecture universal DRAM core chip.
  • the banks of DRAM cells are distributed among quadrant 1110, 1120, 1130 and 1140.
  • An address decoder 1150 located in the center of the chip, controls word line drivers 1155, 1164, 1170 and 1176 in quadrants 1110, 1120, 1130 and 1140 respectively.
  • the data from the bank sub-arrays are output to sense amplifiers (1157, 1166, 1172 and 1178) and input to the respective bank select MUXs (1160, 1168, 1174 and 1180).
  • the data is then routed to data I/O pads 1162 located in the proximity for each of the quadrants.
  • the interface chip may be designed or configured to act similar to a xl6 DDR2
  • SDRAM Secure Digital RAM
  • x8 DDR2 SDRAM x4 DDR2 SDRAM
  • x2 DDR2 SDRAM xl DDR2
  • the interface chip may be designed to support any data width between xl and xl6 when operating in a 4n pre-fetch mode.
  • the distributed-bank architecture is flexible enough to support protocols like SDRAM, DDR SDRAM, DDR2 SDRAM, and DDR3 SDRAM.
  • the DRAM core chip shown in FIG. 11 may be configured or used as shown in FIG. 12 to support DDR2 speeds.
  • FIG 12 is a block diagram illustrating a distributed-bank architecture DRAM core chip configured to support DDR2 speeds.
  • MUX 1210 selects 64 bits of data for one of the banks (1220, 1230, 1240 and 1250).
  • MUX 1210 represents the data MUXs located in all four quadrants on the DRAM core chip.
  • the DRAM core chip shown in FIG. 11 may also be configured or used as shown in FIG 13 to support DDR SDRAM speeds when it is operated in a 2n pre-fetch mode.
  • FIG. 13 is a block diagram illustrating a distributed-bank architecture DRAM core chip configured to support DDR speeds and external bus widths from 17 to 32 bits.
  • MUX 1310 selects 64 bits of data for one of the banks (1320, 1330, 1340 and 1350).
  • the mode of operation shown in FIG. 13 may be used with the appropriate interface chip to support external data widths between (and inclusive) of 17 and 32 in a 2n pre-fetch mode.
  • FIG. 14 is a block diagram illustrating a distributed-bank architecture DRAM core chip configured to support DDR speeds and external bus widths from 9 to 16 bits.
  • MUX 1410 selects 32 bits of data for one of the banks (1420, 1430, 1440 and 1450).
  • FIG. 15 is a block diagram illustrating a distributed-bank architecture DRAM core chip configured to support DDR speeds and external bus widths from 1 to 8 bits.
  • MUX 1510 selects 16 bits of data for one of the banks (1520, 1530, 1540 and 1550).
  • the internal data bus width (the width of the bus between the DRAM core chip and the interface chip) may be configured to match the amount of pre-fetching required (which is determined by the external data rate) and the width of the external data bus.
  • the external data bus is the bus from the interface chip to the ASIC or memory controller.
  • the DRAM core chip as shown in FIG. 11 may be configured to support the following modes and requirements shown in TABLE 6.
  • the proposed DDR3 SDRAM is an example of an 8n pre-fetch protocol; DDR2 SDRAM is an example of a 4n pre-fetch protocol; DDR SDRAM is an example of a 2n pre-fetch protocol; and SDRAM is an example of a In pre-fetch protocol (i.e. no pre-fetching needed).
  • DDR3 SDRAM is an example of an 8n pre-fetch protocol
  • DDR2 SDRAM is an example of a 4n pre-fetch protocol
  • DDR SDRAM is an example of a 2n pre-fetch protocol
  • SDRAM is an example of a In pre-fetch protocol (i.e. no pre-fetching needed).
  • 3 modes of operation may be defined and a 2-bit binary code may be assigned to represent them as shown in TABLE 7.
  • Mode[l:0] may be inputs to the DRAM core chip so that the internal data bus width is selected through external means.
  • the Mode[l:0] inputs to the core chip may be selected by means of fuses on the core chip or on the interface chip, by means of pull-up or pull-down resistors in the package of either chip (or in the common package) or on the printed circuit board, or may be driven by a register on the interface chip, or may be part of the address input to the core chip.
  • FIG. 16 illustrates one embodiment for a portion of a DRAM core chip that includes a decoder for selecting a mode of operation.
  • the decoder 1610 in the core chip is aware of the Mode[l :0] inputs as shown in FIG. 16.
  • a universal DRAM core chip such as the embodiment shown in FIG. 11, may be configured to support a wide variety of data speeds and widths.
  • the core chip shown in FIG. 11 may support data rates up to 8*f MB/s, where f is the maximum clock rate (in MHz) at which the DRAM core can run in sync with the external data bus without using pre-fetching (i.e. using a pre- fetching of In).
  • f is typically between 100MHz and 200MHz. So, the DRAM core chip shown in FIG. 11 supports maximum data rates between 800MB/s and 1600MB/s (1.6GB/s).
  • Semiconductor fabrication process is inherently statistical in nature. That is, if we fabricate a statistically significant number of identical chips, some of the chips will only be capable of operating below the target speed, some of the chip will be capable of operating at the target speed, and some of the chips will be capable of operating above the target speed. These are known in the industry as slow, typical, and fast parts respectively. Usually, the fast parts are sold at a price premium over the other parts while the slow parts are sold at lower prices compared to the typical parts.
  • Attach interface chips designed for low power markets e.g. an SDRAM-like interface for the cell phone market
  • Attach interface chips designed for the high performance/speed markets e.g. a GDDR3-like interface for the game console market
  • Attach interface chips designed for markets sensitive to both power and performance e.g. a DDR-like interface for the server market
  • Speed binning of memory chips is typically done after it is packaged. Note that it is possible to do a simple speed sort of the memory chips at the wafer level itself. In order to do a speed sort or speed bin, we need to use ATE (automatic test equipment), also known as tester.
  • ATE automated test equipment
  • the DRAM core chips When we speed bin the DRAM core chips, we need to measure the time required for basic operations like Read, Write, Activate (open one or more pages), Precharge (close one or more pages), and Refresh.
  • the DRAM core chips defined by the present invention, are fully functional asynchronous DRAM chips capable of stand-alone operation. In other words, the DRAM core chips contain all the necessary circuits and capabilities needed to access the internal array used to store the data.
  • Memory makers, especially DRAM manufacturers, build redundancy into the memory core. For example, if the memory array is to be organized as P x Q (P rows and Q columns), the actual array is designed as (P + i) x (Q + j), where i and j are small compared to P and Q respectively. This allows the memory makers to replace up to i defective rows in the main array with the redundant rows, and up to j defective columns in the main array with the redundant columns. With the help of the redundant rows and columns, memory makers can increase the yield (i.e. the percentage of fully functional chips) to - 90%. Ih a typical DRAM manufacturing flow, the individual dies on a wafer are tested at low speed and the partially functional dies (i.e. those with some defective rows and/or columns) are marked. The defective rows and/or columns on these marked dies are replaced with the redundant rows and/or columns respectively.
  • Interface chips that are designed for high performance markets may be attached to the DRAM core dies that do not have any defective rows and/or columns in the main array.
  • the defective rows and/or columns of memory core dies are not replaced with the redundant rows and/or columns, but are configured to operate the memory core dies as (P / y) x (Q / z), where y and z are preferably powers of 2
  • DRAM core chips may then be attached to interface chips that are designed for high performance markets.
  • DDR2 SDRAM uses 4n pre-fetching. This means that for an n-bit wide external data bus, 4n data bits are accessed from the memory core for every read or write, hi a conventional DRAM (where the memory core and the interface are on the same die), increasing the amount of pre-fetching increases the amount of metal interconnects on the die, which has a modest impact on the cost. In the invention described herein, increasing the amount of pre-fetching may make either the memory core chip or the interface chip or both pad limited. Being pad limited can increase the cost substantially.
  • Burst mode is another technique that can be used to increase the data rate of memory chips, hi burst mode, the memory chip reads or writes multiple data bits per column address.
  • an n-bit wide (external data bus width) memory chip that is configured for a burst mode of 4n will access 4n bits from the memory core for a given column address. So this is quite similar to a 4n pre-fetch except that in burst mode, the same data wires are used.
  • the internal data bus between the memory core and the interface is only n-bits wide. Each line in the internal bus carries 4 data bits that are separated in time.
  • FIG. 17a is a block diagram illustrating the relationship between the internal data bus rate and the external data bus rate for 4n pre-fetching.
  • Memory core 1710 is coupled to memory interface 1720 via internal data bus 1715 at 4n @ f ls Hz data rate.
  • the memory interface 1720 is coupled to external data bus 1725, and under these conditions, the external data bus operates at a n @ 4*f 1? Hz data rate.
  • FIG. 17b is a block diagram illustrating the relationship between the internal data bus rate and the external data bus rate for burst mode with a length of 4n.
  • Memory core 1730 is coupled to memory interface 1750 via internal data bus 1740 at n @ 4*f 2 , Hz data rate.
  • the memory interface 1750 is coupled to external data bus 1760, and for the burst mode of operation, the external data bus operates at a n @ 4*f 2 , Hz data rate.
  • pre-fetching will provide higher external data rates than burst mode.
  • burst mode does not increase the amount of off-chip connections between the core chip and the interface chip. So, in some embodiments, it is preferable to design the DRAM core chip of this invention with burst mode capability.
  • one of the aspects of this invention is the ability to test and speed bin the memory core chips and then attach the appropriate interface chips.
  • Testing and speed binning of the DRAM core chip is usually done on a tester. This requires the core chip to have sufficiently strong output drivers to drive the inputs of the tester, which are usually some distance (several inches) from the outputs of the core chip. However, in the normal mode of operation, the inputs of the interface chip will be much closer ( ⁇ 1") to the outputs of the core chip. So 3 it is not necessary to have strong output drivers in the core chip in the normal mode of operation. In order to satisfy both requirements, in some embodiments the DRAM core chip preferably has output drivers whose strength or drive capability is adjustable.
  • the core chip may have, by default, normal strength output drivers that are capable of driving signals across some distance to the inputs of the tester. However, when an interface chip is attached to the core chip, a signal from the interface chip decreases the drive strength of the core chip's output drivers.
  • the output drivers of interface chip that interface with the DRAM core chip have similar adjustable drive strength capability. This allows testing of the interface chips separately prior to attaching them to the core chips.
  • the adjustable drive strength drivers are not necessarily required on the interface chip on the pins that interface to the electronic host system. However, it is preferable to have the adjustable strength capability on these drivers as well so that the drive strength can be tailored to the requirements of the system or external world.
  • the strength of the output drivers on the interface chip that communicate with the core chip are preferably controlled by a signal from the core chip.
  • FIG. 18 is a block diagram illustrating an example multi-chip memory implementation.
  • the solution includes a DRAM core chip 1810 and an interface chip 1820.
  • the main characteristics of the DRAM core chip of this invention are:
  • Asynchronous or synchronous DRAM that is capable of stand-alone operation
  • a plurality of DRAM core chips may be coupled together with one or more interface chips;
  • a plurality of interface chips may be coupled together with one or more DRAM core chips;
  • the interface on the DRAM core chip may include a custom and/or industry standard interface; Has address inputs (bank address, row address, column address - row and column address can be on separate inputs or multiplexed on same pins);
  • Has control inputs that determine mode of operation - examples are inputs that determine the width of the internal data bus (bus between the memory core chip and interface chip) aid inputs that determine the strength of the output drivers;
  • Internal data bus width external data bus width (bus from interface chip to memory controller or ASIC);
  • the main characteristics of the interface chip of this invention are:
  • Interface chip implements an industry standard protocol like DDR SDRAM,
  • Interface chip implements an industry standard protocol with custom extensions (e.g. GDDR2 SDRAM with extensions as specified by mutual agreement with one or more customers);
  • Interface chip implements a fully custom protocol as specified by one or more customers or a fully custom protocol developed in-house;
  • Interface chip operates as a transformer to convert protocols from the external interface to the interface of the DRAM core chip (e.g., synchronous to asynchronous and asynchronous to synchronous);
  • Interface chip determines the signaling used by the external interface; For example, single ended, pseudo-differential, fully differential;
  • push-pull outputs open drain/collector outputs
  • Example special error detection and error correction capabilities, as well as other types of redundancy capabilities and functions.
  • the DRAM core chip and the interface chip of this invention may be attached together in a number of different ways:
  • One or more DRAM core chip dies and one or more interface chip dies may be electrically connected to each other and the whole combination be put into a single package (e.g., a single DRAM core chip die with a single interface chip die, multiple
  • the core chip die may be put in a separate package, and then the interface chip die may then be electrically attached to the package containing the core chip die;
  • the interface chip die may be put in a separate package, and then the core chip die may then be electrically attached to the package containing the interface chip die;
  • the core chip die can be put in a separate package; the interface chip die may be put in a separate package; and the two packages can be electrically attached to each other; Multiple DRAM core chip dies may be put in a separate package; the interface chip die may be put in a separate package; and the two packages can be electrically attached to each other;
  • a DRAM core chip die may be put in a separate package; multiple interface chip dies may be put in a separate package; and the two packages can be electrically attached to each other;
  • the DRAM core chip die and the interface chip die may be electrically attached in any way without deviating from the spirit or scope of the invention.
  • One aspect of this invention is that a multi-chip DRAM that is built according to this invention, might have higher cost than a traditional DRAM, especially if the DRAM core chip die and the interface chip die were packaged separately and then attached to each other. This is due to the cost associated with the extra package.
  • One way to ameliorate this is to put multiple DRAM core chip dies in a single package. For the purpose of this discussion, we shall consider putting two DRAM core chip dies in a single package, each die being a 256Mb density device.
  • a typical DRAM manufacturing process might have the following sequences after the wafer has been fully processed:
  • DRAM dies on a wafer are tested at low speed and dies with defective rows and/or columns are marked;
  • the defective rows and/or columns are replaced with redundant rows and/or columns; Wafer is diced into individual dies, which are then packaged;
  • Packaged parts are tested for functionality - parts damaged by the packaging process are eliminated;
  • Tested packaged parts undergo long term burn in to eliminate infant mortality parts; and Burnt in parts are optionally tested again for functionality and shipped.
  • Bin A both the DRAM core chip dies are functional, so the total capacity is 512Mb
  • Bin B only one of the DRAM core chip dies is functional, so the total capacity is 256Mb
  • Bin C neither of the DRAM core chip dies is functional, so the total capacity is
  • the bin C parts should be discarded.
  • the bin B parts for those markets and/or customers who require only 256Mb devices.
  • a handheld device manufacturer might require only a 256Mb DRAM. So, the bin B parts can be attached to the interface chips designed for this manufacturer.
  • Other markets and/or manufacturers might require 512Mb devices.
  • a network router manufacturer might need 512Mb DRAMs. So, we can use bin A parts for this manufacturer by attaching the appropriate interface chips to the bin A parts. This concept can be extended to cover more than two DRAM core chip dies in a single package as well as DRAM core chip dies of all densities.
  • some embodiments cover the idea of attaching multiple DRAM core chips to a single interface chip.
  • the core chips may be attached to the interface chip in a number of different ways. Some of these ways are described below and in FIG. 19. Again, for the purpose of illustration, we shall assume that two 4-bank 256Mb DRAM core chips (FIG. 11) are attached to the interface chip. Each of the core chips has a 64-bit wide data bus designed to connect to the interface chip. Note that the idea explained below can be applied to DRAM core chips with different number of banks, density, data bus width, etc.
  • the row addresses are used to select the DRAM core chip.
  • bank addresses are used to select DRAM core chips.
  • column addresses are used to select the DRAM core chip.
  • the two DRAM core chips are attached to the interface chip such that only one of the core chips is accessible at any given time. That is, the two core chips look to the electronic host system as a single 512Mb DRAM with 4 banks. This implies that the interface chip will use the row address to select one or the other core chip.
  • the two DRAM core chips are attached to the interface such that both of the core chips are accessible at any given time, and that the two chips look to the external world electronic host system as a single 512Mb DRAM with 8 banks. This implies that the interface chip will use the bank address to select one or the other core chip.
  • the two DRAM core chips are attached to the interface chip such that both of the core chips are accessible at any given time, and that the two chips look to the electronic host system as a single 512Mb DRAM with 4 banks.
  • the interface chip uses the column address to select one or the other core chip. Note that in other embodiments an interface chip always accesses both the core chips in parallel, so that the data bus between the core chips and the interface chip becomes 128-bits wide. For this embodiment, the interface chip doubles the external data rate. In other words, the amount of pre-fetching has been doubled.
  • the multi-chip solution is configured such that the attachment of the DRAM core chips to the interface chip is programmable.
  • the customer may choose between one of the three methods listed above to attach two A- bank, 64-bit wide, 256Mb DRAM core chips to an interface chip by programmable means. These means include using fuses on the interface chip or the core chips, pull-up or pull-down resistors on the package substrates or printed circuit board, or by means of a register on the interface chip or core chips.
  • any way of attaching the DRAM core chips to the interface chip may be accomplished without deviating from the spirit or scope of the invention.
  • Other embodiments of the invention include building redundant memory systems by attaching multiple DRAM core chips to an interface chip. For example, when more than one core chip is attached to an interface chip, redundancy is added by several means including:
  • the interface chip can read the multiple copies of the data from the different core chips and select the correct copy and transmit it to the memory controller.
  • the correct copy can be determined by means like majority voting, and/or by the use of parity or ECC bits; Using (n + m) bits to store n data bits.
  • Another aspect of this invention is placing memory core chips of different types behind a common interface chip.
  • DRAM Dynamic Random Access Memory
  • SRAM Static Random Access Memory
  • Flash Flash
  • MCP Multi-Chip Package
  • Another aspect of this invention is placing a large and slow memory as well as a smaller and faster memory behind a common interface chip and using the faster memory as a cache for the slower memory.
  • an SRAM chip might be used as the cache for a DRAM core chip or a DRAM core chip can be used as the cache for a Flash chip.
  • the cache management logic may be built into the interface chip so that the cache is transparent to the memory controller. Alternately, the cache may be made visible to the memory controller and managed by the memory controller. Let us consider the case of an interface chip that has been designed to interface to one or more DRAM core chips and an SRAM chip.
  • the SRAM chip can be used to cache the rows in the DRAM core chips that were recently opened.
  • the SRAM may be used to cache the entire contents of the recently opened rows in the DRAM or cache part of the contents of the recently opened rows in the DRAM.
  • the properties of the cache may be determined by programming certain registers in the interface chip. By storing data that has a high likelihood of being accessed in the near future, system performance is improved.
  • a cache also allows the interface chip to do speculative pre-fetching of data from the DRAM core chip (and storing it in the SRAM cache chip), which again improves system performance.
  • the interface chip may operate with SRAM chips (that are used as caches) of different densities. This allows the same interface chip to be used across several different segments within a market.
  • a DRAM / SRAM combination memory device may includes a common interface where the DRAM capacity is 512Mb and the SRAM capacity ranges from 0 to 32Mb.
  • the techniques of the present invention are not just applicable to DRAM.
  • the DRAM core chip need not necessarily be a trench-capacitor or stacked-capacitor device.
  • the present invention is applicable to a variety of memory technologies like MRAM (Magnetic RAM), FRAM (Ferro-electric RAM) 3 Ovonics memory, molecular memory (e.g. memory technology developed by ZettaCore), carbon nanotube memory (e.g. memory technology developed by Nantero Inc.), etc.
  • Another aspect of this invention is that it can be used with DRAM core chips that have different architectures like FCRAM (Fast Cycle RAM), RLDRAM (Reduced Latency DRAM), ESDRAM (Enhanced SDRAM).
  • FCRAM Flust Cycle RAM
  • RLDRAM Reduced Latency DRAM
  • ESDRAM Enhanced SDRAM
  • Some embodiments of invention allow the use of a common memory core across a wide range of markets while varying the interface of the memory core according to the market and customer needs. It also allows the interface to be kept constant while changing the memory core behind the interface to address the needs of the different segments within a market.

Abstract

A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die.

Description

AN INTEGRATED MEMORY CORE AND MEMORY INTERFACE CIRCUIT Related Applications:
This patent application claims the benefit to United States Provisional Patent Application entitled "Methods and Apparatus for Integrating Multi-Chip Memory Devices," Serial number 60/693,631, filed on June 24, 2005.
BACKGROUND OF THE INVENTION Field of the Invention:
The present invention is directed toward the field of building custom memory systems cost-effectively for a wide range of markets. Art Background:
Dynamic Random Access Memory (DRAM) is the most popular type of volatile memory and is widely used in a number of different markets. The popularity of DRAMs is mostly due to their cost-effectiveness (Mb/$). The PC main memory market has traditionally been the largest consumer of DRAMs. However, in recent times, other important markets have adopted DRAMs. A report published by De Dios and Associates showed that in 2004, the PC main memory market consumed only 50% of the total DRAM bits.
Several of the non-PC markets use specialty or legacy memories. Specialty memory is typically memory that is not used by the PC main memory but is memory that is designed for one or more niche markets. For example, the PC graphics market uses
GDDR (Graphics Dual Data Rate) DRAM. Similarly, some segments of the network infrastructure market use FCRAM (Fast Cycle RAM) or RLDRAM (Reduced Latency
DRAM). Legacy memory is typically memory that was used in the past but is not used in that particular market segment now. For example, SDRAM (Synchronous DRAM) was used for PC main memory from ~1997 to -2001 but is no longer used today for PC main memory. Instead, most cellular phones and handheld (or mobile) devices use SDRAM today.
Bringing a new DRAM architecture into the market requires significant investment of time and money. For example, it typically takes 4 years for JEDEC to approve a new DRAM architecture. DRAM makers must then spend hundreds of millions of dollars to productize the new architecture. Unless the investment is amortized over an extremely large number of devices, the cost of the new devices will be high. In addition, the DRAM makers have optimized their manufacturing flow for high volumes. Any deviation from the norm disrupts the flow. This is the reason why specialty and legacy memory typically carry a price premium over memory used by the PC main memory market (which is usually referred to as commodity memory). Given the time and money required to bring a new DRAM architecture into the market, it is obvious that the industry does not have the luxury of being able to define a DRAM architecture that exclusively meets the needs of the smaller markets for DRAMs. For example, it is difficult for the DRAM makers to cost-effectively produce a DRAM that perfectly meets the needs of the cell phone market. Therefore, it is even more difficult for each cell phone maker (e.g. Nokia or Motorola) to design DRAMs tailor made for its phones. So, cell phone designers are forced to choose the DRAM architecture that is least objectionable from their perspective. Hence the selection of SDRAM for cell phones.
This situation will become even worse in the future. Most analyst projections show that not only will DRAM usage expand rapidly into newer markets but also that the DRAM bit consumption growth rate will be higher for non-PC markets. The needs of these markets are quite different from the needs of the PC main memory market. Clearly, there is a need in the market for a way to quickly and cost-effectively build custom memory that is tailor made for a customer's exact needs.
SUMMARY OF THE INVENTION A memory device comprises a first integrated circuit die. The first integrated circuit die comprises a memory core, with a plurality of memory cells, and a first interface circuit for accessing the memory cells of the memory core. For example, the first interface circuit provides reading, writing, activating, pre-charging and refreshing operations to the memory cells. A second integrated circuit die, electrically coupled to the first integrated circuit die, comprises a second interface circuit for accessing the memory core via the first interface circuit and for interfacing the memory core to an external circuit. For example, the second interface circuit may comprise a synchronous interface to an external bus. As such, the memory device has two separate die: one for the memory core and a second as an external interface. In one embodiment, the memory core includes a plurality of memory banks for partitioning the memory cells. A multiplexer, coupled to the memory banks, selects data from one or more of the memory banks. The multiplexer is located generally near an edge of the first integrated circuit die. The first integrated circuit die further comprises data input/output ("I/O") pads and a plurality of bond wires that couple the multiplexer to the I/O pads. The I/O pads are located essentially adjacent to the multiplexer near an edge of the first integrated circuit die so as to minimize distance of the bond wires.
In another embodiment, a distributed-bank architecture is used to configure the memory device. For this embodiment, the memory cells are partitioned into memory banks. The memory banks comprise a plurality of sub-arrays across the physical sections of the memory core such that a physical section of the memory cells comprises a plurality of sub-arrays associated with different memory banks. A multiplexer selects a memory bank from a physical section. In some embodiment, the first and second integrated circuit dies are housed in separate packages. In other embodiments, the first and second integrated circuit dies are housed in the same package.
BRIEF DESCRIPTION OF THE DRAWINGS FIG 1 is a block diagram illustrating a conventional DRAM chip.
FIG. 2 illustrates a typical organization of a 4-bank modern SDRAM. FIG. 3 is a block diagram illustrating one embodiment of banks arranged in sub- arrays.
FIG. 4 illustrates a block diagram of an interface and multiple banks in a DRAM. FIG. 5 is a block diagram illustrating a DRAM chip with an interface removed.
FIG. 6 illustrates one embodiment for a center bonded DRAM core chip. FIG. 7 illustrates one embodiment for an edge bonded DRAM core chip. FIG. 8 illustrates one embodiment for a concentrated-bank architecture. FIG. 9 illustrates one embodiment for a distributed-bank architecture. FIG. 10 illustrates one embodiment for a quadrant in a distributed-bank architecture DRAM core chip.
FIG. 11 is block diagram illustrating one embodiment of a distributed-bank architecture universal DRAM core chip.
FIG 12 is a block diagram illustrating a distributed-bank architecture DRAM core chip configured to support DDR2 speeds.
FIG. 13 is a block diagram illustrating a distributed-bank architecture DRAM core chip configured to support DDR speeds and external bus widths from 17 to 32 bits. FIG. 14 is a block diagram illustrating a distributed-bank architecture DRAM core chip configured to support DDR speeds and external bus widths from 9 to 16 bits.
FIG. 15 is a block diagram illustrating a distributed-bank architecture DRAM core chip configured to support DDR speeds and external bus widths from 1 to 8 bits. FIG. 16 illustrates one embodiment for a portion of a DRAM core chip that includes a decoder for selecting a mode of operation.
FIG 17a is a block diagram illustrating the relationship between the internal data bus rate and the external data bus rate for 4n pre-fetching.
FIG. 17b is a block diagram illustrating the relationship between the internal data bus rate and the external data bus rate for burst mode with a length of 4n.
FIG. 18 is a block diagram illustrating an example multi-chip memory implementation.
FIG. 19 illustrates techniques for stacking two DRAM core chips behind a single interface chip. DETAILED DESCRIPTION
The disclosure of U.S. Provisional Patent Application Ser. No. 60/693,631, entitled "Methods and Apparatus for Integrating Multi-Chip Memory Devices", filed on June 24, 2005, is hereby expressly incorporated herein by reference.
By examining several different DRAM architectures, it is clear that the internal organizations of the DRAMs are quite similar. For example, a xl6 (xl6 denotes the external data width) 256Mb SDRAM, xl6 256Mb DDR SDRAM, and xl6 256Mb DDR2 SDRAM consist of:
Control logic block;
Address input register and decoder; Memory arrays that store the data;
Data selection circuit (I/O gating);
Data read circuit; and
Data write circuit.
It is obvious that most of the blocks are common across all the three architectures. The main differences are in the control logic block (which implements the protocol, among other functions), in the width of the data that is accessed per column address, and in the data I/O section. These are usually considered part of the interface section of the
DRAM while the rest of the circuits (address decoder, memory arrays, and data selection) are considered part of the memory core. The core timing parameters are typically specified in absolute units of time (seconds) rather than in terms of clock periods. For example, the Micron 256Mb DDR2 SDRAM data sheet lists the following core timing parameters:
TABLE l
Figure imgf000006_0001
Similarly, the Micron 256Mb DDR SDRAM data sheet identifies the following timing specifications:
TABLE 2
Figure imgf000006_0002
The Micron 256Mb SDRAM data sheet discloses the following specifications:
TABLE 3
Figure imgf000006_0003
So, even though the protocol and speed of SDRAM, DDR SDRAM, and DDR2 SDRAM are quite different, it is clear that the internal core or array of all these types of DRAMs has similar characteristics. In fact, we can go even further and observe that all synchronous DRAMs are composed of an asynchronous core and an interface that defines the protocol, synchronous operation, speed, and signaling. The memory core typically comprises ~ 90% - 95% of the total die area.
Current practice is to integrate the memory core and the interface onto a common die. The drawback with this approach is that a change in the protocol, speed, or signaling for example requires a re-design of the entire chip. This is usually very expensive and time consuming, and hence the inability to bring specialty or custom DRAMs to the market quickly and cost-effectively. One embodiment of the invention comprises a multi- chip implementation, wherein one or more DRAM core chips are attached to an interface chip. The interface chip sits between the host electronic system and the DRAM core chips, hi other words, the interface chip can be thought of as a "wrapper" that surrounds the DRAM core chips. The partitioning of the conventional DRAM into DRAM core chip and interface chip should preferably be done is such a way that that the functions and circuits that are relatively constant across many different architectures are retained in the DRAM core chip while the functions and circuits that vary between the different architectures are moved to the interface chip.
The DRAM core chip can be designed to be suitable for a large number of markets (i.e. a "universal core"). The interface chip can now be designed to meet the exact needs of a market, and even the exact needs of individual customers in that market. To illustrate, the proposed solution enables the design of an interface chip to meet the exact needs of Nokia for the cell phone market and another interface chip to meet the exact needs of Motorola for the cell phone market.
In order to accommodate the needs of the different markets, the DRAM core chip must be capable of operating across a wide range of frequencies, be capable of supporting high data rates, and must be low cost. In one embodiment, the DRAM core chip is asynchronous, wide, and operates at its natural speed. For the case of modern DRAM cores, the natural speed is between 5ns to 10ns per column access, which is equivalent to lOOMHz to 200MHz synchronous operation. That is, a modern DRAM core can keep up with an external memory bus or interface that runs at a speed from lOOMHz to 200MHz. So, for the case of a synchronous DRAM that operates at lOOMHz to 200MHz and is n- bits wide (1 <n <32 typically), n bits can be fetched from the DRAM core once every clock cycle. In fact, this is how SDRAMs operate.
Newer synchronous DRAMs run at higher clock speeds. JEDEC defines the DDR SDRAM specification with external data rates of 200MHz5 266MHz, 333MHz, and 400MHz. An even newer specification called DDR2 SDRAM has been defined with external data rates of 400MHz, 533MHz, 667MHz, and 800MHz. Effort is currently underway in JEDEC to define a DDR3 SDRAM specification that spans data rates from 800MHz to 1600MHz. GDDR, GDDR2, and GDDR3 SDRAMs typically run faster than the DDR, DDR2, and DDR3 SDRAMs. However, even though the external data rate has been increasing quite rapidly, the speed of the DRAM core has not kept pace. In order to bridge the gap between the external data rate and the internal core speed, the DRAM industry has adopted a technique called "pre-fetching."
Pre-fetching involves accessing more bits than the external data bus width on every column access. To illustrate, an n-bit wide DDR SDRAM accesses 2n bits every column access. This allows the external data bus to run at 200MHz to 400MHz while the internal memory core runs at 100MHz to 200MHz respectively. FIG. 1 is a block diagram illustrating a conventional DRAM chip. A DRAM chip 100 comprises a DRAM core 110, Internal Data Bus 120, DRAM interface 130 and External data bus 140. TABLE 4 shows the concept of pre-fetching for a DRAM chip.
TABLE 4
Figure imgf000008_0001
This implies that the universal DRAM core chip must be sufficiently wide enough to support the data rates required by many different markets. Obviously there is a limit to how wide the universal DRAM core chip can be before it starts to negatively impact the cost of the chip, hi general, if the width of the DRAM core chip is so large so as to make either the core chip or the interface chip pad limited (especially the core chip), the cost of this solution would be very high.
Modern DRAMs also feature multiple banks. A bank is a section of the DRAM core that can be accessed independently. The DRAM core is broken up into banks that can be active simultaneously. Within each bank, only one row can be open at any given time. Most DRAMs up to 512Mb densities are organized into 4 banks. IGb (and possibly, up to 4Gb) DRAMs are organized into 8 banks but only 4 banks can be activated within a specific time window. This is dictated by power and thermal considerations. So, the universal DRAM core chip must be capable of supporting multiple banks. Let us consider the internal organization of a xl6 256Mb SDRAM. A xl6 256Mb SDRAM may have 4 banks, each of which is 64Mb. Each bank can be conceptualized as consisting of 16 sub-arrays, each sub-array being a 8192 x 512 matrix of memory cells. That is, each sub-array has 8192 or 8k rows and 512 columns. So, when a bank is accessed, a particular row is accessed (activated) in each of the 16 sub-arrays in the bank. The row is determined by the row address. After the 16 rows are activated, a particular bit in each row is selected. The bit is specified by the column address. So, on each access to a bank, 16 bits are accessed.
FIG. 2 illustrates a typical organization of a 4-bank modem SDRAM. The memory cells are arranged into four banks: bank 0 (220), bank 1 (210), bank 2 (230) and bank 3 (240). Each bank contains P x Q x 16 cells (e.g., P = 8192 and Q = 512 for a 256 Mb SDRAM). Each bank has associated word line drivers (275, 280, 285 and 290) and sense amplifiers (255, 260, 265 and 270). The banks are selected through use of MUX 250. In one embodiment, the banks are organized in sub-arrays. FIG. 3 is a block diagram illustrating one embodiment of banks arranged in sub-arrays. For this embodiment, each bank has 16 sub-arrays (each sub-array being 8K x 512) because the DRAM is organized as a xl6 memory.
Consider the internal organization of a xl6 256Mb DDR SDRAM. The xl6 256Mb DDR SDRAM is organized similar to the xl6 256Mb SDRAM with some changes to the memory core. The more important changes to the core organization are: Each bank has 32 sub-arrays; and
Each sub-array is now 8192 x 256 matrix (i.e. P = 8192, Q = 256). The reason for having 32 sub-arrays is that DDR SDRAM memory uses a pre-fetching of 2n. Since this is a xl6 DDR memory, 32 bits must be accessed from each bank for a read or write operation.
Note that pre-fetching can be done in a number of ways. Consider a memory array that is organized as a P x Q matrix that needs to support 2n pre-fetching. One approach is to divide the P x Q array into two arrays (i.e. two P x Q/2 arrays) and access both arrays in parallel, so that we get 2 bits per column address. Another approach is to not split the array but modify the column decoder so that 2 bits are selected for each column address (in other words, the least significant bit of the column address is not used). Some embodiments of the invention are described that use the first approach. However, the teachings of the present invention are applicable to different pre-fetching implementations.
Looking at the organization of a xl6 256Mb DDR2 SDRAM, the xlό 256Mb DDR2 SDRAM is organized similar to the xl6 256Mb SDRAM (and the xl6 256Mb DDR SDRAM). The following identify some of the changes to the memory core:
Each bank has 64 sub-arrays. Each sub-array is now a 8192 x 128 matrix (i.e. P = 8192, Q = 128). The reason for the 64 sub-arrays per bank is that DDR2 SDRAM uses a 4n pre-fetching. Since this is a xl6 DDR2 memory (n = 16), 64 bits must be accessed from each bank for a read or write operation. hi all cases (SDRAM, DDR, DDR2), data bits to/from each bank are brought to a multiplexer / de-multiplexer (hereafter referred to as a MUX), which in turn is connected to the external DQ pins. This MUX is typically in the middle of the DRAM chip. FIG. 4 illustrates a block diagram of an interface and multiple banks in a DRAM. As shown in FIG. 4, bank 0 (410), bank 1 (420), bank 2 (430) and bank 3 (440) are accessed by interface 450. Note that for SDRAM, m = n, for DDR SDRAM, m = 2n, DDR2 SDRAM, m = 4n, and DDR3 SDRAM (proposed), m = 8n, Also note that the data MUX is typically part of the interface.
This arrangement works well for a conventional DRAM since everything is on a single die. However, in one embodiment of the invention, the interface is on a separate die. If we were to just move the interface alone (to another die) without disturbing the memory core, then the number of I/O pads on both the memory core chip and the interface chip will become quite large, as shown in TABLE 5 below for a xl6 4-bank implementation. FIG. 5 is a block diagram illustrating a DRAM chip with an interface removed. For this embodiment, bank 0 (510), bank 1 (520), bank 2 (530) and bank 3 (540) are coupled to VO pads 550, 560, 570 and 580, respectively. If we look at only the data pins and ignored the address, command, power and ground pins, we can see that the number of data signals that have to go off-chip between the DRAM core chip and the interface chip is 4m.
TABLE 5
Figure imgf000010_0001
Figure imgf000011_0001
So, it is quite obvious that removing the interface without disturbing the rest of the memory core quickly leads to a very large number of off-chip connections, especially for wider external data bus widths and higher data speeds (because, the amount of pre- fetching will increase with higher data speeds). Under these conditions, either the DRAM core chip or the interface chip or both will become pad limited, which will increase the cost of the total solution.
In one embodiment, in order to reduce the number of off-chip connections between the DRAM core chip and the interface chip, some part or all of the multiplexing of the data I/O from the banks is done in the core chip itself.
One option is to route all the data bits from each bank to a central MUX, and then connect the other side of the MUX to off-chip drivers. This is quite similar to the current practice for center bonded DRAMs. FIG. 6 illustrates one embodiment for a center bonded DRAM core chip. For this example, integrated circuit 600 includes bank 0 (610), bank 1 (620), bank 2 (630) and bank 3 (640) coupled to MUX 650. MUX 650 is connected to substrate bonding pads 670 via bond wires 680 through I/O pads 660.
The drawback with this approach is that bond wires 680 that connect I/O pads 660 on the DRAM core die to the substrate bonding pads 670 become quite long. Long bond wires have significant inductance and limit the speed at which the memory chip can operate.
In another embodiment, edge bonding for the core chip is used. FIG. 7 illustrates one embodiment for an edge bonded DRAM core chip. For this embodiment, integrated circuit 700 includes bank 0 (710), bank 1 (720), bank 2 (730) and bank 3 (740). I/O pads
750, located on the silicon die 705, are connected to the substrate bonding pads 760 via bond wires 780.
If the DRAM core was organized with one bank per quadrant, then the number of data I/O pads will be equal to 4m as illustrated previously. The other option is to route the data bits from each bank to a centrally located MUX (as shown in FIG. 6) and then route the signals from the other side of the MUX to the periphery of the die. However, this means that the data signals will have to traverse the die twice - once from the bank to the central MUX and once from the central MUX to the periphery. This increases routing complexity, may possibly require an extra metal layer on the die (higher cost), and adds to the latency of the memory core. hi another embodiment, an inventive "Distributed-Bank" architecture is used. In this architecture, a bank is distributed (or spread) across all 4 quadrants instead of concentrating a bank in only one quadrant. Using this architecture, data MUXs, located in all 4 quadrants, select the appropriate bank, and the data signals corresponding to the selected bank can be easily routed to the periphery of the chip.
FIG. 8 illustrates one embodiment for a concentrated-bank architecture. For the purpose of this illustration, a xl6, 4-bank, 256Mb DDR2 SDRAM core is used. However, any type of DRAM, with different external data widths, different number of banks, different density, and different amount of pre-fetching may be used without deviating from the spirit or scope of the invention. As previously shown, each bank (810, 820, 830 and 840) in a xl6, 4-bank, 256Mb DDR2 SDRAM consists of 64 sub-arrays, with each sub-array organized as a 8192 x 128 array of memory cells.
FIG. 9 illustrates one embodiment for a distributed-bank architecture. For this embodiment, the DRAM core chip is divided into four quadrants (910, 920, 930 and 940). Each quadrant includes a portion of a bank.
FIG. 10 illustrates one embodiment for a quadrant in a distributed-bank architecture DRAM core chip. As discussed previously, there are 64 sub-arrays per quadrant with each sub-array being a 8192 x 128 matrix. Instead of assigning all 64 sub- arrays in a single quadrant to a single bank in the concentrated-bank architecture, there arel6 sub-arrays to each of the 4 banks within a single quadrant in the distributed-bank architecture. In the distributed-bank architecture embodiment, local data MUXs are located in each quadrant to select one of the four banks.
FIG. 11 is block diagram illustrating one embodiment of a distributed-bank architecture universal DRAM core chip. For this embodiment, the banks of DRAM cells are distributed among quadrant 1110, 1120, 1130 and 1140. An address decoder 1150, located in the center of the chip, controls word line drivers 1155, 1164, 1170 and 1176 in quadrants 1110, 1120, 1130 and 1140 respectively. The data from the bank sub-arrays are output to sense amplifiers (1157, 1166, 1172 and 1178) and input to the respective bank select MUXs (1160, 1168, 1174 and 1180). The data is then routed to data I/O pads 1162 located in the proximity for each of the quadrants.
Since 64 data bits are accessed from the core chip for every read or write operation, the interface chip may be designed or configured to act similar to a xl6 DDR2
SDRAM, x8 DDR2 SDRAM, x4 DDR2 SDRAM, x2 DDR2 SDRAM, or xl DDR2
SDRAM, hi fact, the interface chip may be designed to support any data width between xl and xl6 when operating in a 4n pre-fetch mode.
The distributed-bank architecture is flexible enough to support protocols like SDRAM, DDR SDRAM, DDR2 SDRAM, and DDR3 SDRAM. For example, the DRAM core chip shown in FIG. 11 may be configured or used as shown in FIG. 12 to support DDR2 speeds. FIG 12 is a block diagram illustrating a distributed-bank architecture DRAM core chip configured to support DDR2 speeds. MUX 1210 selects 64 bits of data for one of the banks (1220, 1230, 1240 and 1250). MUX 1210 represents the data MUXs located in all four quadrants on the DRAM core chip.
The DRAM core chip shown in FIG. 11 may also be configured or used as shown in FIG 13 to support DDR SDRAM speeds when it is operated in a 2n pre-fetch mode. FIG. 13 is a block diagram illustrating a distributed-bank architecture DRAM core chip configured to support DDR speeds and external bus widths from 17 to 32 bits. MUX 1310 selects 64 bits of data for one of the banks (1320, 1330, 1340 and 1350). The mode of operation shown in FIG. 13 may be used with the appropriate interface chip to support external data widths between (and inclusive) of 17 and 32 in a 2n pre-fetch mode. The same DRAM core chip may be used with the appropriate interface chip to support external data widths between (and inclusive) 9 and 16 in a 2n pre-fetch mode when operated as shown in FIG. 14. FIG. 14 is a block diagram illustrating a distributed-bank architecture DRAM core chip configured to support DDR speeds and external bus widths from 9 to 16 bits. For this embodiment, MUX 1410 selects 32 bits of data for one of the banks (1420, 1430, 1440 and 1450).
Also, the same DRAM core chip can be used with the appropriate interface chip to support external data widths between (and inclusive of) 1 and 8 in a 2n pre-fetch mode. FIG. 15 is a block diagram illustrating a distributed-bank architecture DRAM core chip configured to support DDR speeds and external bus widths from 1 to 8 bits. For this embodiment, MUX 1510 selects 16 bits of data for one of the banks (1520, 1530, 1540 and 1550).
From these architectures, the internal data bus width (the width of the bus between the DRAM core chip and the interface chip) may be configured to match the amount of pre-fetching required (which is determined by the external data rate) and the width of the external data bus. The external data bus is the bus from the interface chip to the ASIC or memory controller. The DRAM core chip as shown in FIG. 11 may be configured to support the following modes and requirements shown in TABLE 6.
TABLE 6
Figure imgf000014_0001
Note that:
The proposed DDR3 SDRAM is an example of an 8n pre-fetch protocol; DDR2 SDRAM is an example of a 4n pre-fetch protocol; DDR SDRAM is an example of a 2n pre-fetch protocol; and SDRAM is an example of a In pre-fetch protocol (i.e. no pre-fetching needed). Again, for the DRAM core chip shown in FIG. 11, 3 modes of operation may be defined and a 2-bit binary code may be assigned to represent them as shown in TABLE 7.
TABLE 7
Figure imgf000015_0001
These two bits (Mode[l:0]) may be inputs to the DRAM core chip so that the internal data bus width is selected through external means. For example, the Mode[l:0] inputs to the core chip may be selected by means of fuses on the core chip or on the interface chip, by means of pull-up or pull-down resistors in the package of either chip (or in the common package) or on the printed circuit board, or may be driven by a register on the interface chip, or may be part of the address input to the core chip.
Let us assume that the Mode[l:0] inputs to the DRAM core chip are controlled by a register in the interface chip. FIG. 16 illustrates one embodiment for a portion of a DRAM core chip that includes a decoder for selecting a mode of operation. The decoder 1610 in the core chip is aware of the Mode[l :0] inputs as shown in FIG. 16.
Note that the embodiments disclosed below are based on the DRAM core chip shown in FIG. 11 only for the purpose of explaining the concept, and that the following embodiments are applicable to DRAM core chips of different densities, number of banks, internal organization, and number of sub-arrays. For the purpose of simplicity, only bank
0 is shown being accessed in the different modes of operation.
The mode decoder truth table is shown below in TABLE 8. In TABLE 8 below, RA = Row Address X = Don't Care H = Asserted
L = Not Asserted
TABLE 8
Figure imgf000015_0002
Figure imgf000016_0001
Based on the techniques of the present invention, a universal DRAM core chip, such as the embodiment shown in FIG. 11, may be configured to support a wide variety of data speeds and widths. For example, the core chip shown in FIG. 11 may support data rates up to 8*f MB/s, where f is the maximum clock rate (in MHz) at which the DRAM core can run in sync with the external data bus without using pre-fetching (i.e. using a pre- fetching of In). For modern DRAM processes and designs, f is typically between 100MHz and 200MHz. So, the DRAM core chip shown in FIG. 11 supports maximum data rates between 800MB/s and 1600MB/s (1.6GB/s). In order to build custom memory cost-effectively, it is imperative that the DRAM core chip be used in a variety of markets. This will reduce the cost of the core chip because of economies of scale. Since the memory core is typically 90% to 95% of the silicon area, the overall cost may be lowered. Here, we can make two observations:
Some markets for the universal DRAM core chip value low power at the expense of performance (e.g. cell phones and other handheld devices) whereas other markets will sacrifice power to achieve higher speed (e.g, PC graphics and game console markets).
Semiconductor fabrication process is inherently statistical in nature. That is, if we fabricate a statistically significant number of identical chips, some of the chips will only be capable of operating below the target speed, some of the chip will be capable of operating at the target speed, and some of the chips will be capable of operating above the target speed. These are known in the industry as slow, typical, and fast parts respectively. Usually, the fast parts are sold at a price premium over the other parts while the slow parts are sold at lower prices compared to the typical parts.
However, slow parts typically consume less power than the typical parts, which in turn typically consume less power than the fast parts. So, if we can sort the DRAM core chips according to their maximum speeds of operation (usually called "speed binning") before they are attached to the interface chips, we can:
Attach interface chips designed for low power markets (e.g. an SDRAM-like interface for the cell phone market) to the slow core parts; Attach interface chips designed for the high performance/speed markets (e.g. a GDDR3-like interface for the game console market) to the fast core parts; and
Attach interface chips designed for markets sensitive to both power and performance (e.g. a DDR-like interface for the server market) to the typical core parts. This allows us to maximize the ASP (average selling price or average sales price) of all the solutions since all the core chips have natural homes.
Speed binning of memory chips is typically done after it is packaged. Note that it is possible to do a simple speed sort of the memory chips at the wafer level itself. In order to do a speed sort or speed bin, we need to use ATE (automatic test equipment), also known as tester.
When we speed bin the DRAM core chips, we need to measure the time required for basic operations like Read, Write, Activate (open one or more pages), Precharge (close one or more pages), and Refresh. To satisfy this requirement, the DRAM core chips, defined by the present invention, are fully functional asynchronous DRAM chips capable of stand-alone operation. In other words, the DRAM core chips contain all the necessary circuits and capabilities needed to access the internal array used to store the data.
Memory makers, especially DRAM manufacturers, build redundancy into the memory core. For example, if the memory array is to be organized as P x Q (P rows and Q columns), the actual array is designed as (P + i) x (Q + j), where i and j are small compared to P and Q respectively. This allows the memory makers to replace up to i defective rows in the main array with the redundant rows, and up to j defective columns in the main array with the redundant columns. With the help of the redundant rows and columns, memory makers can increase the yield (i.e. the percentage of fully functional chips) to -=90%. Ih a typical DRAM manufacturing flow, the individual dies on a wafer are tested at low speed and the partially functional dies (i.e. those with some defective rows and/or columns) are marked. The defective rows and/or columns on these marked dies are replaced with the redundant rows and/or columns respectively.
However, a die that uses the redundant rows and/or columns (because it had some defective rows and/or columns) will be slower than a die that does not use redundant rows and/or columns. This is due to the nature of how redundancy is built into the memory and how it is enabled. Therefore: Interface chips that are designed for high performance markets may be attached to the DRAM core dies that do not have any defective rows and/or columns in the main array.
In another embodiment, the defective rows and/or columns of memory core dies are not replaced with the redundant rows and/or columns, but are configured to operate the memory core dies as (P / y) x (Q / z), where y and z are preferably powers of 2
(including 2° = 1). These DRAM core chips may then be attached to interface chips that are designed for high performance markets.
As we have seen previously, the DRAM makers use pre-fetching to support higher external data rates. For example, DDR2 SDRAM uses 4n pre-fetching. This means that for an n-bit wide external data bus, 4n data bits are accessed from the memory core for every read or write, hi a conventional DRAM (where the memory core and the interface are on the same die), increasing the amount of pre-fetching increases the amount of metal interconnects on the die, which has a modest impact on the cost. In the invention described herein, increasing the amount of pre-fetching may make either the memory core chip or the interface chip or both pad limited. Being pad limited can increase the cost substantially.
Burst mode is another technique that can be used to increase the data rate of memory chips, hi burst mode, the memory chip reads or writes multiple data bits per column address. For example, an n-bit wide (external data bus width) memory chip that is configured for a burst mode of 4n will access 4n bits from the memory core for a given column address. So this is quite similar to a 4n pre-fetch except that in burst mode, the same data wires are used. In other words, in a memory chip that supports 4n burst mode (but not 4n pre-fetching), the internal data bus between the memory core and the interface is only n-bits wide. Each line in the internal bus carries 4 data bits that are separated in time.
The difference between pre-fetching and burst mode is shown in FIGS. 17a and 17b. FIG 17a is a block diagram illustrating the relationship between the internal data bus rate and the external data bus rate for 4n pre-fetching. Memory core 1710 is coupled to memory interface 1720 via internal data bus 1715 at 4n @ fls Hz data rate. The memory interface 1720 is coupled to external data bus 1725, and under these conditions, the external data bus operates at a n @ 4*f1? Hz data rate. FIG. 17b is a block diagram illustrating the relationship between the internal data bus rate and the external data bus rate for burst mode with a length of 4n. Memory core 1730 is coupled to memory interface 1750 via internal data bus 1740 at n @ 4*f2, Hz data rate. The memory interface 1750 is coupled to external data bus 1760, and for the burst mode of operation, the external data bus operates at a n @ 4*f2, Hz data rate. Typically, pre-fetching will provide higher external data rates than burst mode.
However, burst mode does not increase the amount of off-chip connections between the core chip and the interface chip. So, in some embodiments, it is preferable to design the DRAM core chip of this invention with burst mode capability.
As mentioned previously, one of the aspects of this invention is the ability to test and speed bin the memory core chips and then attach the appropriate interface chips. Testing and speed binning of the DRAM core chip is usually done on a tester. This requires the core chip to have sufficiently strong output drivers to drive the inputs of the tester, which are usually some distance (several inches) from the outputs of the core chip. However, in the normal mode of operation, the inputs of the interface chip will be much closer (< 1") to the outputs of the core chip. So3 it is not necessary to have strong output drivers in the core chip in the normal mode of operation. In order to satisfy both requirements, in some embodiments the DRAM core chip preferably has output drivers whose strength or drive capability is adjustable. For example, the core chip may have, by default, normal strength output drivers that are capable of driving signals across some distance to the inputs of the tester. However, when an interface chip is attached to the core chip, a signal from the interface chip decreases the drive strength of the core chip's output drivers.
In some embodiments, the output drivers of interface chip that interface with the DRAM core chip have similar adjustable drive strength capability. This allows testing of the interface chips separately prior to attaching them to the core chips. Note that the adjustable drive strength drivers are not necessarily required on the interface chip on the pins that interface to the electronic host system. However, it is preferable to have the adjustable strength capability on these drivers as well so that the drive strength can be tailored to the requirements of the system or external world. As with the DRAM core chips, the strength of the output drivers on the interface chip that communicate with the core chip are preferably controlled by a signal from the core chip.
FIG. 18 is a block diagram illustrating an example multi-chip memory implementation. The solution includes a DRAM core chip 1810 and an interface chip 1820. In some embodiments, the main characteristics of the DRAM core chip of this invention are:
Asynchronous or synchronous DRAM that is capable of stand-alone operation;
A plurality of DRAM core chips may be coupled together with one or more interface chips;
A plurality of interface chips may be coupled together with one or more DRAM core chips;
The interface on the DRAM core chip may include a custom and/or industry standard interface; Has address inputs (bank address, row address, column address - row and column address can be on separate inputs or multiplexed on same pins);
Has command inputs like address strobes, read/write, output enable, and data masks);
Has control inputs that determine mode of operation - examples are inputs that determine the width of the internal data bus (bus between the memory core chip and interface chip) aid inputs that determine the strength of the output drivers;
Has control outputs that determine some aspect of the functions performed by the interface chip;
Internal data bus width > external data bus width (bus from interface chip to memory controller or ASIC);
Optional burst mode capability;
Adjustable drive strength on output drivers;
Capable of well-defined standard operations like Read, Write, Activate, Precharge, and Refresh that can be clearly characterized in terms of speed; and May be tested, burnt in, and speed binned independently (i.e. in stand-alone mode).
In some embodiments, the main characteristics of the interface chip of this invention are:
Implements the protocol used by the memory controller; Interface chip implements an industry standard protocol like DDR SDRAM,
DDR2 SDRAM, GDDR2 SDRAM3 etc.; Interface chip implements an industry standard protocol with custom extensions (e.g. GDDR2 SDRAM with extensions as specified by mutual agreement with one or more customers);
Interface chip implements a fully custom protocol as specified by one or more customers or a fully custom protocol developed in-house;
Interface chip operates as a transformer to convert protocols from the external interface to the interface of the DRAM core chip (e.g., synchronous to asynchronous and asynchronous to synchronous);
Interface chip determines the signaling used by the external interface; For example, single ended, pseudo-differential, fully differential;
For example, push-pull outputs, open drain/collector outputs;
For example, asynchronous, synchronous, source synchronous, SerDes-like where clock is encoded/embedded in the data stream;
Determines the width of the external data bus; Determines the speed of operation of the memory chip (by memory chip, we mean the combination of the DRAM core chip and the interface chip);
Determines the pin out of the memory chip as seen by the external world;
Allows the pin out of the memory chip to better match the pin out of the ASIC / memory controller to reduce the board routing complexity; Implements special or custom functions and modes of operation;
Example, special power management functions and operating modes; and
Example, special error detection and error correction capabilities, as well as other types of redundancy capabilities and functions.
The DRAM core chip and the interface chip of this invention may be attached together in a number of different ways:
One or more DRAM core chip dies and one or more interface chip dies may be electrically connected to each other and the whole combination be put into a single package (e.g., a single DRAM core chip die with a single interface chip die, multiple
DRAM core chip dies with a single interface chip die, or a single DRAM core chip die with multiple interface chip dies).
The core chip die may be put in a separate package, and then the interface chip die may then be electrically attached to the package containing the core chip die; The interface chip die may be put in a separate package, and then the core chip die may then be electrically attached to the package containing the interface chip die;
The core chip die can be put in a separate package; the interface chip die may be put in a separate package; and the two packages can be electrically attached to each other; Multiple DRAM core chip dies may be put in a separate package; the interface chip die may be put in a separate package; and the two packages can be electrically attached to each other;
A DRAM core chip die may be put in a separate package; multiple interface chip dies may be put in a separate package; and the two packages can be electrically attached to each other;
The DRAM core chip die and the interface chip die may be electrically attached in any way without deviating from the spirit or scope of the invention.
One aspect of this invention is that a multi-chip DRAM that is built according to this invention, might have higher cost than a traditional DRAM, especially if the DRAM core chip die and the interface chip die were packaged separately and then attached to each other. This is due to the cost associated with the extra package. One way to ameliorate this is to put multiple DRAM core chip dies in a single package. For the purpose of this discussion, we shall consider putting two DRAM core chip dies in a single package, each die being a 256Mb density device. A typical DRAM manufacturing process might have the following sequences after the wafer has been fully processed:
DRAM dies on a wafer are tested at low speed and dies with defective rows and/or columns are marked;
The defective rows and/or columns are replaced with redundant rows and/or columns; Wafer is diced into individual dies, which are then packaged;
Packaged parts are tested for functionality - parts damaged by the packaging process are eliminated;
Tested packaged parts undergo long term burn in to eliminate infant mortality parts; and Burnt in parts are optionally tested again for functionality and shipped.
So, if we place two 256Mb DRAM core dies in a single package, the following 3 bins may be generated after the parts have been packaged and burnt-ύr. Bin A - both the DRAM core chip dies are functional, so the total capacity is 512Mb
Bin B - only one of the DRAM core chip dies is functional, so the total capacity is 256Mb Bin C - neither of the DRAM core chip dies is functional, so the total capacity is
OMb
The bin C parts should be discarded. We can now use the bin B parts for those markets and/or customers who require only 256Mb devices. For example, a handheld device manufacturer might require only a 256Mb DRAM. So, the bin B parts can be attached to the interface chips designed for this manufacturer. Other markets and/or manufacturers might require 512Mb devices. For example, a network router manufacturer might need 512Mb DRAMs. So, we can use bin A parts for this manufacturer by attaching the appropriate interface chips to the bin A parts. This concept can be extended to cover more than two DRAM core chip dies in a single package as well as DRAM core chip dies of all densities.
As disclosed above, some embodiments cover the idea of attaching multiple DRAM core chips to a single interface chip. The core chips may be attached to the interface chip in a number of different ways. Some of these ways are described below and in FIG. 19. Again, for the purpose of illustration, we shall assume that two 4-bank 256Mb DRAM core chips (FIG. 11) are attached to the interface chip. Each of the core chips has a 64-bit wide data bus designed to connect to the interface chip. Note that the idea explained below can be applied to DRAM core chips with different number of banks, density, data bus width, etc.
In one method (1910), the row addresses are used to select the DRAM core chip. hi a second method (1920), bank addresses are used to select DRAM core chips. In a third method (1930), the column addresses are used to select the DRAM core chip.
The two DRAM core chips are attached to the interface chip such that only one of the core chips is accessible at any given time. That is, the two core chips look to the electronic host system as a single 512Mb DRAM with 4 banks. This implies that the interface chip will use the row address to select one or the other core chip.
The two DRAM core chips are attached to the interface such that both of the core chips are accessible at any given time, and that the two chips look to the external world electronic host system as a single 512Mb DRAM with 8 banks. This implies that the interface chip will use the bank address to select one or the other core chip.
The two DRAM core chips are attached to the interface chip such that both of the core chips are accessible at any given time, and that the two chips look to the electronic host system as a single 512Mb DRAM with 4 banks. The interface chip uses the column address to select one or the other core chip. Note that in other embodiments an interface chip always accesses both the core chips in parallel, so that the data bus between the core chips and the interface chip becomes 128-bits wide. For this embodiment, the interface chip doubles the external data rate. In other words, the amount of pre-fetching has been doubled.
In other embodiments the multi-chip solution is configured such that the attachment of the DRAM core chips to the interface chip is programmable. For example, the customer may choose between one of the three methods listed above to attach two A- bank, 64-bit wide, 256Mb DRAM core chips to an interface chip by programmable means. These means include using fuses on the interface chip or the core chips, pull-up or pull-down resistors on the package substrates or printed circuit board, or by means of a register on the interface chip or core chips. However, any way of attaching the DRAM core chips to the interface chip may be accomplished without deviating from the spirit or scope of the invention. Other embodiments of the invention include building redundant memory systems by attaching multiple DRAM core chips to an interface chip. For example, when more than one core chip is attached to an interface chip, redundancy is added by several means including:
Storing identical copies of the data in corresponding locations of each core chip when data is written to the memory by the memory controller; when the data is read back by the memory controller, the interface chip can read the multiple copies of the data from the different core chips and select the correct copy and transmit it to the memory controller. The correct copy can be determined by means like majority voting, and/or by the use of parity or ECC bits; Using (n + m) bits to store n data bits.
Another aspect of this invention is placing memory core chips of different types behind a common interface chip. For example, we can place any combination of DRAM core, SRAM (Static Random Access Memory), and Flash chips behind a common interface chip. Multi-Chip Package (MCP) memory solutions are fairly common in the cell phone and handheld markets today. The issue with current MCP solutions is that each of these memories (DRAM, SRAM, Flash) has different interfaces, which complicates the design of the memory controller, the packaging, and the board routing. Placing any possible combination of DRAM core chip, SRAM, and Flash behind a common interface chip simplifies the memory controller design since the idiosyncrasies of each of these memory types is hidden from the memory controller. In addition, the board routing is simplified.
Another aspect of this invention is placing a large and slow memory as well as a smaller and faster memory behind a common interface chip and using the faster memory as a cache for the slower memory. For example, an SRAM chip might be used as the cache for a DRAM core chip or a DRAM core chip can be used as the cache for a Flash chip. The cache management logic may be built into the interface chip so that the cache is transparent to the memory controller. Alternately, the cache may be made visible to the memory controller and managed by the memory controller. Let us consider the case of an interface chip that has been designed to interface to one or more DRAM core chips and an SRAM chip. The SRAM chip can be used to cache the rows in the DRAM core chips that were recently opened. The SRAM may be used to cache the entire contents of the recently opened rows in the DRAM or cache part of the contents of the recently opened rows in the DRAM. The properties of the cache (associatively of the cache lines, mapping between DRAM rows and SRAM cache lines, etc.) may be determined by programming certain registers in the interface chip. By storing data that has a high likelihood of being accessed in the near future, system performance is improved.
Using a cache also allows the interface chip to do speculative pre-fetching of data from the DRAM core chip (and storing it in the SRAM cache chip), which again improves system performance. In addition, the interface chip may operate with SRAM chips (that are used as caches) of different densities. This allows the same interface chip to be used across several different segments within a market. For example, a DRAM / SRAM combination memory device may includes a common interface where the DRAM capacity is 512Mb and the SRAM capacity ranges from 0 to 32Mb. This allows a DRAM supplier to ship the 512Mb DRAM + 32Mb SRAM combination in the high performance segment of the market, ship a 512Mb DRAM + 8Mb SRAM combination in the mainstream segment of the market, and ship a 512Mb DRAM (no SRAM cache) device in the value segment of the market.
The techniques of the present invention are not just applicable to DRAM. As such, the DRAM core chip need not necessarily be a trench-capacitor or stacked-capacitor device. The present invention is applicable to a variety of memory technologies like MRAM (Magnetic RAM), FRAM (Ferro-electric RAM)3 Ovonics memory, molecular memory (e.g. memory technology developed by ZettaCore), carbon nanotube memory (e.g. memory technology developed by Nantero Inc.), etc.
Another aspect of this invention is that it can be used with DRAM core chips that have different architectures like FCRAM (Fast Cycle RAM), RLDRAM (Reduced Latency DRAM), ESDRAM (Enhanced SDRAM).
Some embodiments of invention allow the use of a common memory core across a wide range of markets while varying the interface of the memory core according to the market and customer needs. It also allows the interface to be kept constant while changing the memory core behind the interface to address the needs of the different segments within a market.
Although the present invention has been described in terms of specific exemplary embodiments, it will be appreciated that various modifications and alterations might be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims

CLAIMS What is claimed is:
1. A memory device comprising: at least one first integrated circuit die comprising: memory core comprising a plurality of memory cells; first interface circuit for accessing said memory cells of said memory core; and at least one second integrated circuit die, electrically coupled to said first integrated circuit die, comprising a second interface for accessing said memory core via said first interface circuit and for interfacing said memory core to an external circuit.
2. The memory device as set forth in claim 1, further comprising a plurality of first integrated circuit dies.
3. The memory device as set forth in claim .1, further comprising a plurality of second integrated circuit dies.
4. The memory device as set forth in claim 1, further comprising: first package for housing said at least one first integrated circuit die; and second package for housing said at least one second integrated circuit die.
5. The memory device as set forth in claim 1, further comprising a single package for housing said first and second integrated circuit dies.
6. The memory device as set forth in claim 1, further comprising a single package for housing said at least one first integrated circuit die and for housing a plurality o off s seeccoonndd i inntteeggrraatteedd c ciirrccuuiitt d diieess..
7. The memory device as set forth in claim 1, further comprising a single package for housing a plurality of first integrated circuit dies and for housing said at least one second integrated circuit die,
8. The memory device as set forth in claim 1 , further comprising: first package for housing a plurality of first integrated circuit dies; and second package for housing said at least one second integrated circuit die.
9. The memory device as set forth in claim 1, wherein said second interface of said second integrated circuit die for converting protocols between said external circuit and first interface of said first integrated circuit.
10. The memory device as set forth in claim 9, wherein said protocols comprise different protocols.
11. The memory device as set forth in claim 9, wherein said second interface of said second integrated circuit die for converting between synchronous and asynchronous protocols.
12. The memory device as set forth in claim 9, wherein said second interface of said second integrated circuit die for converting between custom and industry standard protocols.
13. The memory device as set forth in claim 1, wherein said first interface circuit of said first integrated circuit die provides a read operation to said memory cells.
14. The memory device as set forth in claim 1, wherein said first interface circuit of said first integrated circuit die provides a write operation to said memory cells.
15. The memory device as set forth in claim 1, wherein said first integrated circuit of said first integrated circuit die provides activating, pre-charging and refreshing operations to said memory cells.
16. The memory device as set forth in claim 1, wherein said first integrated circuit die comprises a plurality of memory banks for partitioning said memory cells.
17. The memory device as set forth in claim 16, wherein said memory banks comprise a plurality of sub-arrays arranged in a distributed bank architecture across a plurality of physical sections such that a physical section of said memory cells comprises a plurality of sub-arrays associated with different memory banks.
18. The memory device as set forth in claim 1, wherein said memory cells comprise at least one non-volatile memory cell.
19. The memory device as set forth in claim 1, wherein said memory cells comprise at least one volatile memory cell.
20. A memory device comprising: first integrated circuit die comprising: memory core comprising a plurality of memory cells; first interface circuit coupled to said memory cells, for dynamically configuring a data rate for transferring data between said memory cells and said first interface circuit; and second integrated circuit die, electrically coupled to said first integrated circuit die, comprising a second interface for accessing data from said memory core via said first interface circuit and for interfacing said memory core to an external circuit.
21. The memory device as set forth in claim 20, wherein: said memory device comprises an internal data bus for coupling data between said first integrated circuit die and said second integrated circuit die; and said configurable internal data rate comprises a configurable data width for said internal data bus.
22. The memory device as set forth in claim 20, wherein said configurable internal data rate comprises a configurable amount of data for pre-fetching.
23. The memory device as set forth in claim 20, wherein said first integrated circuit die further comprising at least one input for programming said internal data rate.
24. The memory device as set forth in claim 20, further comprising an external data bus comprising an external data rate for accessing data external to said memory device, wherein said configurable internal data rate permits selecting an internal data rate compatible with said external data rate.
PCT/US2006/024360 2005-06-24 2006-06-23 An integrated memory core and memory interface circuit WO2007002324A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1020147005128A KR101463375B1 (en) 2005-06-24 2006-06-23 An integrated memory core and memory interface circuit
KR1020087001812A KR101318116B1 (en) 2005-06-24 2006-06-23 An integrated memory core and memory interface circuit
GB0800734A GB2441726B (en) 2005-06-24 2006-06-23 An integrated memory core and memory interface circuit
DE112006001810T DE112006001810T5 (en) 2005-06-24 2006-06-23 Integrated memory core and memory interface circuitry
KR1020137004006A KR101377305B1 (en) 2005-06-24 2006-06-23 An integrated memory core and memory interface circuit
JP2008518401A JP2008544437A (en) 2005-06-24 2006-06-23 Integrated memory core and memory interface circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US69363105P 2005-06-24 2005-06-24
US60/693,631 2005-06-24

Publications (2)

Publication Number Publication Date
WO2007002324A2 true WO2007002324A2 (en) 2007-01-04
WO2007002324A3 WO2007002324A3 (en) 2007-04-12

Family

ID=37595841

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/024360 WO2007002324A2 (en) 2005-06-24 2006-06-23 An integrated memory core and memory interface circuit

Country Status (6)

Country Link
US (4) US20070014168A1 (en)
JP (1) JP2008544437A (en)
KR (3) KR101463375B1 (en)
DE (1) DE112006001810T5 (en)
GB (1) GB2441726B (en)
WO (1) WO2007002324A2 (en)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7515453B2 (en) * 2005-06-24 2009-04-07 Metaram, Inc. Integrated memory core and memory interface circuit
US7610417B2 (en) 2005-11-30 2009-10-27 Rambus Inc. Data-width translator coupled between variable-width and fixed-width data ports and supporting multiple data-width configurations
US8233303B2 (en) 2006-12-14 2012-07-31 Rambus Inc. Multi-die memory device
JP2012248267A (en) * 2001-03-21 2012-12-13 Micron Technology Inc Memory device and method having data bus with multiple pre-fetch i/o configuration
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8572320B1 (en) 2009-01-23 2013-10-29 Cypress Semiconductor Corporation Memory devices and systems including cache devices for memory modules
US8725983B2 (en) 2009-01-23 2014-05-13 Cypress Semiconductor Corporation Memory devices and systems including multi-speed access of memory modules
WO2014110050A1 (en) * 2013-01-08 2014-07-17 Qualcomm Incorporated Memory device having an adaptable number of open rows
US9047976B2 (en) 2006-07-31 2015-06-02 Google Inc. Combined signal delay and power saving for use with a plurality of memory circuits
US9110832B2 (en) 2009-06-03 2015-08-18 Micron Technology, Inc. Object oriented memory in solid state devices
US9542353B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US9727458B2 (en) 2006-02-09 2017-08-08 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
CN108155174A (en) * 2016-12-06 2018-06-12 三星电子株式会社 Semiconductor storage unit including stacked chips and with its memory module
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
CN108804315A (en) * 2018-05-23 2018-11-13 北京五八信息技术有限公司 Applied to the test method of dynamic development, device, electronic equipment and storage medium
US10679722B2 (en) 2016-08-26 2020-06-09 Sandisk Technologies Llc Storage system with several integrated components and method for use therewith

Families Citing this family (130)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050022798A (en) * 2003-08-30 2005-03-08 주식회사 이즈텍 A system for analyzing bio chips using gene ontology, and a method thereof
EP1825433A4 (en) * 2004-11-23 2010-01-06 Efficient Memory Technology Method and apparatus of multiple abbreviations of interleaved addressing of paged memories and intelligent memory banks therefor
US8190809B2 (en) * 2004-11-23 2012-05-29 Efficient Memory Technology Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines
US7367586B2 (en) * 2005-05-09 2008-05-06 Ford Global Technologies, Llc Airbag restraint for automotive vehicle
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US7609567B2 (en) * 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US7580312B2 (en) * 2006-07-31 2009-08-25 Metaram, Inc. Power saving system and method for use with a plurality of memory circuits
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US7392338B2 (en) 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US8041881B2 (en) * 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US7355905B2 (en) 2005-07-01 2008-04-08 P.A. Semi, Inc. Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage
KR101303518B1 (en) 2005-09-02 2013-09-03 구글 인코포레이티드 Methods and apparatus of stacking drams
KR100655078B1 (en) * 2005-09-16 2006-12-08 삼성전자주식회사 Semiconductor memory device having bit registering layer and method for driving thereof
KR100757924B1 (en) * 2006-03-07 2007-09-11 주식회사 하이닉스반도체 Apparatus and method for controlling test mode of semiconductor memory
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
US7746724B2 (en) * 2007-01-31 2010-06-29 Qimonda Ag Asynchronous data transmission
US8427891B2 (en) * 2007-04-17 2013-04-23 Rambus Inc. Hybrid volatile and non-volatile memory device with a shared interface circuit
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US7623365B2 (en) * 2007-08-29 2009-11-24 Micron Technology, Inc. Memory device interface methods, apparatus, and systems
US7899983B2 (en) * 2007-08-31 2011-03-01 International Business Machines Corporation Buffered memory module supporting double the memory device data width in the same physical space as a conventional memory module
US8082482B2 (en) * 2007-08-31 2011-12-20 International Business Machines Corporation System for performing error correction operations in a memory hub device of a memory module
US7865674B2 (en) * 2007-08-31 2011-01-04 International Business Machines Corporation System for enhancing the memory bandwidth available through a memory module
US7861014B2 (en) * 2007-08-31 2010-12-28 International Business Machines Corporation System for supporting partial cache line read operations to a memory module to reduce read data traffic on a memory channel
US7840748B2 (en) * 2007-08-31 2010-11-23 International Business Machines Corporation Buffered memory module with multiple memory device data interface ports supporting double the memory capacity
US8086936B2 (en) * 2007-08-31 2011-12-27 International Business Machines Corporation Performing error correction at a memory device level that is transparent to a memory channel
US7818497B2 (en) * 2007-08-31 2010-10-19 International Business Machines Corporation Buffered memory module supporting two independent memory channels
US8019919B2 (en) * 2007-09-05 2011-09-13 International Business Machines Corporation Method for enhancing the memory bandwidth available through a memory module
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
JP5095344B2 (en) * 2007-10-19 2012-12-12 本田技研工業株式会社 Data writing device
WO2009082706A1 (en) * 2007-12-21 2009-07-02 The Trustees Of Columbia University In The City Of New York Active cmos sensor array for electrochemical biomolecular detection
US7770077B2 (en) * 2008-01-24 2010-08-03 International Business Machines Corporation Using cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem
US7925824B2 (en) * 2008-01-24 2011-04-12 International Business Machines Corporation System to reduce latency by running a memory channel frequency fully asynchronous from a memory device frequency
US7925825B2 (en) * 2008-01-24 2011-04-12 International Business Machines Corporation System to support a full asynchronous interface within a memory hub device
US7930470B2 (en) * 2008-01-24 2011-04-19 International Business Machines Corporation System to enable a memory hub device to manage thermal conditions at a memory device level transparent to a memory controller
US7925826B2 (en) * 2008-01-24 2011-04-12 International Business Machines Corporation System to increase the overall bandwidth of a memory channel by allowing the memory channel to operate at a frequency independent from a memory device frequency
US7930469B2 (en) * 2008-01-24 2011-04-19 International Business Machines Corporation System to provide memory system power reduction without reducing overall memory system performance
US8140936B2 (en) * 2008-01-24 2012-03-20 International Business Machines Corporation System for a combined error correction code and cyclic redundancy check code for a memory channel
US8516185B2 (en) 2009-07-16 2013-08-20 Netlist, Inc. System and method utilizing distributed byte-wise buffers on a memory module
US8787060B2 (en) 2010-11-03 2014-07-22 Netlist, Inc. Method and apparatus for optimizing driver load in a memory package
US8154901B1 (en) 2008-04-14 2012-04-10 Netlist, Inc. Circuit providing load isolation and noise reduction
JP5351145B2 (en) * 2008-04-22 2013-11-27 パナソニック株式会社 Memory control device, memory system, semiconductor integrated circuit, and memory control method
CN102047229A (en) * 2008-05-29 2011-05-04 先进微装置公司 Embedded programmable component for memory device training
US8106520B2 (en) * 2008-09-11 2012-01-31 Micron Technology, Inc. Signal delivery in stacked device
US7872936B2 (en) * 2008-09-17 2011-01-18 Qimonda Ag System and method for packaged memory
US7957216B2 (en) * 2008-09-30 2011-06-07 Intel Corporation Common memory device for variable device width and scalable pre-fetch and page size
JP5419431B2 (en) * 2008-11-28 2014-02-19 ルネサスエレクトロニクス株式会社 Semiconductor memory device
US8368112B2 (en) * 2009-01-14 2013-02-05 Cree Huizhou Opto Limited Aligned multiple emitter package
US9105323B2 (en) * 2009-01-23 2015-08-11 Micron Technology, Inc. Memory device power managers and methods
WO2010144624A1 (en) 2009-06-09 2010-12-16 Google Inc. Programming of dimm termination resistance values
US8626997B2 (en) * 2009-07-16 2014-01-07 Micron Technology, Inc. Phase change memory in a dual inline memory module
US9128632B2 (en) 2009-07-16 2015-09-08 Netlist, Inc. Memory module with distributed data buffers and method of operation
US8316175B2 (en) 2009-11-03 2012-11-20 Inphi Corporation High throughput flash memory system
US8966208B2 (en) * 2010-02-25 2015-02-24 Conversant Ip Management Inc. Semiconductor memory device with plural memory die and controller die
WO2011132310A1 (en) * 2010-04-23 2011-10-27 株式会社日立製作所 Information processing device and semiconductor storage device
EP2579158A1 (en) * 2010-05-27 2013-04-10 Fujitsu Limited Memory system and memory interface device
IT1401755B1 (en) 2010-08-30 2013-08-02 St Microelectronics Srl INTEGRATED ELECTRONIC DEVICE WITH VERTICAL CONDUCTION AND ITS MANUFACTURING METHOD.
IT1401756B1 (en) * 2010-08-30 2013-08-02 St Microelectronics Srl INTEGRATED ELECTRONIC DEVICE WITH ON-BOARD TERMINATION STRUCTURE AND ITS MANUFACTURING METHOD.
IT1401754B1 (en) * 2010-08-30 2013-08-02 St Microelectronics Srl INTEGRATED ELECTRONIC DEVICE AND ITS MANUFACTURING METHOD.
US8582373B2 (en) * 2010-08-31 2013-11-12 Micron Technology, Inc. Buffer die in stacks of memory dies and methods
KR101796116B1 (en) 2010-10-20 2017-11-10 삼성전자 주식회사 Semiconductor device, memory module and memory system having the same and operating method thereof
US9684623B2 (en) * 2011-03-17 2017-06-20 Rambus Inc. Memory system with independently adjustable core and interface data rates
US9170878B2 (en) 2011-04-11 2015-10-27 Inphi Corporation Memory buffer with data scrambling and error correction
US8687451B2 (en) 2011-07-26 2014-04-01 Inphi Corporation Power management in semiconductor memory system
WO2013032753A2 (en) * 2011-08-26 2013-03-07 The Trustees Of Columbia University In The City Of New York Systems and methods for switched-inductor integrated voltage regulators
US8564004B2 (en) 2011-11-29 2013-10-22 Cree, Inc. Complex primary optics with intermediate elements
US9158726B2 (en) 2011-12-16 2015-10-13 Inphi Corporation Self terminated dynamic random access memory
US8949473B1 (en) 2012-02-16 2015-02-03 Inphi Corporation Hybrid memory blade
US9069717B1 (en) 2012-03-06 2015-06-30 Inphi Corporation Memory parametric improvements
WO2013181803A1 (en) 2012-06-06 2013-12-12 Qualcomm Incorporated Methods and systems for redundant data storage in a register
US8861277B1 (en) 2012-06-26 2014-10-14 Inphi Corporation Method of using non-volatile memories for on-DIMM memory address list storage
US9647799B2 (en) 2012-10-16 2017-05-09 Inphi Corporation FEC coding identification
US9129071B2 (en) * 2012-10-24 2015-09-08 Texas Instruments Incorporated Coherence controller slot architecture allowing zero latency write commit
TWI486736B (en) * 2012-12-06 2015-06-01 Yu Sheng So Method and equipment for configuring lighting
KR20150019268A (en) * 2013-08-13 2015-02-25 에스케이하이닉스 주식회사 Data input/output apparatus and system including the same
US9842630B2 (en) 2013-10-16 2017-12-12 Rambus Inc. Memory component with adjustable core-to-interface data rate ratio
US9135982B2 (en) * 2013-12-18 2015-09-15 Intel Corporation Techniques for accessing a dynamic random access memory array
US10185499B1 (en) 2014-01-07 2019-01-22 Rambus Inc. Near-memory compute module
US9553670B2 (en) 2014-03-03 2017-01-24 Inphi Corporation Optical module
US9874800B2 (en) 2014-08-28 2018-01-23 Inphi Corporation MZM linear driver for silicon photonics device characterized as two-channel wavelength combiner and locker
US10622522B2 (en) 2014-09-05 2020-04-14 Theodore Lowes LED packages with chips having insulated surfaces
US9325419B1 (en) 2014-11-07 2016-04-26 Inphi Corporation Wavelength control of two-channel DEMUX/MUX in silicon photonics
US9473090B2 (en) 2014-11-21 2016-10-18 Inphi Corporation Trans-impedance amplifier with replica gain control
US9553689B2 (en) 2014-12-12 2017-01-24 Inphi Corporation Temperature insensitive DEMUX/MUX in silicon photonics
US9461677B1 (en) 2015-01-08 2016-10-04 Inphi Corporation Local phase correction
US9484960B1 (en) 2015-01-21 2016-11-01 Inphi Corporation Reconfigurable FEC
US9547129B1 (en) 2015-01-21 2017-01-17 Inphi Corporation Fiber coupler for silicon photonics
US9548726B1 (en) 2015-02-13 2017-01-17 Inphi Corporation Slew-rate control and waveshape adjusted drivers for improving signal integrity on multi-loads transmission line interconnects
US9632390B1 (en) 2015-03-06 2017-04-25 Inphi Corporation Balanced Mach-Zehnder modulator
US9690494B2 (en) 2015-07-21 2017-06-27 Qualcomm Incorporated Managing concurrent access to multiple storage bank domains by multiple interfaces
US11120884B2 (en) 2015-09-30 2021-09-14 Sunrise Memory Corporation Implementing logic function and generating analog signals using NOR memory strings
US9892800B2 (en) 2015-09-30 2018-02-13 Sunrise Memory Corporation Multi-gate NOR flash thin-film transistor strings arranged in stacked horizontal active strips with vertical control gates
US9842651B2 (en) 2015-11-25 2017-12-12 Sunrise Memory Corporation Three-dimensional vertical NOR flash thin film transistor strings
US10818638B2 (en) * 2015-11-30 2020-10-27 Pezy Computing K.K. Die and package
US9847839B2 (en) 2016-03-04 2017-12-19 Inphi Corporation PAM4 transceivers for high-speed communication
KR20180079811A (en) 2017-01-02 2018-07-11 삼성전자주식회사 Method of reconfiguring DQ pad of memory device and DQ pad reconfigurable memory device
US11527510B2 (en) * 2017-06-16 2022-12-13 Micron Technology, Inc. Finer grain dynamic random access memory
US10608008B2 (en) 2017-06-20 2020-03-31 Sunrise Memory Corporation 3-dimensional nor strings with segmented shared source regions
JP7203054B2 (en) 2017-06-20 2023-01-12 サンライズ メモリー コーポレイション Three-dimensional NOR-type memory array architecture and method of manufacturing the same
US10692874B2 (en) 2017-06-20 2020-06-23 Sunrise Memory Corporation 3-dimensional NOR string arrays in segmented stacks
KR102482896B1 (en) 2017-12-28 2022-12-30 삼성전자주식회사 Memory device including heterogeneous volatile memory chips and electronic device including the same
KR102483476B1 (en) * 2018-04-03 2023-01-03 에스케이하이닉스 주식회사 Semiconductor memory apparatus supporting repair with data I/O terminal as a unit and method of repairing the semiconductor memory apparatus
CN108665916A (en) * 2018-04-09 2018-10-16 烽火通信科技股份有限公司 A kind of memory modules and its implementation of Android embedded devices
KR20190124914A (en) 2018-04-27 2019-11-06 삼성전자주식회사 Dynamic random access memory device and memory system having the same
TWI713195B (en) 2018-09-24 2020-12-11 美商森恩萊斯記憶體公司 Wafer bonding in fabrication of 3-dimensional nor memory circuits and integrated circuit formed therefrom
US10871906B2 (en) 2018-09-28 2020-12-22 Intel Corporation Periphery shoreline augmentation for integrated circuits
US10483978B1 (en) * 2018-10-16 2019-11-19 Micron Technology, Inc. Memory device processing
US11164847B2 (en) 2019-12-03 2021-11-02 Intel Corporation Methods and apparatus for managing thermal behavior in multichip packages
US11515309B2 (en) 2019-12-19 2022-11-29 Sunrise Memory Corporation Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array
TW202143049A (en) 2020-02-07 2021-11-16 美商森恩萊斯記憶體公司 High capacity memory circuit with low effective latency
WO2021173209A1 (en) * 2020-02-24 2021-09-02 Sunrise Memory Corporation High capacity memory module including wafer-section memory circuit
US11842777B2 (en) 2020-11-17 2023-12-12 Sunrise Memory Corporation Methods for reducing disturb errors by refreshing data alongside programming or erase operations
US11848056B2 (en) 2020-12-08 2023-12-19 Sunrise Memory Corporation Quasi-volatile memory with enhanced sense amplifier operation
TW202310429A (en) 2021-07-16 2023-03-01 美商日升存儲公司 3-dimensional memory string array of thin-film ferroelectric transistors

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838165A (en) * 1996-08-21 1998-11-17 Chatter; Mukesh High performance self modifying on-the-fly alterable logic FPGA, architecture and method
US6338108B1 (en) * 1997-04-15 2002-01-08 Nec Corporation Coprocessor-integrated packet-type memory LSI, packet-type memory/coprocessor bus, and control method thereof
US6510097B2 (en) * 2001-02-15 2003-01-21 Oki Electric Industry Co., Ltd. DRAM interface circuit providing continuous access across row boundaries

Family Cites Families (354)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3800292A (en) 1972-10-05 1974-03-26 Honeywell Inf Systems Variable masking for segmented memory
US4069452A (en) 1976-09-15 1978-01-17 Dana Laboratories, Inc. Apparatus for automatically detecting values of periodically time varying signals
IT1109655B (en) 1978-06-28 1985-12-23 Cselt Centro Studi Lab Telecom SOLID STATE GROUND MEMORY ORGANIZED WITH SELF-CORRECTIVE BIT AND RECONFIGURABLE FOR A REGISTERED PROGRAM CONTROL SYSTEM
US4334307A (en) 1979-12-28 1982-06-08 Honeywell Information Systems Inc. Data processing system with self testing and configuration mapping capability
US4323965A (en) 1980-01-08 1982-04-06 Honeywell Information Systems Inc. Sequential chip select decode apparatus and method
US4646128A (en) * 1980-09-16 1987-02-24 Irvine Sensors Corporation High-density electronic processing package--structure and fabrication
US4525921A (en) 1981-07-13 1985-07-02 Irvine Sensors Corporation High-density electronic processing package-structure and fabrication
US4566082A (en) 1983-03-23 1986-01-21 Tektronix, Inc. Memory pack addressing system
JPS59200327A (en) 1983-04-26 1984-11-13 Nec Corp Control system of peripheral device
US4592019A (en) 1983-08-31 1986-05-27 At&T Bell Laboratories Bus oriented LIFO/FIFO memory
US4698748A (en) 1983-10-07 1987-10-06 Essex Group, Inc. Power-conserving control system for turning-off the power and the clocking for data transactions upon certain system inactivity
US4780843A (en) 1983-11-07 1988-10-25 Motorola, Inc. Wait mode power reduction system and method for data processor
KR890004820B1 (en) 1984-03-28 1989-11-27 인터내셔널 비지네스 머신즈 코포레이션 Stacked double density memory module using industry standard memory chips
AU593281B2 (en) 1985-09-11 1990-02-08 Motorola, Inc. Semi-conductor integrated circuit/systems
US4794597A (en) 1986-03-28 1988-12-27 Mitsubishi Denki Kabushiki Kaisha Memory device equipped with a RAS circuit
US4710903A (en) 1986-03-31 1987-12-01 Wang Laboratories, Inc. Pseudo-static memory subsystem
US4862347A (en) 1986-04-22 1989-08-29 International Business Machine Corporation System for simulating memory arrays in a logic simulation machine
US4706166A (en) 1986-04-25 1987-11-10 Irvine Sensors Corporation High-density electronic modules--process and product
JPS63163912A (en) 1986-12-26 1988-07-07 Toshiba Corp Microcomputer system
US4764846A (en) 1987-01-05 1988-08-16 Irvine Sensors Corporation High density electronic package comprising stacked sub-modules
US4922451A (en) 1987-03-23 1990-05-01 International Business Machines Corporation Memory re-mapping in a microcomputer system
US4888687A (en) 1987-05-04 1989-12-19 Prime Computer, Inc. Memory control system
KR970003915B1 (en) 1987-06-24 1997-03-22 미다 가쓰시게 Semiconductor device and the use memory module
US5025364A (en) 1987-06-29 1991-06-18 Hewlett-Packard Company Microprocessor emulation system with memory mapping using variable definition and addressing of memory space
JPS6484496A (en) 1987-09-26 1989-03-29 Mitsubishi Electric Corp Semiconductor memory
US4983533A (en) 1987-10-28 1991-01-08 Irvine Sensors Corporation High-density electronic modules - process and product
US4937791A (en) 1988-06-02 1990-06-26 The California Institute Of Technology High performance dynamic ram interface
US4899107A (en) * 1988-09-30 1990-02-06 Micron Technology, Inc. Discrete die burn-in for nonpackaged die
US4956694A (en) 1988-11-04 1990-09-11 Dense-Pac Microsystems, Inc. Integrated circuit chip stacking
US5104820A (en) 1989-07-07 1992-04-14 Irvine Sensors Corporation Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting
US5907512A (en) 1989-08-14 1999-05-25 Micron Technology, Inc. Mask write enablement for memory devices which permits selective masked enablement of plural segments
US5453434A (en) 1989-11-13 1995-09-26 Allergan, Inc. N-substituted derivatives of 3R,4R-ethyl-[(1-methyl-1H-imidazol-5-yl)methyl]-2-pyrrolidone
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Integrated circuit i/o using a high performance bus interface
US5995443A (en) 1990-04-18 1999-11-30 Rambus Inc. Synchronous memory device
US5252807A (en) 1990-07-02 1993-10-12 George Chizinsky Heated plate rapid thermal processor
US5544347A (en) 1990-09-24 1996-08-06 Emc Corporation Data storage system controlled remote data mirroring with respectively maintained data indices
JPH04230508A (en) 1990-10-29 1992-08-19 Internatl Business Mach Corp <Ibm> Apparatus and method for controlling electric power with page arrangment control
US5257233A (en) 1990-10-31 1993-10-26 Micron Technology, Inc. Low power memory module using restricted RAM activation
JPH0511876A (en) 1990-12-25 1993-01-22 Mitsubishi Electric Corp Digital circuit device
US5278796A (en) 1991-04-12 1994-01-11 Micron Technology, Inc. Temperature-dependent DRAM refresh circuit
DE69226150T2 (en) * 1991-11-05 1999-02-18 Hsu Fu Chieh Redundancy architecture for circuit module
US5309324A (en) 1991-11-26 1994-05-03 Herandez Jorge M Device for interconnecting integrated circuit packages to circuit boards
JPH05298134A (en) 1991-12-16 1993-11-12 Internatl Business Mach Corp <Ibm> Method and mechanism for processing of processing error in computer system
US5559990A (en) 1992-02-14 1996-09-24 Advanced Micro Devices, Inc. Memories with burst mode access
GB2264794B (en) 1992-03-06 1995-09-20 Intel Corp Method and apparatus for automatic power management in a high integration floppy disk controller
US5282177A (en) 1992-04-08 1994-01-25 Micron Technology, Inc. Multiple register block write method and circuit for video DRAMs
US5384745A (en) 1992-04-27 1995-01-24 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device
US5629876A (en) * 1992-07-10 1997-05-13 Lsi Logic Corporation Method and apparatus for interim in-situ testing of an electronic system with an inchoate ASIC
JPH06194415A (en) 1992-09-30 1994-07-15 American Teleph & Telegr Co <Att> Method and device for testing logic circuit
US5519832A (en) 1992-11-13 1996-05-21 Digital Equipment Corporation Method and apparatus for displaying module diagnostic results
US5347428A (en) 1992-12-03 1994-09-13 Irvine Sensors Corporation Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip
US5644161A (en) 1993-03-29 1997-07-01 Staktek Corporation Ultra-high density warp-resistant memory module
WO1994026083A1 (en) 1993-04-23 1994-11-10 Irvine Sensors Corporation Electronic module comprising a stack of ic chips
EP0713609B1 (en) 1993-08-13 2003-05-07 Irvine Sensors Corporation Stack of ic chips as substitute for single ic chip
JP3304531B2 (en) 1993-08-24 2002-07-22 富士通株式会社 Semiconductor storage device
US5502667A (en) 1993-09-13 1996-03-26 International Business Machines Corporation Integrated multichip memory module structure
US5561622A (en) 1993-09-13 1996-10-01 International Business Machines Corporation Integrated memory cube structure
US5467455A (en) 1993-11-03 1995-11-14 Motorola, Inc. Data processing system and method for performing dynamic bus termination
US5677291A (en) 1993-12-10 1997-10-14 Hoechst Marion Roussel, Inc. Method of lowering serum cholesterol levels with 2,6-di-alkyl-4-silyl-phenols
US5502333A (en) 1994-03-30 1996-03-26 International Business Machines Corporation Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit
US5448511A (en) 1994-06-01 1995-09-05 Storage Technology Corporation Memory stack with an integrated interconnect and mounting structure
JP3304893B2 (en) 1994-06-28 2002-07-22 日本電気株式会社 Memory selection circuit and semiconductor memory device
US5530836A (en) 1994-08-12 1996-06-25 International Business Machines Corporation Method and apparatus for multiple memory bank selection
US5798961A (en) 1994-08-23 1998-08-25 Emc Corporation Non-volatile memory module
US5796673A (en) * 1994-10-06 1998-08-18 Mosaid Technologies Incorporated Delay locked loop implementation in a synchronous dynamic random access memory
US6047073A (en) 1994-11-02 2000-04-04 Advanced Micro Devices, Inc. Digital wavetable audio synthesizer with delay-based effects processing
US5513135A (en) 1994-12-02 1996-04-30 International Business Machines Corporation Synchronous memory packaged in single/dual in-line memory module and method of fabrication
US5606710A (en) * 1994-12-20 1997-02-25 National Semiconductor Corporation Multiple chip package processor having feed through paths on one die
US6421754B1 (en) 1994-12-22 2002-07-16 Texas Instruments Incorporated System management mode circuits, systems and methods
US5729503A (en) * 1994-12-23 1998-03-17 Micron Technology, Inc. Address transition detection on a synchronous design
US5721859A (en) * 1994-12-23 1998-02-24 Micron Technology, Inc. Counter control circuit in a burst memory
US5652724A (en) 1994-12-23 1997-07-29 Micron Technology, Inc. Burst EDO memory device having pipelined output buffer
US5526320A (en) 1994-12-23 1996-06-11 Micron Technology Inc. Burst EDO memory device
US5598376A (en) 1994-12-23 1997-01-28 Micron Technology, Inc. Distributed write data drivers for burst access memories
US5682354A (en) 1995-11-06 1997-10-28 Micron Technology, Inc. CAS recognition in burst extended data out DRAM
US5640364A (en) 1994-12-23 1997-06-17 Micron Technology, Inc. Self-enabling pulse trapping circuit
US5668773A (en) 1994-12-23 1997-09-16 Micron Technology, Inc. Synchronous burst extended data out DRAM
US5610864A (en) * 1994-12-23 1997-03-11 Micron Technology, Inc. Burst EDO memory device with maximized write cycle timing
US5675549A (en) 1994-12-23 1997-10-07 Micron Technology, Inc. Burst EDO memory device address counter
US5717654A (en) * 1995-02-10 1998-02-10 Micron Technology, Inc. Burst EDO memory device with maximized write cycle timing
US5731945A (en) 1995-02-22 1998-03-24 International Business Machines Corporation Multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes
US5608262A (en) * 1995-02-24 1997-03-04 Lucent Technologies Inc. Packaging multi-chip modules without wire-bond interconnection
US5901105A (en) 1995-04-05 1999-05-04 Ong; Adrian E Dynamic random access memory having decoding circuitry for partial memory blocks
US5692121A (en) 1995-04-14 1997-11-25 International Business Machines Corporation Recovery unit for mirrored processors
IN188196B (en) 1995-05-15 2002-08-31 Silicon Graphics Inc
US5850368A (en) 1995-06-01 1998-12-15 Micron Technology, Inc. Burst EDO memory address counter
US5860106A (en) * 1995-07-13 1999-01-12 Intel Corporation Method and apparatus for dynamically adjusting power/performance characteristics of a memory subsystem
US5752045A (en) 1995-07-14 1998-05-12 United Microelectronics Corporation Power conservation in synchronous SRAM cache memory blocks of a computer system
JP2701802B2 (en) 1995-07-17 1998-01-21 日本電気株式会社 Printed circuit board for bare chip mounting
FR2737591B1 (en) 1995-08-03 1997-10-17 Sgs Thomson Microelectronics DEVICE FOR ORGANIZING ACCESS TO A MEMORY BUS
FR2737592B1 (en) 1995-08-03 1997-10-17 Sgs Thomson Microelectronics HDLC CIRCUIT WITH SHARED INTERNAL BUS
US5724288A (en) 1995-08-30 1998-03-03 Micron Technology, Inc. Data communication for memory
US5924111A (en) 1995-10-17 1999-07-13 Huang; Chu-Kai Method and system for interleaving data in multiple memory bank partitions
US5748914A (en) 1995-10-19 1998-05-05 Rambus, Inc. Protocol for communication with dynamic memory
US5590071A (en) 1995-11-16 1996-12-31 International Business Machines Corporation Method and apparatus for emulating a high capacity DRAM
US5604714A (en) * 1995-11-30 1997-02-18 Micron Technology, Inc. DRAM having multiple column address strobe operation
US5729504A (en) 1995-12-14 1998-03-17 Micron Technology, Inc. Continuous burst edo memory device
KR970051229A (en) 1995-12-22 1997-07-29 김광호 Semiconductor memory device using asynchronous generation signal
US5692202A (en) 1995-12-29 1997-11-25 Intel Corporation System, apparatus, and method for managing power in a computer system
US5966724A (en) 1996-01-11 1999-10-12 Micron Technology, Inc. Synchronous memory device with dual page and burst mode operations
US5627791A (en) 1996-02-16 1997-05-06 Micron Technology, Inc. Multiple bank memory with auto refresh to specified bank
US5680342A (en) 1996-04-10 1997-10-21 International Business Machines Corporation Memory module package with address bus buffering
US6001671A (en) 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US5661677A (en) 1996-05-15 1997-08-26 Micron Electronics, Inc. Circuit and method for on-board programming of PRD Serial EEPROMS
US5802395A (en) 1996-07-08 1998-09-01 International Business Machines Corporation High density memory modules with improved data bus performance
KR100202021B1 (en) 1996-09-30 1999-06-15 전주범 Device for clamping an optical disk player
US5787457A (en) 1996-10-18 1998-07-28 International Business Machines Corporation Cached synchronous DRAM architecture allowing concurrent DRAM operations
US5917758A (en) 1996-11-04 1999-06-29 Micron Technology, Inc. Adjustable output driver circuit
US5949254A (en) 1996-11-26 1999-09-07 Micron Technology, Inc. Adjustable output driver circuit
US5923611A (en) 1996-12-20 1999-07-13 Micron Technology, Inc. Memory having a plurality of external clock signal inputs
KR100231605B1 (en) 1996-12-31 1999-11-15 김영환 Apparatus of reduced power consumption for semiconductor memory device
US5838177A (en) 1997-01-06 1998-11-17 Micron Technology, Inc. Adjustable output driver circuit having parallel pull-up and pull-down elements
US6708144B1 (en) * 1997-01-27 2004-03-16 Unisys Corporation Spreadsheet driven I/O buffer synthesis process
US5953263A (en) 1997-02-10 1999-09-14 Rambus Inc. Synchronous memory device having a programmable register and method of controlling same
US5870347A (en) 1997-03-11 1999-02-09 Micron Technology, Inc. Multi-bank memory input/output line selection
EP0931290A1 (en) * 1997-03-21 1999-07-28 International Business Machines Corporation Address mapping for system memory
KR100253282B1 (en) 1997-04-01 2000-05-01 김영환 Auto power down circuit of memory device
JP2964983B2 (en) 1997-04-02 1999-10-18 日本電気株式会社 Three-dimensional memory module and semiconductor device using the same
JP3504104B2 (en) * 1997-04-03 2004-03-08 富士通株式会社 Synchronous DRAM
US5915167A (en) 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
US5903500A (en) 1997-04-11 1999-05-11 Intel Corporation 1.8 volt output buffer on flash memories
US5870350A (en) 1997-05-21 1999-02-09 International Business Machines Corporation High performance, high bandwidth memory bus architecture utilizing SDRAMs
US5875142A (en) 1997-06-17 1999-02-23 Micron Technology, Inc. Integrated circuit with temperature detector
JPH1125678A (en) * 1997-06-27 1999-01-29 Samsung Electron Co Ltd Output driver and semiconductor storage
US5995424A (en) 1997-07-16 1999-11-30 Tanisys Technology, Inc. Synchronous memory test system
US5963429A (en) 1997-08-20 1999-10-05 Sulzer Intermedics Inc. Printed circuit substrate with cavities for encapsulating integrated circuits
AU9798798A (en) * 1997-10-10 1999-05-03 Rambus Incorporated Power control system for synchronous memory device
US6226709B1 (en) 1997-10-24 2001-05-01 Compaq Computer Corporation Memory refresh control system
KR100252048B1 (en) * 1997-11-18 2000-05-01 윤종용 Data masking circuit and its method for semiconductor memory device
US5953215A (en) 1997-12-01 1999-09-14 Karabatsos; Chris Apparatus and method for improving computer memory speed and capacity
US5835435A (en) 1997-12-02 1998-11-10 Intel Corporation Method and apparatus for dynamically placing portions of a memory in a reduced power consumtion state
US20040236877A1 (en) 1997-12-17 2004-11-25 Lee A. Burton Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM)
US5956233A (en) 1997-12-19 1999-09-21 Texas Instruments Incorporated High density single inline memory module
JP3335898B2 (en) 1998-01-08 2002-10-21 株式会社東芝 Private branch exchange system and its private branch exchange.
US6222739B1 (en) * 1998-01-20 2001-04-24 Viking Components High-density computer module with stacked parallel-plane packaging
US6742098B1 (en) 2000-10-03 2004-05-25 Intel Corporation Dual-port buffer-to-memory interface
US5963464A (en) 1998-02-26 1999-10-05 International Business Machines Corporation Stackable memory card
US6154821A (en) 1998-03-10 2000-11-28 Rambus Inc. Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain
JP3285815B2 (en) 1998-03-12 2002-05-27 松下電器産業株式会社 Lead frame, resin-encapsulated semiconductor device and method of manufacturing the same
US6233650B1 (en) 1998-04-01 2001-05-15 Intel Corporation Using FET switches for large memory arrays
JP4017248B2 (en) * 1998-04-10 2007-12-05 株式会社日立製作所 Semiconductor device
US6512392B2 (en) * 1998-04-17 2003-01-28 International Business Machines Corporation Method for testing semiconductor devices
US6016282A (en) * 1998-05-28 2000-01-18 Micron Technology, Inc. Clock vernier adjustment
US6199151B1 (en) 1998-06-05 2001-03-06 Intel Corporation Apparatus and method for storing a device row indicator for use in a subsequent page-miss memory cycle
JPH11353228A (en) * 1998-06-10 1999-12-24 Mitsubishi Electric Corp Memory module system
JP3109479B2 (en) 1998-06-12 2000-11-13 日本電気株式会社 Heat radiator and memory module equipped with heat radiator
US6557071B2 (en) 1998-06-22 2003-04-29 Intel Corporation Memory system including a memory controller having a data strobe generator and method for accesing a memory using a data storage
US6510503B2 (en) * 1998-07-27 2003-01-21 Mosaid Technologies Incorporated High bandwidth memory interface
US6910152B2 (en) * 1998-08-28 2005-06-21 Micron Technology, Inc. Device and method for repairing a semiconductor memory
US6526471B1 (en) * 1998-09-18 2003-02-25 Digeo, Inc. Method and apparatus for a high-speed memory subsystem
JP4156721B2 (en) * 1998-09-18 2008-09-24 富士通株式会社 Semiconductor integrated circuit device
US6668242B1 (en) 1998-09-25 2003-12-23 Infineon Technologies North America Corp. Emulator chip package that plugs directly into the target system
US6587912B2 (en) * 1998-09-30 2003-07-01 Intel Corporation Method and apparatus for implementing multiple memory buses on a memory module
US6438670B1 (en) 1998-10-02 2002-08-20 International Business Machines Corporation Memory controller with programmable delay counter for tuning performance based on timing parameter of controlled memory storage device
US6038673A (en) * 1998-11-03 2000-03-14 Intel Corporation Computer system with power management scheme for DRAM devices
US6044032A (en) * 1998-12-03 2000-03-28 Micron Technology, Inc. Addressing scheme for a double data rate SDRAM
KR100355226B1 (en) * 1999-01-12 2002-10-11 삼성전자 주식회사 DRAM performable selectively self-refresh operation for memory bank
US6324071B2 (en) * 1999-01-14 2001-11-27 Micron Technology, Inc. Stacked printed circuit board memory module
US6658016B1 (en) 1999-03-05 2003-12-02 Broadcom Corporation Packet switching fabric having a segmented ring with token based resource control protocol and output queuing control
US6389514B1 (en) 1999-03-25 2002-05-14 Hewlett-Packard Company Method and computer system for speculatively closing pages in memory
KR100287190B1 (en) 1999-04-07 2001-04-16 윤종용 Memory module system connecting a selected memory module with data line &data input/output method for the same
US6625692B1 (en) 1999-04-14 2003-09-23 Micron Technology, Inc. Integrated semiconductor memory chip with presence detect data capability
US6341347B1 (en) * 1999-05-11 2002-01-22 Sun Microsystems, Inc. Thread switch logic in a multiple-thread processor
US7243185B2 (en) 2004-04-05 2007-07-10 Super Talent Electronics, Inc. Flash memory system with a high-speed flash controller
US6336174B1 (en) 1999-08-09 2002-01-01 Maxtor Corporation Hardware assisted memory backup system and method
KR100344927B1 (en) * 1999-09-27 2002-07-19 삼성전자 주식회사 Stack package and method for manufacturing the same
US6166991A (en) * 1999-11-03 2000-12-26 Cypress Semiconductor Corp. Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit
US6683372B1 (en) * 1999-11-18 2004-01-27 Sun Microsystems, Inc. Memory expansion module with stacked memory packages and a serial storage unit
TW451193B (en) 1999-11-30 2001-08-21 Via Tech Inc A method to determine the timing setting value of dynamic random access memory
US7363422B2 (en) * 2000-01-05 2008-04-22 Rambus Inc. Configurable width buffered module
US7017002B2 (en) * 2000-01-05 2006-03-21 Rambus, Inc. System featuring a master device, a buffer device and a plurality of integrated circuit memory devices
US6502161B1 (en) * 2000-01-05 2002-12-31 Rambus Inc. Memory system including a point-to-point linked memory subsystem
US6621760B1 (en) * 2000-01-13 2003-09-16 Intel Corporation Method, apparatus, and system for high speed data transfer using source synchronous data strobe
US6766469B2 (en) 2000-01-25 2004-07-20 Hewlett-Packard Development Company, L.P. Hot-replace of memory
US6522018B1 (en) 2000-05-16 2003-02-18 Micron Technology, Inc. Ball grid array chip packages having improved testing and stacking characteristics
US6466491B2 (en) 2000-05-19 2002-10-15 Fujitsu Limited Memory system and memory controller with reliable data latch operation
JP2001338489A (en) * 2000-05-24 2001-12-07 Mitsubishi Electric Corp Semiconductor device
US6356105B1 (en) * 2000-06-28 2002-03-12 Intel Corporation Impedance control system for a center tapped termination bus
DE10030994A1 (en) 2000-06-30 2002-01-17 Infineon Technologies Ag Semiconductor chip
US7104804B2 (en) 2000-07-03 2006-09-12 Advanced Interconnect Solutions Method and apparatus for memory module circuit interconnection
US20020004897A1 (en) 2000-07-05 2002-01-10 Min-Cheng Kao Data processing apparatus for executing multiple instruction sets
US6523089B2 (en) * 2000-07-19 2003-02-18 Rambus Inc. Memory controller with power management logic
FR2812417A1 (en) 2000-07-27 2002-02-01 St Microelectronics Sa DSP PROCESSOR WITH PARALLEL ARCHITECTURE
US6445591B1 (en) 2000-08-10 2002-09-03 Nortel Networks Limited Multilayer circuit board
US6356500B1 (en) * 2000-08-23 2002-03-12 Micron Technology, Inc. Reduced power DRAM device and method
TW473965B (en) 2000-09-04 2002-01-21 Siliconware Precision Industries Co Ltd Thin type semiconductor device and the manufacturing method thereof
US6487102B1 (en) * 2000-09-18 2002-11-26 Intel Corporation Memory module having buffer for isolating stacked memory devices
US6862653B1 (en) * 2000-09-18 2005-03-01 Intel Corporation System and method for controlling data flow direction in a memory system
US6553450B1 (en) * 2000-09-18 2003-04-22 Intel Corporation Buffer to multiply memory interface
US6349050B1 (en) * 2000-10-10 2002-02-19 Rambus, Inc. Methods and systems for reducing heat flux in memory systems
JP2002151648A (en) * 2000-11-07 2002-05-24 Mitsubishi Electric Corp Semiconductor module
JP2002157883A (en) 2000-11-20 2002-05-31 Fujitsu Ltd Synchronous semiconductor device and latch method for input signal in synchronous semiconductor device
US6484273B1 (en) * 2000-11-29 2002-11-19 Lsi Logic Corporation Integrated EJTAG external bus interface
US6954463B1 (en) 2000-12-11 2005-10-11 Cisco Technology, Inc. Distributed packet processing architecture for network access servers
JP2002197878A (en) * 2000-12-26 2002-07-12 Hitachi Ltd Semiconductor device and data processing system
US7058732B1 (en) * 2001-02-06 2006-06-06 Cypress Semiconductor Corporation Method and apparatus for automatic detection of a serial peripheral interface (SPI) device memory size
US6526757B2 (en) * 2001-02-13 2003-03-04 Robin Mackay Multi pressure mode gas turbine
JP3436253B2 (en) 2001-03-01 2003-08-11 松下電器産業株式会社 Resin-sealed semiconductor device and method of manufacturing the same
JP3436254B2 (en) 2001-03-01 2003-08-11 松下電器産業株式会社 Lead frame and manufacturing method thereof
US6631456B2 (en) 2001-03-06 2003-10-07 Lance Leighnor Hypercache RAM based disk emulation and method
TW588235B (en) * 2001-04-02 2004-05-21 Via Tech Inc Motherboard with less power consumption
US6964005B2 (en) * 2001-06-08 2005-11-08 Broadcom Corporation System and method for interleaving data in a communication device
US6914786B1 (en) 2001-06-14 2005-07-05 Lsi Logic Corporation Converter device
US6535387B2 (en) 2001-06-28 2003-03-18 Intel Corporation Heat transfer apparatus
DE10131939B4 (en) * 2001-07-02 2014-12-11 Qimonda Ag Electronic circuit board with a plurality of housing-type housing semiconductor memories
US6438057B1 (en) 2001-07-06 2002-08-20 Infineon Technologies Ag DRAM refresh timing adjustment device, system and method
FR2827682B1 (en) * 2001-07-20 2004-04-02 Gemplus Card Int PRESSURE REGULATION BY TRANSFER OF A CALIBRATED GAS VOLUME
KR100417858B1 (en) * 2001-07-27 2004-02-05 주식회사 하이닉스반도체 Low power type rambus dram
TW564432B (en) 2001-07-31 2003-12-01 Infineon Technologies Ag Fuse programmable I/O organization
JP2003045179A (en) 2001-08-01 2003-02-14 Mitsubishi Electric Corp Semiconductor device and semiconductor memory module using the same
US20030041295A1 (en) 2001-08-24 2003-02-27 Chien-Tzu Hou Method of defects recovery and status display of dram
US6820169B2 (en) * 2001-09-25 2004-11-16 Intel Corporation Memory control with lookahead power management
US6785793B2 (en) 2001-09-27 2004-08-31 Intel Corporation Method and apparatus for memory access scheduling to reduce memory access latency
US6684292B2 (en) 2001-09-28 2004-01-27 Hewlett-Packard Development Company, L.P. Memory module resync
TW533413B (en) * 2001-10-11 2003-05-21 Cascade Semiconductor Corp Asynchronous hidden refresh of semiconductor memory
US6754132B2 (en) * 2001-10-19 2004-06-22 Samsung Electronics Co., Ltd. Devices and methods for controlling active termination resistors in a memory system
WO2003036722A1 (en) 2001-10-26 2003-05-01 Fujitsu Limited Semiconductor integrated circuit device, electronic device having the circuit device packaged therein, and power consumption reducing method
US7026708B2 (en) * 2001-10-26 2006-04-11 Staktek Group L.P. Low profile chip scale stacking system and method
US7007095B2 (en) 2001-12-07 2006-02-28 Redback Networks Inc. Method and apparatus for unscheduled flow control in packet form
US6910092B2 (en) * 2001-12-10 2005-06-21 International Business Machines Corporation Chip to chip interface for interconnecting chips
US6714891B2 (en) * 2001-12-14 2004-03-30 Intel Corporation Method and apparatus for thermal management of a power supply to a high performance processor in a computer system
KR100406543B1 (en) * 2001-12-24 2003-11-20 주식회사 하이닉스반도체 Pipe-latch control circuit in synchronous memory
CA2366397A1 (en) 2001-12-31 2003-06-30 Tropic Networks Inc. An interface for data transfer between integrated circuits
US6751113B2 (en) * 2002-03-07 2004-06-15 Netlist, Inc. Arrangement of integrated circuits in a memory module
US6707756B2 (en) * 2002-03-12 2004-03-16 Smart Modular Technologies, Inc. System and method for translation of SDRAM and DDR signals
US6545895B1 (en) * 2002-04-22 2003-04-08 High Connection Density, Inc. High capacity SDRAM memory module with stacked printed circuit boards
US7028215B2 (en) 2002-05-03 2006-04-11 Hewlett-Packard Development Company, L.P. Hot mirroring in a computer system with redundant memory subsystems
US7573136B2 (en) 2002-06-27 2009-08-11 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor device components
US6906407B2 (en) * 2002-07-09 2005-06-14 Lucent Technologies Inc. Field programmable gate array assembly
US7010736B1 (en) * 2002-07-22 2006-03-07 Advanced Micro Devices, Inc. Address sequencer within BIST (Built-in-Self-Test) system
US6631086B1 (en) * 2002-07-22 2003-10-07 Advanced Micro Devices, Inc. On-chip repair of defective address of core flash memory cells
US7200711B2 (en) * 2002-08-15 2007-04-03 Network Appliance, Inc. Apparatus and method for placing memory into self-refresh state
US6851032B2 (en) 2002-08-16 2005-02-01 Micron Technology, Inc. Latency reduction using negative clock edge and read flags
KR100468761B1 (en) * 2002-08-23 2005-01-29 삼성전자주식회사 Semiconductor memory system having memory module connected to devided system bus
US7194559B2 (en) * 2002-08-29 2007-03-20 Intel Corporation Slave I/O driver calibration using error-nulling master reference
US6713856B2 (en) 2002-09-03 2004-03-30 Ultratera Corporation Stacked chip package with enhanced thermal conductivity
DE10343525B4 (en) * 2002-09-27 2011-06-16 Qimonda Ag Method for operating semiconductor components, control device for semiconductor components and arrangement for operating memory components
US7028234B2 (en) * 2002-09-27 2006-04-11 Infineon Technologies Ag Method of self-repairing dynamic random access memory
US6952794B2 (en) 2002-10-10 2005-10-04 Ching-Hung Lu Method, system and apparatus for scanning newly added disk drives and automatically updating RAID configuration and rebuilding RAID data
JP4229674B2 (en) * 2002-10-11 2009-02-25 Necエレクトロニクス株式会社 Semiconductor memory device and control method thereof
US20040083324A1 (en) 2002-10-24 2004-04-29 Josef Rabinovitz Large array of mass data storage devices connected to a computer by a serial link
US7035150B2 (en) * 2002-10-31 2006-04-25 Infineon Technologies Ag Memory device with column select being variably delayed
JP5138869B2 (en) * 2002-11-28 2013-02-06 ルネサスエレクトロニクス株式会社 Memory module and memory system
DE10300781B4 (en) 2003-01-11 2014-02-06 Qimonda Ag Memory module, test system and method for testing one or more memory modules
US6705877B1 (en) * 2003-01-17 2004-03-16 High Connection Density, Inc. Stackable memory module with variable bandwidth
KR100468783B1 (en) 2003-02-11 2005-01-29 삼성전자주식회사 Clothespin typed apparatus for dissipating heat generated from semiconductor module
DE10309679B4 (en) * 2003-02-27 2014-05-22 Dr. Johannes Heidenhain Gmbh Scanning unit for scanning a material measure
US6847582B2 (en) * 2003-03-11 2005-01-25 Micron Technology, Inc. Low skew clock input buffer and method
US7480774B2 (en) 2003-04-01 2009-01-20 International Business Machines Corporation Method for performing a command cancel function in a DRAM
US7234099B2 (en) 2003-04-14 2007-06-19 International Business Machines Corporation High reliability memory module with a fault tolerant address and command bus
US7444546B2 (en) * 2003-04-17 2008-10-28 Arm Limited On-board diagnostic circuit for an integrated circuit
US6968440B2 (en) 2003-05-09 2005-11-22 Hewlett-Packard Development Company, L.P. Systems and methods for processor memory allocation
US7428644B2 (en) 2003-06-20 2008-09-23 Micron Technology, Inc. System and method for selective memory module power management
DE10330811B4 (en) * 2003-07-08 2009-08-13 Qimonda Ag Semiconductor memory module
DE10330812B4 (en) * 2003-07-08 2006-07-06 Infineon Technologies Ag Semiconductor memory module
US7412588B2 (en) * 2003-07-25 2008-08-12 International Business Machines Corporation Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus
US7143236B2 (en) * 2003-07-30 2006-11-28 Hewlett-Packard Development Company, Lp. Persistent volatile memory fault tracking using entries in the non-volatile memory of a fault storage unit
DE10334779B4 (en) * 2003-07-30 2005-09-29 Infineon Technologies Ag Semiconductor memory module
KR100585099B1 (en) * 2003-08-13 2006-05-30 삼성전자주식회사 Stacked memory module and memoey system
US7210059B2 (en) 2003-08-19 2007-04-24 Micron Technology, Inc. System and method for on-board diagnostics of memory modules
JP4450586B2 (en) * 2003-09-03 2010-04-14 株式会社ルネサステクノロジ Semiconductor integrated circuit
US7386765B2 (en) * 2003-09-29 2008-06-10 Intel Corporation Memory device having error checking and correction
US7353329B2 (en) * 2003-09-29 2008-04-01 Intel Corporation Memory buffer device integrating refresh logic
JP4386706B2 (en) * 2003-11-06 2009-12-16 富士通マイクロエレクトロニクス株式会社 Semiconductor memory device
US20050108460A1 (en) 2003-11-14 2005-05-19 Intel Corporation Partial bank DRAM refresh
KR101198981B1 (en) 2003-12-09 2012-11-07 톰슨 라이센싱 Memory controller
US7127566B2 (en) 2003-12-18 2006-10-24 Intel Corporation Synchronizing memory copy operations with memory accesses
US7127567B2 (en) 2003-12-18 2006-10-24 Intel Corporation Performing memory RAS operations over a point-to-point interconnect
US7173863B2 (en) * 2004-03-08 2007-02-06 Sandisk Corporation Flash controller cache architecture
US20050018495A1 (en) * 2004-01-29 2005-01-27 Netlist, Inc. Arrangement of integrated circuits in a memory module
US7234081B2 (en) 2004-02-04 2007-06-19 Hewlett-Packard Development Company, L.P. Memory module with testing logic
US7723995B2 (en) * 2004-02-27 2010-05-25 Infineon Technologies Ag Test switching circuit for a high speed data interface
JP4205613B2 (en) 2004-03-01 2009-01-07 エルピーダメモリ株式会社 Semiconductor device
JP3910598B2 (en) 2004-03-04 2007-04-25 松下電器産業株式会社 Resin-sealed semiconductor device and manufacturing method thereof
US7286436B2 (en) 2004-03-05 2007-10-23 Netlist, Inc. High-density memory module utilizing low-density memory components
US7532537B2 (en) 2004-03-05 2009-05-12 Netlist, Inc. Memory module with a circuit providing load isolation and memory domain translation
US7289386B2 (en) 2004-03-05 2007-10-30 Netlist, Inc. Memory module decoder
US6992501B2 (en) * 2004-03-15 2006-01-31 Staktek Group L.P. Reflection-control system and method
KR100558065B1 (en) 2004-03-15 2006-03-10 삼성전자주식회사 Semiconductor module with heat sink
EP1585139A1 (en) * 2004-04-08 2005-10-12 STMicroelectronics Pvt. Ltd An on-chip and at-speed tester for testing and characterization of different types of memories
KR100642414B1 (en) 2004-04-20 2006-11-03 주식회사 하이닉스반도체 Control circuit for semiconductor memory device
US7126399B1 (en) * 2004-05-27 2006-10-24 Altera Corporation Memory interface phase-shift circuitry to support multiple frequency ranges
US7176714B1 (en) * 2004-05-27 2007-02-13 Altera Corporation Multiple data rate memory interface architecture
US7079396B2 (en) 2004-06-14 2006-07-18 Sun Microsystems, Inc. Memory module cooling
US20060010339A1 (en) * 2004-06-24 2006-01-12 Klein Dean A Memory system and method having selective ECC during low power refresh
US7539800B2 (en) 2004-07-30 2009-05-26 International Business Machines Corporation System, method and storage medium for providing segment level sparing
US7669027B2 (en) * 2004-08-19 2010-02-23 Micron Technology, Inc. Memory command delay balancing in a daisy-chained memory topology
US7126393B2 (en) 2004-08-20 2006-10-24 Micron Technology, Inc. Delay circuit with reset-based forward path static delay
US7437497B2 (en) 2004-08-23 2008-10-14 Apple Inc. Method and apparatus for encoding memory control signals to reduce pin count
US7289383B2 (en) * 2004-08-23 2007-10-30 Apple Inc. Reducing the number of power and ground pins required to drive address signals to memory modules
US6965537B1 (en) * 2004-08-31 2005-11-15 Micron Technology, Inc. Memory system and method using ECC to achieve low power refresh
US7200062B2 (en) * 2004-08-31 2007-04-03 Micron Technology, Inc. Method and system for reducing the peak current in refreshing dynamic random access memory devices
US7606049B2 (en) * 2004-09-03 2009-10-20 Entorian Technologies, Lp Module thermal management system and method
US7301831B2 (en) * 2004-09-15 2007-11-27 Rambus Inc. Memory systems with variable delays for write data signals
US7317250B2 (en) 2004-09-30 2008-01-08 Kingston Technology Corporation High density memory card assembly
US7305518B2 (en) * 2004-10-20 2007-12-04 Hewlett-Packard Development Company, L.P. Method and system for dynamically adjusting DRAM refresh rate
DE102004051345B9 (en) 2004-10-21 2014-01-02 Qimonda Ag Semiconductor device, method for inputting and / or outputting test data, and memory module
KR100564635B1 (en) * 2004-10-25 2006-03-28 삼성전자주식회사 Memory system for controlling interface timing in memory module and method thereof
EP1839219B1 (en) * 2004-11-12 2017-03-22 ATI Technologies ULC Method for configuring an integrated circuit
US20060112219A1 (en) 2004-11-19 2006-05-25 Gaurav Chawla Functional partitioning method for providing modular data storage systems
US20060129740A1 (en) 2004-12-13 2006-06-15 Hermann Ruckerbauer Memory device, memory controller and method for operating the same
US20060136791A1 (en) 2004-12-16 2006-06-22 Klaus Nierle Test method, control circuit and system for reduced time combined write window and retention testing
KR100691583B1 (en) 2004-12-31 2007-03-09 학교법인 포항공과대학교 Memory system having multi terminated multi-drop bus
US20060195631A1 (en) 2005-01-31 2006-08-31 Ramasubramanian Rajamani Memory buffers for merging local data from memory modules
US7321950B2 (en) 2005-02-03 2008-01-22 International Business Machines Corporation Method and apparatus for managing write-to-read turnarounds in an early read after write memory system
US20060180926A1 (en) 2005-02-11 2006-08-17 Rambus, Inc. Heat spreader clamping mechanism for semiconductor modules
DE102005009806A1 (en) * 2005-03-03 2006-09-14 Infineon Technologies Ag Buffer component for use in e.g. dynamic random access memory module, has control unit setting control signal for activating memory chips group with consecutive address and command signals, so that signals are taken to memory chips of group
US8301938B2 (en) 2005-03-21 2012-10-30 Hewlett-Packard Development Company, L.P. Managing memory health
US7543102B2 (en) 2005-04-18 2009-06-02 University Of Maryland System and method for performing multi-rank command scheduling in DDR SDRAM memory systems
US7218566B1 (en) 2005-04-28 2007-05-15 Network Applicance, Inc. Power management of memory via wake/sleep cycles
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US7609567B2 (en) 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US7590796B2 (en) 2006-07-31 2009-09-15 Metaram, Inc. System and method for power management in memory systems
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US7580312B2 (en) * 2006-07-31 2009-08-25 Metaram, Inc. Power saving system and method for use with a plurality of memory circuits
KR101463375B1 (en) * 2005-06-24 2014-11-18 구글 인코포레이티드 An integrated memory core and memory interface circuit
US8359187B2 (en) * 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US7392338B2 (en) 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US7454639B2 (en) 2005-06-30 2008-11-18 Intel Corporation Various apparatuses and methods for reduced power states in system memory
US7441064B2 (en) 2005-07-11 2008-10-21 Via Technologies, Inc. Flexible width data protocol
US7327592B2 (en) * 2005-08-30 2008-02-05 Micron Technology, Inc. Self-identifying stacked die semiconductor components
KR101303518B1 (en) * 2005-09-02 2013-09-03 구글 인코포레이티드 Methods and apparatus of stacking drams
KR100704023B1 (en) * 2005-09-26 2007-04-04 삼성전자주식회사 Non volatile Semiconductor Memory Device for improving accuracy in reading out the data of selected memory cell with dummy bitline
JP4790386B2 (en) * 2005-11-18 2011-10-12 エルピーダメモリ株式会社 Stacked memory
US7409491B2 (en) 2005-12-14 2008-08-05 Sun Microsystems, Inc. System memory board subsystem using DRAM with stacked dedicated high speed point to point links
DE102006002090A1 (en) 2006-01-17 2007-07-26 Infineon Technologies Ag Memory module radiator box for use in fully buffered dual inline memory module to remove heat produced in memory module, has even metal plate, at which memory module is provided, where metal plate at the outer edge has reinforcing element
US7411283B2 (en) 2006-02-14 2008-08-12 Sun Microsystems, Inc. Interconnect design for reducing radiated emissions
CN100482060C (en) 2006-02-22 2009-04-22 富准精密工业(深圳)有限公司 Heat radiator
US20080002447A1 (en) 2006-06-29 2008-01-03 Smart Modular Technologies, Inc. Memory supermodule utilizing point to point serial data links
US7379361B2 (en) 2006-07-24 2008-05-27 Kingston Technology Corp. Fully-buffered memory-module with redundant memory buffer in serializing advanced-memory buffer (AMB) for repairing DRAM
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
US20080028135A1 (en) 2006-07-31 2008-01-31 Metaram, Inc. Multiple-component memory interface system and method
US20080025136A1 (en) * 2006-07-31 2008-01-31 Metaram, Inc. System and method for storing at least a portion of information received in association with a first operation for use in performing a second operation
US20080028137A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and Apparatus For Refresh Management of Memory Modules
US7480147B2 (en) 2006-10-13 2009-01-20 Dell Products L.P. Heat dissipation apparatus utilizing empty component slot
US7870459B2 (en) 2006-10-23 2011-01-11 International Business Machines Corporation High density high reliability memory module with power gating and a fault tolerant address and command bus
TWI324736B (en) * 2006-11-01 2010-05-11 Sunplus Technology Co Ltd Searial transmission controller, searial transmission decoder and searial transmission method thereof
KR100881393B1 (en) 2006-12-28 2009-02-02 주식회사 하이닉스반도체 Semiconductor memory device with mirror function
US7739441B1 (en) * 2007-04-30 2010-06-15 Hewlett-Packard Development Company, L.P. Communicating between a native fully buffered dual in-line memory module protocol and a double data rate synchronous dynamic random access memory protocol
US7711887B1 (en) * 2007-04-30 2010-05-04 Hewlett-Packard Development Company, L.P. Employing a native fully buffered dual in-line memory module protocol to write parallel protocol memory module channels
US7996602B1 (en) * 2007-04-30 2011-08-09 Hewlett-Packard Development Company, L.P. Parallel memory device rank selection
TWI338839B (en) * 2007-06-27 2011-03-11 Etron Technology Inc Memory control system and memory data fetching method
US7633785B2 (en) * 2007-07-10 2009-12-15 Samsung Electronics Co., Ltd. Semiconductor memory device and method of generating chip enable signal thereof
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US20100005218A1 (en) 2008-07-01 2010-01-07 International Business Machines Corporation Enhanced cascade interconnected memory system
US7894230B2 (en) * 2009-02-24 2011-02-22 Mosaid Technologies Incorporated Stacked semiconductor devices including a master device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838165A (en) * 1996-08-21 1998-11-17 Chatter; Mukesh High performance self modifying on-the-fly alterable logic FPGA, architecture and method
US6338108B1 (en) * 1997-04-15 2002-01-08 Nec Corporation Coprocessor-integrated packet-type memory LSI, packet-type memory/coprocessor bus, and control method thereof
US6510097B2 (en) * 2001-02-15 2003-01-21 Oki Electric Industry Co., Ltd. DRAM interface circuit providing continuous access across row boundaries

Cited By (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012248267A (en) * 2001-03-21 2012-12-13 Micron Technology Inc Memory device and method having data bus with multiple pre-fetch i/o configuration
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US7515453B2 (en) * 2005-06-24 2009-04-07 Metaram, Inc. Integrated memory core and memory interface circuit
US11302371B2 (en) 2005-11-30 2022-04-12 Rambus Inc. Memory systems and methods for dividing physical memory locations into temporal memory locations
US7610417B2 (en) 2005-11-30 2009-10-27 Rambus Inc. Data-width translator coupled between variable-width and fixed-width data ports and supporting multiple data-width configurations
US8078775B2 (en) 2005-11-30 2011-12-13 Rambus Inc. Memory systems and methods for translating memory addresses to temporal addresses in support of varying data widths
US10043560B2 (en) 2005-11-30 2018-08-07 Rambus Inc. Memory systems and methods for dividing physical memory locations into temporal memory locations
US8281055B2 (en) 2005-11-30 2012-10-02 Rambus Inc. Memory systems and methods for dividing physical memory locations into temporal memory locations
US9727458B2 (en) 2006-02-09 2017-08-08 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US9542353B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US9047976B2 (en) 2006-07-31 2015-06-02 Google Inc. Combined signal delay and power saving for use with a plurality of memory circuits
US9818470B2 (en) 2006-12-14 2017-11-14 Rambus Inc. Multi-die memory device
US10607691B2 (en) 2006-12-14 2020-03-31 Rambus Inc. Multi-die memory device
US9082463B2 (en) 2006-12-14 2015-07-14 Rambus Inc. Multi-die memory device
US8233303B2 (en) 2006-12-14 2012-07-31 Rambus Inc. Multi-die memory device
US8737106B2 (en) 2006-12-14 2014-05-27 Rambus Inc. Multi-die memory device
US11195572B2 (en) 2006-12-14 2021-12-07 Rambus Inc. Multi-die memory device
US9324411B2 (en) 2006-12-14 2016-04-26 Rambus Inc. Multi-die memory device
US11657868B2 (en) 2006-12-14 2023-05-23 Rambus Inc. Multi-die memory device
US10885971B2 (en) 2006-12-14 2021-01-05 Rambus Inc. Multi-die memory device
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8631193B2 (en) 2008-02-21 2014-01-14 Google Inc. Emulation of abstracted DIMMS using abstracted DRAMS
US9390783B1 (en) 2009-01-23 2016-07-12 Cypress Semiconductor Corporation Memory devices and systems including cache devices for memory modules
US9836416B2 (en) 2009-01-23 2017-12-05 Cypress Semiconductor Corporation Memory devices and systems including multi-speed access of memory modules
US8572320B1 (en) 2009-01-23 2013-10-29 Cypress Semiconductor Corporation Memory devices and systems including cache devices for memory modules
US8725983B2 (en) 2009-01-23 2014-05-13 Cypress Semiconductor Corporation Memory devices and systems including multi-speed access of memory modules
US9110832B2 (en) 2009-06-03 2015-08-18 Micron Technology, Inc. Object oriented memory in solid state devices
US9343127B1 (en) 2013-01-08 2016-05-17 Qualcomm Incorporated Memory device having an adaptable number of open rows
US9281036B2 (en) 2013-01-08 2016-03-08 Qualcomm Incorporated Memory device having an adaptable number of open rows
CN104903962A (en) * 2013-01-08 2015-09-09 高通股份有限公司 Memory device having an adaptable number of open rows
WO2014110050A1 (en) * 2013-01-08 2014-07-17 Qualcomm Incorporated Memory device having an adaptable number of open rows
US10679722B2 (en) 2016-08-26 2020-06-09 Sandisk Technologies Llc Storage system with several integrated components and method for use therewith
US11211141B2 (en) 2016-08-26 2021-12-28 Sandisk Technologies Llc Storage system with multiple components and method for use therewith
US11610642B2 (en) 2016-08-26 2023-03-21 Sandisk Technologies Llc Storage system with multiple components and method for use therewith
CN108155174A (en) * 2016-12-06 2018-06-12 三星电子株式会社 Semiconductor storage unit including stacked chips and with its memory module
CN108155174B (en) * 2016-12-06 2021-06-08 三星电子株式会社 Semiconductor memory device including stacked chips and memory module having the same
CN108804315A (en) * 2018-05-23 2018-11-13 北京五八信息技术有限公司 Applied to the test method of dynamic development, device, electronic equipment and storage medium

Also Published As

Publication number Publication date
GB2441726A (en) 2008-03-12
KR101377305B1 (en) 2014-03-25
US20070050530A1 (en) 2007-03-01
US7990746B2 (en) 2011-08-02
US20110310686A1 (en) 2011-12-22
US20070014168A1 (en) 2007-01-18
KR20080039877A (en) 2008-05-07
WO2007002324A3 (en) 2007-04-12
GB2441726B (en) 2010-08-11
US20090290442A1 (en) 2009-11-26
KR101463375B1 (en) 2014-11-18
KR20140037283A (en) 2014-03-26
KR20130033456A (en) 2013-04-03
US7515453B2 (en) 2009-04-07
KR101318116B1 (en) 2013-11-14
JP2008544437A (en) 2008-12-04
GB0800734D0 (en) 2008-02-20
DE112006001810T5 (en) 2008-08-21

Similar Documents

Publication Publication Date Title
US7515453B2 (en) Integrated memory core and memory interface circuit
US7466603B2 (en) Memory accessing circuit system
EP3540736B1 (en) Multi-die memory device
US20230418471A1 (en) Apparatuses and methods for configurable memory array bank architectures
CN101055768B (en) Semiconductor memory device
KR100695436B1 (en) Multi port memory device with serial input/output interface and method for controlling operation mode thereof
EP1849161B1 (en) Register read for volatile memory
JP5052842B2 (en) Memory system and method having point-to-point links
US20110205828A1 (en) Semiconductor memory with memory cell portions having different access speeds
US5802005A (en) Four bit pre-fetch sDRAM column select architecture
CN115705169A (en) Apparatus, system, and method for input/output mapping
KR100499844B1 (en) Dram architecture with aligned data storage and bond pads
US11842762B2 (en) System application of DRAM component with cache mode
US20140268978A1 (en) Semiconductor memory device having asymmetric access time
KR100520597B1 (en) Semiconductor memory device capable of changing an address space thereof
US20210200680A1 (en) Cache dynamic random access memory
US7434018B2 (en) Memory system
US7110321B1 (en) Multi-bank integrated circuit memory devices having high-speed memory access timing
CN114429772A (en) Column select architecture with edge pad optimization
US20080098152A1 (en) Method and apparatus for configuring a memory device
WO2022076652A1 (en) Systems for high speed transactions with nonvolatile memory on a double data rate memory bus
Itoh et al. High-performance subsystem memories
US20050102476A1 (en) Random access memory with optional column address strobe latency of one

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
ENP Entry into the national phase

Ref document number: 2008518401

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 1120060018108

Country of ref document: DE

ENP Entry into the national phase

Ref document number: 0800734

Country of ref document: GB

Kind code of ref document: A

Free format text: PCT FILING DATE = 20060623

WWE Wipo information: entry into national phase

Ref document number: 0800734.6

Country of ref document: GB

WWE Wipo information: entry into national phase

Ref document number: 1020087001812

Country of ref document: KR

122 Ep: pct application non-entry in european phase

Ref document number: 06773794

Country of ref document: EP

Kind code of ref document: A2

RET De translation (de og part 6b)

Ref document number: 112006001810

Country of ref document: DE

Date of ref document: 20080821

Kind code of ref document: P

WWE Wipo information: entry into national phase

Ref document number: 1020137004006

Country of ref document: KR