WO2006135420A2 - Method for simultaneous fabrication of a nanocrystal and non-nanocrystal device - Google Patents

Method for simultaneous fabrication of a nanocrystal and non-nanocrystal device Download PDF

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Publication number
WO2006135420A2
WO2006135420A2 PCT/US2005/033208 US2005033208W WO2006135420A2 WO 2006135420 A2 WO2006135420 A2 WO 2006135420A2 US 2005033208 W US2005033208 W US 2005033208W WO 2006135420 A2 WO2006135420 A2 WO 2006135420A2
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Prior art keywords
substrate
fabricated
nanocrystal
layer
semiconductor devices
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PCT/US2005/033208
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French (fr)
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WO2006135420A3 (en
Inventor
Bohumil Lojek
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Atmel Corporation
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Publication of WO2006135420A3 publication Critical patent/WO2006135420A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/70—Nanostructure
    • Y10S977/701—Integrated with dissimilar structures on a common substrate

Definitions

  • This invention relates to semiconductor device ' fabrication, in particular, simultaneous fabrication of nanocrystal and non-nanocrystal devices .
  • Nanocrystals are known to effectively store small amounts of electric charge in microscopic metal or semiconductor particles involving only a few atoms. Nanocrystal devices may be exceedingly small since the charge storage structures have nanometer size.
  • Fabrication of nanocrystal devices usually requires that the thermal temperature of processing or annealing steps be as low as possible since high temperatures may cause increased dopant diffusion that adversely affects the performance of the fabricated device. Therefore, it would be advantageous to provide a fabrication flow for simultaneous fabrication of nanocrystal devices and non-nanocrystal devices where the subsequent thermal treatment will not alter properties of nanocrystals .
  • a method of simultaneously fabricating two semiconductor devices comprises forming a first thermal oxide layer for at least two semiconductor devices being fabricated on at least two portions of a surface of a substrate, forming a nanocrystal layer over the oxide layer of the at least two semiconductor devices being fabricated, removing with an etching process the nanocrystal layer from the at least one portion of the substrate corresponding to the at least one non-nanocrystal device being fabricated, forming a polycrystalline gate for each of the at least two semiconductor devices being fabricated, the exposed nanocrystals not covered by the gate on the at least one portion of the substrate associated with the at least one nanocrystal device consumed by a thermal oxidation process, the thermal oxidation process producing a second thermal oxide, a remaining plurality of nanocrystals forming a floating gate, providing doping in selected areas of the substrate to form source and drain regions
  • method for simultaneously fabricating two semiconductor devices comprises forming a first thermal oxide layer for at least two semiconductor devices being fabricated on at least two portions of a surface of a substrate, forming a nanocrystal layer over the oxide layer of the at least two semiconductor devices being fabricated, masking at least one portion of the substrate associated with the at least one nanocrystal device being fabricated to protect underlying layers while performing fabrication processes for the at least non-nanocrystal device being fabricated, said fabrication processes including removing with an etching process the nanocrystal layer from the at least one portion of the substrate corresponding to the at least one non-nanocrystal device being fabricated, forming a polycrystalline gate for each of the at least two semiconductor devices being fabricated, the exposed nanocrystals not covered by the gate on the at least one portion of the substrate associated with the at least one nanocrystal device consumed by a thermal oxide layer for at least two semiconductor devices being fabricated on at least two portions of a surface of a substrate, forming a nanocrystal layer over the oxide layer of
  • Figs. Ia and Ib are cross sections of a semiconductor wafer at a starting point of an embodiment of the invention.
  • Figs. 2a - 22a are cross sections of semiconductor peripheral device structures at selected processing stages according to an embodiment of the invention.
  • Figs. 2b - 22b are cross sections of semiconductor memory device structures at selected processing stages according to an embodiment of the invention.
  • a process for simultaneously fabricating a semiconductor device, such as a memory cell, containing a nanocrystal layer as well as a peripheral semiconductor device (in one embodiment, forming CMOS transistor) that does not contain a nanocyrstal layer is described below.
  • a semiconductor device such as a memory cell
  • a peripheral semiconductor device in one embodiment, forming CMOS transistor
  • exemplary process steps provide detail for fabrication of a peripheral device that does not contain nanocrystals
  • Figs. lb-22b provide detail for an exemplary fabrication of a memory cell containing nanocyrstals .
  • a semicondcutor substrate for example, p-type silicon
  • a peripheral semiconductor device without nanocyrstals Fig. Ia
  • a memory cell with nanocrystals Fig. Ib
  • both a portion 10 of the substrate 24 corresponding to the to-be fabricated peripheral device and a portion 12 of the substrate 26 corresponding to the memory cell with nanocyrstals are doped in the usual way for formation of a MOS or CMOS EEPROM device.
  • Shallow trench isolation (“STI") regions 14, 54, 56, and 58 are implanted within the relevant portions 24, 26 of the substrate to define the active area of the devices. Other isolation methods may be employed in other embodiments.
  • STI shallow trench isolation
  • Other isolation methods may be employed in other embodiments.
  • CMP chemical mechanical planarization
  • a layer of thermal oxide 16 (such as tunnel or gate oxide) having a target thickness of about 60 A is deposited.
  • oxide surface hydroxylation is performed after the oxide surface is etched to less than 20 A by exposing the oxide to 0.05% hydrofluoric acid for 300 seconds .
  • the nanocrystal layer 18 with nanocrystals approximately 40 A in diameter is then formed.
  • the nanocrystal layer is formed by CVD deposition of an insulating layer such as oxide, nitride, or oxynitride. Silicon atoms may be implanted into this dielectric material . This layer is annealed to further improve properties of silicon nanocrystals . This thermal processing step does not limit the thermal budget of further fabrication processes because other semiconductor devices which are usually compromised by dopant diffusion are not in place. (Other methods of nanocrystal formation known in the art may also be used.)
  • a layer of control dielectric 20 is formed on top of the nanocrystal layer.
  • the layer of control dielectric 20 is formed by the deposition of one layer of oxide, one layer of nitride, and one layer of oxynitride (i.e., an ONO layer), where each of these layers is 40 A thick.
  • a first photoresist layer 22 is formed over the to-be-fabricated memory cell array 12 to protect the underlying layers 16, 18, 20 from fabrication steps carried out on the portion of the substrate 24 corresponding to the to-be-fabricated peripheral semiconductor device without nanocrystals.
  • the mask layer is removed from the portion 24 of the to-be- fabricated peripheral semiconductor device 10 without nanocrystals shown in Fig. 3a.
  • control dielectric and nanocrystal layers are removed from the section 10 of the substrate 24 corresponding to the to-be-fabricated peripheral semiconductor device without nanocrystals.
  • a wet/dry etch removes the control dielectric and a wet etch removes the nanocrystal layer.
  • other processes known to those skilled in the art may be used to remove the dielectric and nanocrystal layers.
  • the photo resistive mask layer is stripped.
  • the underlying layers are cleaned using a - S -
  • the nanocrystal gate should have a targeted thickness of 50 A (the targeted thickness may vary in other embodiments) . (The original thickness of the control dielectric layer 20 will also increase and needs to be accounted for.)
  • a layer of polysilicon 28 is deposited over both portions 10, 12 of the substrate 24, 26.
  • a second layer of photoresist 30 is applied to mask the portion of the substrate 24 corresponding to the to-be-fabricated peripheral semiconductor device 10 and part of the portion 12 of the substrate 26 associated with the to-be- fabricated memory cell, specifically, the cell transistor.
  • Fig. 8b the polysilicon layer 28 not protected by the photoresist layer 30 is etched away by a standard dry etch.
  • Fig. 8a the polysilicon layer 28 is unaffected since it is protected by the second photoresist layer 30.
  • Fig. 9b the portion of the control dielectric layer 20 not protected by the second photoresist layer 30 is removed by a wet (dry) etch or a dry/wet etch. This exposes the underlying nanocrystal layer 18.
  • Fig. 9a the portion 10 of the substrate 24 associated with the to-be-fabricated peripheral semiconductor device is unaffected due to the second photoresist layer 30.
  • a second thermal oxide layer 32 is grown, consuming the exposed nanocrystals .
  • Mechanisms for thermal oxide growth are well understood. About 44% of underlying silicon is consumed to form a thermal silicon dioxide. At standard ambient temperatures (e.g., 68 0 C), thermal oxide will grow to about 1 nm (10 A, known as "native oxide"), consuming about 0.44 nm (4.4 A) of underlying silicon. By elevating a processing temperature, for example, in a rapid thermal processor or diffusion furnace, the exposed nanocrystals are entirely consumed.
  • an Applied Materials ISSG diluted wet oxidation oxide chamber is used with a temperature of about 800°C - 900 0 C for 10-30 seconds. Therefore, the second thermal oxide 32 is comprised of consumed nanocrystals. In Figs. 12a and 12b, an oxide etch completely removes the layer of oxide from the surface of areas where the source and drain will be formed.
  • a third layer of photoresist 60 is applied to mask the area 10 of the substrate 24 corresponding to the peripheral semiconductor device to be manufactured.
  • the third layer of photoresist 60 is applied over the entire area 12 of the substrate 24 associated with the to-be-manufactured memory cell.
  • the gate polysilicon 28 and tunnel oxide 16 are etched away except for the gate region protected by the photoresist 60.
  • the etching process has no effect due to the presence of the third photoresist layer 60.
  • the third photoresist layer 60 is stripped.
  • a temporary oxide spacer 34 is deposited in Figs. 16a and 16b (by CVD or PECVD) .
  • the temporary spacer is removed by a dry etch process, leaving only a portion of the oxide spacer 34 on the sides of the peripheral device 10 and memory cell 12 being fabricated.
  • the source and drain regions 42, 36, 44, and 46 of the to-be-fabricated peripheral devices 10 and the to-be-fabricated memory cells 12, respectively, are formed by ion implantation (or diffusion in other embodiments) . If dopants are implanted, a thermal annealing process is performed after implantation, in one embodiment, at 900 0 C - 1100°C for typically 10 sec - several minutes. The temporary spacers are removed by a standard wet etch process in Figs. 19a and 19b.
  • source/drain extensions 48, 38, 50, 52 are implanted.
  • a nitride layer 40 is deposited.
  • the nitride layer 40 is dry etched using a standard dry etch such that spacers 40 are formed on the sides of the gate stacks of both the peripheral device and memory cell structures 10, 12.

Abstract

A method of simultaneously fabricating at least two semiconductor devices, at least one of which is an nanocrystal memory and at least one of which is a non-nanocrystal semiconductor device. A nanocrystal layer (18) is formed over an oxide layer (16) of the at least two semiconductor devices being fabricated. The nanocrystal layer (18) is removed from at least one portion o the substrate (10) corresponding to the at least one non-nanocrystal device being fabricated. A polycrystalline gate is formed for each of the semiconductor devices being fabricated. Doping is provided to provide the source and drain regions (42, 36, 44, 46) for each of the semiconductor devices being fabricated. The substrate (10, 12) is thermally treated after the doping. The thermal budget of the fabrication process is not limited by this thermal treatment.

Description

Description
METHOD FOR SIMULTANEOUS FABRICATION OF A NANOCRYSTAL AND NON-NANOCRYSTAL DEVICE
FIELD OF THE INVENTION
This invention relates to semiconductor device 'fabrication, in particular, simultaneous fabrication of nanocrystal and non-nanocrystal devices .
BACKGROUND OF THE INVENTION
Nanocrystals are known to effectively store small amounts of electric charge in microscopic metal or semiconductor particles involving only a few atoms. Nanocrystal devices may be exceedingly small since the charge storage structures have nanometer size.
Fabrication of nanocrystal devices usually requires that the thermal temperature of processing or annealing steps be as low as possible since high temperatures may cause increased dopant diffusion that adversely affects the performance of the fabricated device. Therefore, it would be advantageous to provide a fabrication flow for simultaneous fabrication of nanocrystal devices and non-nanocrystal devices where the subsequent thermal treatment will not alter properties of nanocrystals .
SUMMARY OF THE INVENTION
In one embodiment of the invention, a method of simultaneously fabricating two semiconductor devices, at least one of which is a nanocrystal device and at least one of which is a non-nanocrystal device, comprises forming a first thermal oxide layer for at least two semiconductor devices being fabricated on at least two portions of a surface of a substrate, forming a nanocrystal layer over the oxide layer of the at least two semiconductor devices being fabricated, removing with an etching process the nanocrystal layer from the at least one portion of the substrate corresponding to the at least one non-nanocrystal device being fabricated, forming a polycrystalline gate for each of the at least two semiconductor devices being fabricated, the exposed nanocrystals not covered by the gate on the at least one portion of the substrate associated with the at least one nanocrystal device consumed by a thermal oxidation process, the thermal oxidation process producing a second thermal oxide, a remaining plurality of nanocrystals forming a floating gate, providing doping in selected areas of the substrate to form source and drain regions for the at least two semiconductor devices being fabricated, thermally treating the substrate following the doping, the thermal treatment not limiting a thermal budget of the fabrication process. A CMOS transistor may be formed in this fashion in one embodiment of the invention.
In another embodiment of the invention, method for simultaneously fabricating two semiconductor devices, at least one of which is a nanocrystal device and at least one of which is a non-nanocrystal device, comprises forming a first thermal oxide layer for at least two semiconductor devices being fabricated on at least two portions of a surface of a substrate, forming a nanocrystal layer over the oxide layer of the at least two semiconductor devices being fabricated, masking at least one portion of the substrate associated with the at least one nanocrystal device being fabricated to protect underlying layers while performing fabrication processes for the at least non-nanocrystal device being fabricated, said fabrication processes including removing with an etching process the nanocrystal layer from the at least one portion of the substrate corresponding to the at least one non-nanocrystal device being fabricated, forming a polycrystalline gate for each of the at least two semiconductor devices being fabricated, the exposed nanocrystals not covered by the gate on the at least one portion of the substrate associated with the at least one nanocrystal device consumed by a thermal oxidation process, the thermal oxidation process producing a second thermal oxide, a remaining plurality of nanocrystals forming a floating gate, providing doping in selected areas of the substrate to form source and drain regions for the at least two semiconductor devices being fabricated, and thermally treating the substrate following the doping, the thermal treatment not limiting a thermal budget of the fabrication process. A CMOS transistor may be formed in one embodiment of the invention.
BRIEF DECRIPTION OF THE DRAWINGS
Figs. Ia and Ib are cross sections of a semiconductor wafer at a starting point of an embodiment of the invention.
Figs. 2a - 22a are cross sections of semiconductor peripheral device structures at selected processing stages according to an embodiment of the invention.
Figs. 2b - 22b are cross sections of semiconductor memory device structures at selected processing stages according to an embodiment of the invention.
BEST MODE FOR CARRYING OUT THE INVENTION
A process for simultaneously fabricating a semiconductor device, such as a memory cell, containing a nanocrystal layer as well as a peripheral semiconductor device (in one embodiment, forming CMOS transistor) that does not contain a nanocyrstal layer is described below. With reference to Figs. la-22a, exemplary process steps provide detail for fabrication of a peripheral device that does not contain nanocrystals while Figs. lb-22b provide detail for an exemplary fabrication of a memory cell containing nanocyrstals .
In Figs. Ia and Ib, a semicondcutor substrate, for example, p-type silicon, is provided. Assuming two semiconductor devices, a peripheral semiconductor device without nanocyrstals (Fig. Ia) and a memory cell with nanocrystals (Fig. Ib) are to be fabricated simultaneously on the substrate, both a portion 10 of the substrate 24 corresponding to the to-be fabricated peripheral device and a portion 12 of the substrate 26 corresponding to the memory cell with nanocyrstals are doped in the usual way for formation of a MOS or CMOS EEPROM device. Shallow trench isolation ("STI") regions 14, 54, 56, and 58, well known in the art, are implanted within the relevant portions 24, 26 of the substrate to define the active area of the devices. Other isolation methods may be employed in other embodiments. Before layers are formed on the substrate, the surface of the substrate is prepared in the usual way by, for example, a chemical mechanical planarization ("CMP") polishing.
In Figs. 2a and 2b, a layer of thermal oxide 16 (such as tunnel or gate oxide) having a target thickness of about 60 A is deposited. Before a nanocrystal layer is deposited, oxide surface hydroxylation is performed after the oxide surface is etched to less than 20 A by exposing the oxide to 0.05% hydrofluoric acid for 300 seconds .
The nanocrystal layer 18 with nanocrystals approximately 40 A in diameter is then formed. In one embodiment, the nanocrystal layer is formed by CVD deposition of an insulating layer such as oxide, nitride, or oxynitride. Silicon atoms may be implanted into this dielectric material . This layer is annealed to further improve properties of silicon nanocrystals . This thermal processing step does not limit the thermal budget of further fabrication processes because other semiconductor devices which are usually compromised by dopant diffusion are not in place. (Other methods of nanocrystal formation known in the art may also be used.)
After the nanocrystal layer 18 has been formed, a layer of control dielectric 20 is formed on top of the nanocrystal layer. In one embodiment, the layer of control dielectric 20 is formed by the deposition of one layer of oxide, one layer of nitride, and one layer of oxynitride (i.e., an ONO layer), where each of these layers is 40 A thick.
In Fig. 3b, a first photoresist layer 22 is formed over the to-be-fabricated memory cell array 12 to protect the underlying layers 16, 18, 20 from fabrication steps carried out on the portion of the substrate 24 corresponding to the to-be-fabricated peripheral semiconductor device without nanocrystals. The mask layer is removed from the portion 24 of the to-be- fabricated peripheral semiconductor device 10 without nanocrystals shown in Fig. 3a.
In Fig. 4a, the control dielectric and nanocrystal layers are removed from the section 10 of the substrate 24 corresponding to the to-be-fabricated peripheral semiconductor device without nanocrystals. For example, a wet/dry etch removes the control dielectric and a wet etch removes the nanocrystal layer. In other embodiments, other processes known to those skilled in the art may be used to remove the dielectric and nanocrystal layers.
In Fig. 5b, the photo resistive mask layer is stripped. The underlying layers are cleaned using a - S -
known cleaning process such as SCI or SC2 and the gate oxide shown in Figs. 5A and 5b is subject to a standard furnace treatment. After this step, the nanocrystal gate should have a targeted thickness of 50 A (the targeted thickness may vary in other embodiments) . (The original thickness of the control dielectric layer 20 will also increase and needs to be accounted for.)
In Figs. 6a and 6b, a layer of polysilicon 28 is deposited over both portions 10, 12 of the substrate 24, 26. In Figs. 7a and 7b, a second layer of photoresist 30 is applied to mask the portion of the substrate 24 corresponding to the to-be-fabricated peripheral semiconductor device 10 and part of the portion 12 of the substrate 26 associated with the to-be- fabricated memory cell, specifically, the cell transistor.
In Fig. 8b, the polysilicon layer 28 not protected by the photoresist layer 30 is etched away by a standard dry etch. In Fig. 8a, the polysilicon layer 28 is unaffected since it is protected by the second photoresist layer 30.
In Fig. 9b, the portion of the control dielectric layer 20 not protected by the second photoresist layer 30 is removed by a wet (dry) etch or a dry/wet etch. This exposes the underlying nanocrystal layer 18. In Fig. 9a, the portion 10 of the substrate 24 associated with the to-be-fabricated peripheral semiconductor device is unaffected due to the second photoresist layer 30.
In Figs. 10a and 10b, the second photoresist layer is removed. In Fig. lib, a second thermal oxide layer 32 is grown, consuming the exposed nanocrystals . Mechanisms for thermal oxide growth are well understood. About 44% of underlying silicon is consumed to form a thermal silicon dioxide. At standard ambient temperatures (e.g., 680C), thermal oxide will grow to about 1 nm (10 A, known as "native oxide"), consuming about 0.44 nm (4.4 A) of underlying silicon. By elevating a processing temperature, for example, in a rapid thermal processor or diffusion furnace, the exposed nanocrystals are entirely consumed. In one specific embodiment, an Applied Materials ISSG diluted wet oxidation oxide chamber is used with a temperature of about 800°C - 9000C for 10-30 seconds. Therefore, the second thermal oxide 32 is comprised of consumed nanocrystals. In Figs. 12a and 12b, an oxide etch completely removes the layer of oxide from the surface of areas where the source and drain will be formed.
In Fig. 13a, a third layer of photoresist 60 is applied to mask the area 10 of the substrate 24 corresponding to the peripheral semiconductor device to be manufactured. In Fig. 13b, the third layer of photoresist 60 is applied over the entire area 12 of the substrate 24 associated with the to-be-manufactured memory cell. In Fig. 14a, the gate polysilicon 28 and tunnel oxide 16 are etched away except for the gate region protected by the photoresist 60. In Fig. 14b, the etching process has no effect due to the presence of the third photoresist layer 60. In Figs. 15a and 15b, the third photoresist layer 60 is stripped.
A temporary oxide spacer 34 is deposited in Figs. 16a and 16b (by CVD or PECVD) . In Figs. 17a and 17b, the temporary spacer is removed by a dry etch process, leaving only a portion of the oxide spacer 34 on the sides of the peripheral device 10 and memory cell 12 being fabricated.
In Figs. 18a and 18b, the source and drain regions 42, 36, 44, and 46 of the to-be-fabricated peripheral devices 10 and the to-be-fabricated memory cells 12, respectively, are formed by ion implantation (or diffusion in other embodiments) . If dopants are implanted, a thermal annealing process is performed after implantation, in one embodiment, at 9000C - 1100°C for typically 10 sec - several minutes. The temporary spacers are removed by a standard wet etch process in Figs. 19a and 19b.
In Figs. 20a and 20b, source/drain extensions 48, 38, 50, 52 (so called LDD) are implanted.
In Figs. 21a and 21b, a nitride layer 40 is deposited. In Figs. 22a and 22b, the nitride layer 40 is dry etched using a standard dry etch such that spacers 40 are formed on the sides of the gate stacks of both the peripheral device and memory cell structures 10, 12.
In the foregoing specification, the present invention has been described with reference to specific embodiments. It will, however, be evident to a skilled artisan that various changes and modifications can be made to these embodiments without departing from the broader spirit and scope of the present invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

Claims
1. A method for simultaneously fabricating two semiconductor devices, at least one of which is a nanocrystal device and at least one of which is a non- nanocrystal device, comprising: a) forming a first thermal oxide layer for at least two semiconductor devices being fabricated on at least two portions of a surface of a substrate; b) forming a nanocrystal layer over the oxide layer of the at least two semiconductor devices being fabricated; c) removing with an etching process the nanocrystal layer from the at least one portion of the substrate corresponding to the at least one non- nanocrystal device being fabricated; d) forming a polycrystalline gate for each of the at least two semiconductor devices being fabricated, exposed nanocrystals not covered by the gate on the at least one portion of the substrate associated with the at least one nanocrystal device consumed by a thermal oxidation process, the thermal oxidation process producing a second thermal oxide, a remaining plurality of nanocrystals forming a floating gate; e) providing doping in selected areas of the substrate to form source and drain regions for the at least two semiconductor devices being fabricated; and f) thermally treating the substrate following the doping, the thermal treatment not limiting a thermal budget of the fabrication process.
2. The method of claim 1 further comprising masking at least one portion of the substrate associated with the at least one nanocrystal device being fabricated to protect underlying layers while performing fabrication processes for the at least non-nanocrystal device being fabricated.
3. The method of claim 1 further comprising masking at least one portion of the substrate associated with the at least one non-nanocrystal device being fabricated to protect underlying layers while performing fabrication processes for the at least one nanocrystal device being fabricated.
4. The method of claim 1 further comprising forming a control dielectric layer on top of the nanocrystal layer.
5. The method of claim 4 further comprising removing the control dielectric layer from the at least one non- nanocrystal device being fabricated with an etching process .
6. The method of claim 4 further comprising etching portions of the control layer dielectric that are not covered by the polycrystalline gate until a plurality of nanocrystals not located under the polycrystalline gate is exposed.
7. The method of claim 1 further comprising forming oxide spacers for the semiconductor devices being fabricated on the substrate.
8. The method of claim 1 further comprising removing the oxide spacers for the semiconductor devices being fabricated on the semiconductor substrate .
9. The method of claim 1 further comprising forming nitride spacers for the semiconductor devices being fabricated on the semiconductor substrate.
10. The method of claim 1 wherein a CMOS transistor is formed.
11. The method of claim 1 wherein the substrate is a silicon wafer.
12. The method of claim 1 wherein the polycrystalline gate is comprised of polycrystalline silicon.
13. The method of claim 4 wherein the dielectric layer is essentially an ONO layer.
14. A semiconductor substrate having at least two semiconductor devices, at least one of which is a nanocrystal device and at least one of which is a non- nanocrystal device, fabricated by a process comprising:
' a) forming a first thermal oxide layer for at least two semiconductor devices being fabricated on at least two portions of a surface of the substrate; b) forming a nanocrystal layer over the oxide layer of the at least two semiconductor devices being fabricated; c) removing with an etching process the nanocrystal layer from the at least one portion of the substrate corresponding to the at least one non- nanocrystal device being fabricated; d) forming a polycrystalline gate for each of the at least two semiconductor devices being fabricated, the exposed nanocrystals not covered by the gate on the at least one portion of the substrate associated with the at least one nanocrystal device consumed by a thermal oxidation process, the thermal oxidation process producing a second thermal oxide, a remaining plurality of nanocrystals forming a floating gate; e) providing doping in selected areas of the substrate to form source and drain regions for the at least two semiconductor devices being fabricated; and f) thermally treating the substrate following the doping, the thermal treatment not limiting a thermal budget of the fabrication process.
15. The substrate of claim 14 further comprising masking at least one portion of the substrate associated with the at least one nanocrystal device being fabricated to protect underlying layers while performing fabrication processes for the at least non-nanocrystal device being fabricated.
16. The substrate of claim 14 further comprising masking at least one portion of the substrate associated with the at least one non-nanocrystal device being fabricated to protect underlying layers while performing fabrication processes for the at least one nanocrystal device being fabricated.
17. The substrate of claim 14 further comprising forming a control dielectric layer on top of the nanocrystal layer.
18. The substrate of claim 17 further comprising removing the control dielectric layer from the at least one non-nanocrystal device being fabricated with an etching process .
19. The substrate of claim 17 further comprising etching portions of the control layer dielectric that are not covered by the polycrystalline gate until a plurality of nanocrystals not located under the polycrystalline gate is exposed.
20. The substrate of claim 14 further comprising forming oxide spacers for the semiconductor devices being fabricated on the substrate.
21. The substrate of claim 14 further comprising removing the oxide spacers for the semiconductor devices being fabricated on the semiconductor substrate.
22. The substrate of claim 14 further comprising forming nitride spacers for the semiconductor devices being fabricated on the semiconductor substrate.
23. The substrate of claim 14 wherein the at least two devices form a CMOS transistor.
24. The substrate of claim 14 wherein the substrate is a silicon wafer.
25. The substrate of claim 14 wherein the polycrystalline gate is comprised of polycrystalline silicon.
26. The substrate of claim 17 wherein the dielectric layer is essentially an ONO layer.
PCT/US2005/033208 2004-10-13 2005-09-15 Method for simultaneous fabrication of a nanocrystal and non-nanocrystal device WO2006135420A2 (en)

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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7132329B1 (en) 2005-06-29 2006-11-07 Freescale Semiconductor, Inc. Source side injection storage device with spacer gates and method therefor
US7157345B1 (en) * 2005-06-29 2007-01-02 Freescale Semiconductor, Inc. Source side injection storage device and method therefor
US7618492B2 (en) * 2005-08-09 2009-11-17 Infineon Technologies Ag Methods of forming nanocrystals
US8686490B2 (en) * 2006-12-20 2014-04-01 Sandisk Corporation Electron blocking layers for electronic devices
US20080150004A1 (en) * 2006-12-20 2008-06-26 Nanosys, Inc. Electron Blocking Layers for Electronic Devices
US20080150003A1 (en) * 2006-12-20 2008-06-26 Jian Chen Electron blocking layers for electronic devices
US20080150009A1 (en) * 2006-12-20 2008-06-26 Nanosys, Inc. Electron Blocking Layers for Electronic Devices
CN111627810B (en) * 2020-06-05 2022-10-11 合肥晶合集成电路股份有限公司 Semiconductor structure and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030003660A1 (en) * 2001-05-29 2003-01-02 Ching-Hsiang Hsu Structure of an embedded channel write/erase flash memory cell and fabricating method thereof
US6656792B2 (en) * 2001-10-19 2003-12-02 Chartered Semiconductor Manufacturing Ltd Nanocrystal flash memory device and manufacturing method therefor
US20040004246A1 (en) * 2002-07-02 2004-01-08 Fujitsu Limited Semiconductor integrated circuit apparatus and fabrication method thereof
US6690059B1 (en) * 2002-08-22 2004-02-10 Atmel Corporation Nanocrystal electron device
US20040070020A1 (en) * 1999-12-17 2004-04-15 Ichiro Fujiwara Nonvolatile semiconductor memory device and method for operating the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4963505A (en) * 1987-10-27 1990-10-16 Nippondenso Co., Ltd. Semiconductor device and method of manufacturing same
US6190949B1 (en) * 1996-05-22 2001-02-20 Sony Corporation Silicon thin film, group of silicon single crystal grains and formation process thereof, and semiconductor device, flash memory cell and fabrication process thereof
US5994164A (en) * 1997-03-18 1999-11-30 The Penn State Research Foundation Nanostructure tailoring of material properties using controlled crystallization
US6232643B1 (en) * 1997-11-13 2001-05-15 Micron Technology, Inc. Memory using insulator traps
US6444512B1 (en) * 2000-06-12 2002-09-03 Motorola, Inc. Dual metal gate transistors for CMOS process
US6531731B2 (en) 2001-06-15 2003-03-11 Motorola, Inc. Integration of two memory types on the same integrated circuit
US6897151B2 (en) * 2002-11-08 2005-05-24 Wayne State University Methods of filling a feature on a substrate with copper nanocrystals
US20050258470A1 (en) * 2004-05-20 2005-11-24 Bohumil Lojek Gate stack of nanocrystal memory and method for forming same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040070020A1 (en) * 1999-12-17 2004-04-15 Ichiro Fujiwara Nonvolatile semiconductor memory device and method for operating the same
US20030003660A1 (en) * 2001-05-29 2003-01-02 Ching-Hsiang Hsu Structure of an embedded channel write/erase flash memory cell and fabricating method thereof
US6656792B2 (en) * 2001-10-19 2003-12-02 Chartered Semiconductor Manufacturing Ltd Nanocrystal flash memory device and manufacturing method therefor
US20040004246A1 (en) * 2002-07-02 2004-01-08 Fujitsu Limited Semiconductor integrated circuit apparatus and fabrication method thereof
US6690059B1 (en) * 2002-08-22 2004-02-10 Atmel Corporation Nanocrystal electron device

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