WO2006131776A1 - Leadframe, semiconductor package and methods of producing the same - Google Patents

Leadframe, semiconductor package and methods of producing the same Download PDF

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Publication number
WO2006131776A1
WO2006131776A1 PCT/IB2005/001628 IB2005001628W WO2006131776A1 WO 2006131776 A1 WO2006131776 A1 WO 2006131776A1 IB 2005001628 W IB2005001628 W IB 2005001628W WO 2006131776 A1 WO2006131776 A1 WO 2006131776A1
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WO
WIPO (PCT)
Prior art keywords
leadframe
die pad
openings
leadfingers
semiconductor chip
Prior art date
Application number
PCT/IB2005/001628
Other languages
French (fr)
Inventor
Tian Siang Yip
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Priority to PCT/IB2005/001628 priority Critical patent/WO2006131776A1/en
Publication of WO2006131776A1 publication Critical patent/WO2006131776A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the invention relates to a leadframe, a semiconductor package including the leadframe and to methods of producing a leadframe and a semiconductor package.
  • Encapsulated or molded leadframe-based semiconductor packages suffer from reliability problems due to the formation of cracks in the package. Cracks are formed due to the difference in coefficient of thermal expansion (CTE) between the materials of the semiconductor chip, the die pad and the mold com- pound. As the materials expand and contract due to varying temperature, the mis-match in the coefficients of thermal expansion results in warping or cambering of the die pad. This causes cracks to form, typically, at the interface between the die pad and the mold material and the interface between the die pad and the semiconductor chip. The cracks can lead to de- lamination, moisture penetration and failure of the package. The reliability of leadframe-based semiconductor packages is, therefore, limited.
  • CTE coefficient of thermal expansion
  • the invention provides a leadframe which comprises a die pad and a plurality of leadfingers.
  • the die pad is positioned in approximately the lateral centre of the leadframe and the plu- rality of leadfingers are arranged laterally adjacent the die pad.
  • Each leadfinger has an inner portion which will be located inside the plastic housing material of the semiconductor package and an outer portion which will be exposed from the plastic housing. The outer portion will provide the external contacts of the semiconductor package.
  • the die pad comprises a mesh.
  • the mesh comprises a plurality of interconnected fibres which provide a plurality of through-openings or apertures which extend from the upper surface to the lower surface of the die pad.
  • a die pad comprising a mesh has the advantage that a flexible die pad is provided in contrast to the die pads comprising a single solid sheet which are relatively rigid.
  • the flexibility of the mesh die pad enables the warping or cambering effects caused, by the expansion and contraction of the die pad due to temperature variations to be counteracted.
  • the interfacial area between the mesh, which comprises the die pad, and the glue and molding compound is increased.
  • the interconnected fibres and through-openings provide a highly interlocked system between the die pad and the mold compound. This improves the mechanical anchoring or inter-gripping effect between the die pad and the mold compound and the glue. This reduces the risk of delamination at the interfaces between the die pad and the glue and the die pad and the mold compound.
  • the reliability of a semiconductor package including a leadframe with a mesh die pad is, therefore, improved.
  • a semiconductor chip is typically attached to the upper surface of the die pad in the assembly of the semiconductor package by a layer of glue.
  • Each of the plurality of through- openings preferably, has lateral dimensions which are sufficiently small that the effect of surface tension prohibits glue from flowing through the through-openings . Therefore, the problem of mixing of the glue and mold compound is avoided.
  • the optimum lateral dimen- sions of the through-openings provided by the plurality of interconnected fibres can be, therefore, simply determined by routine experimentation for a particular glue so that the effect of surface tension prohibits the glue from flowing through the through-openings and onto the rear surface of the die pad.
  • the semiconductor package typically also includes mold material or compound which encapsulates the semiconductor chip and die pad and provides the plastic package housing of the semi- conductor package.
  • Each of the plurality of through-openings preferably, has lateral dimensions sufficiently large that the mold compound is able to flow through the through-openings . This ensures that the formation of the air bubbles with in the mold compound which comprises the plastic housing of the semi- conductor package is avoided.
  • the mold compound preferably, comprises an epoxy resin and may further comprise filler particles .
  • the lateral dimensions of the plurality of through-openings are simply and easy determined by routine experimentation for a particular mold compound with particular properties so that the mold compound is able to flow through the through-openings and cover both the upper and lower surfaces of the die pad.
  • the lateral dimensions of each of the plurality of through-openings are chosen so that the lateral dimensions are sufficiently small that the effect of surface tension prohibits glue from flowing through the through holes and that each of the plurality of through-openings is sufficiently large that the mold compound is able to flow through the through-openings .
  • the plurality of interconnected fibres preferably, lies in a single plane.
  • This arrangement of the mesh has the advantage that the die pad is simply manufactured by using an etching or stamping method to form a plurality of through-openings which stretch from the upper surface to the lower surface of the die pad.
  • the plurality of interconnected fibres preferably, has a regular grid array arrangement. More preferably, the plurality of interconnected fibres has a square or rectangular grid arrangement or a rhomboid grid arrangement or a diamond grid arrangement .
  • Regular grid arrangements have the advantage that the surface area of the fibres is increased and a homogenous structure is provided which increases the homogeneity of the stress distribution. Therefore, the disadvantageous effects of the mismatch in coefficients of thermal expansion are more effectively reduced and the interlocking effect of the fibres within the package is more effectively improved. The reliability of the semiconductor package is, therefore, further in- creased.
  • each of the plurality of through holes has essentially the same lateral dimensions. This further improves the reliability of a package and simplifies the optimisation proc- ess to determine appropriate lateral dimensions for the through-openings .
  • the leadframe can comprise copper or a copper-based alloy or a nickel iron alloy such as alloy 42. These materials are widely used for leadframes for semiconductor packages and, therefore, the cost of the leadframe according to the invention is not increased.
  • the leadframe may also further include at least one die pad lead.
  • the die pad lead may be used for grounding the rear surface of the semiconductor chip as well as the integrated cir- cuit devices in the active surface of the chip.
  • the die pad is laterally essentially square and leadfingers are arranged adjacent to each of the four sides of the die pad.
  • the leadfingers are ar- ranged so that the inner end of each leadfinger points towards a side of the die pad.
  • Each of the inner ends is typically located at essentially the same distance from a side of the die pad. This simplifies the wire bonding process and provides conduction paths of a similar length which improves the per- formance of the package.
  • the die pad is laterally essentially rectangular and has two short sides and two long sides.
  • the leadfingers are arranged adja- cent to each of the two long sides of the die pad.
  • the inner end of each of the plurality of leadfingers points towards, and is positioned at essentially the same distance from, the long sides of the die pad.
  • the invention also relates to a leadframe strip comprising a plurality of leadframes according to one of the embodiment is already described.
  • the leadframe strip includes a plurality of individual component positions, each component position providing a leadframe for a semiconductor package.
  • Each, leadframe is used in the manufacture of a single semiconductor package or electronic component.
  • Each leadframe is mechanically linked to its adjacent neighbour by at least one tie bar so that a strip is formed.
  • the leadframe strip may also include a plurality of locating holes positioned towards the peripheral edges of the strip and, preferably, outside of the portion of the leadframe strip which will be used to manufacture a semiconductor package. The locating holes enable the strip to be handled by automated equipment and provide a means by which the orientation and alignment of the strip can be controlled and adjusted.
  • the plurality of leadframes are, preferably, arranged in at least one row in the leadframe strip.
  • the leadframe strip comprises a long tape including a plurality of leadframes arranged at regular, periodic inter- vals in a single row.
  • the plurality of leadframes are arranged in a leadframe strip in a grid of rows and columns .
  • the invention also relates to semiconductor packages including a leadframe according to one of the embodiments previously described.
  • the semiconductor package further comprises a semiconductor chip with an active surface and a passive surface.
  • the active surface comprises a plurality of integrated circuit devices and a plurality of chip contact pads which provide electrical access to the integrated circuit devices.
  • the passive surface of the semiconductor chip is attached to a region of the die pad by a layer of glue.
  • the semiconductor package also includes a plurality of bond wires which electrically connect the plurality of chip contact pads and the inner portions of the plurality of leadfingers .
  • a contact pad is positioned towards the inner end of the inner portion of each of the plurality of leadfingers and a bond wire is disposed between a chip contact pad and its corresponding contact pad positioned on the leadfinger.
  • the semiconductor package also comprises mold compound which, preferably, comprises an epoxy resin.
  • the mold compound encapsulates at least the inner portions of the plurality of lead- fingers, the active surface of the semiconductor chip and the plurality of bond wires .
  • the regions of the upper surface of the die pad which are not in contact with the glue layer, the through-openings and the rear surface of the die pad are also encapsulated by the mold compound.
  • a semiconductor package according to the invention therefore, includes a leadframe comprising a die pad which comprises a mesh.
  • the mesh comprises a plurality of interconnected fibres which provide a plurality of through-openings .
  • the invention therefore, provides a more reliable semiconductor package as the flexible mesh die pad reduces the risk of delamination at the interfaces between the die pad and the mold compound and the glue and the die pad as the effect of die pad warping due to temperature fluctuation is reduced.
  • the mesh die pad also improves the mechanical interlocking be- tween the die pad and the mold compound and glue as the inter- facial surface area is increased and a finely structured inter-locking anchoring structure is provided. This reduces the risk of crack formation at the interfaces between the die pad and the mold compound and the die pad and the glue.
  • the layer of glue may be located at least partially within at least one of the through-openings which is located in the region of the die pad vertically adjacent the semiconductor chip.
  • the through-opening is located under the semiconductor chip.
  • the effect of the weight of the glue, wetting properties of the glue on the material of the die pad, the effect of surface tension and the speed of hardening or setting influence the degree to which the glue flows into the through-holes .
  • each of the plurality of through-openings are optimised to control the extent to which the glue flows into the through- openings of the mesh so that the effect of surface tensions prohibits the glue from flowing through the through-openings .
  • the mold compound preferably, essentially fills the through- openings which are located in at least one region of the die pad which is laterally adjacent the semiconductor chip. This provides an improved interlocking of the mold compound with the die pad and avoids the formation of air bubbles within the mold compound. The likelihood of moisture penetration and de- lamination at the interface between the mold compound and the die pad is reduced and the reliability of the package improved.
  • the semiconductor chip is located in the approximate lateral centre of the die pad.
  • the peripheral regions of the die pad lie laterally adjacent the semiconductor chip and are in contact with the mold compound on the upper surface of as well as the lower surface of the die pad.
  • the mold compound preferably, essentially fills the through-openings located in these regions and provides an improved and more uniform interlocking between the mold compound and the die. This uniformity further improves the reliability of the semiconduc- tor package.
  • the invention also relates to methods to produce a leadframe and semiconductor packages.
  • a method to produce a leadframe comprises the step of providing a metal or metal alloy sheet. The sheet is then structure to form at least one leadframe.
  • Each leadframe comprises a die pad and plurality of lead- fingers which are located laterally adjacent the die pad.
  • the die pad comprises a mesh which comprises a plurality of interconnected fibres which provide a plurality of through- openings.
  • the metal sheet is structured by forming a structured resist mask on at least one surface of the sheet. An etching process is then performed to re- move the portions of the sheet which are exposed by a structured resist mask. The remaining portions provide a leadframe having the desired structured. The structured resist mask is then removed to provide a leadframe in which the die pad comprises a mesh.
  • This method has the advantage that the dimensions of the plurality of interconnected fibres and plurality of through- openings which comprise the mesh can be simply and accurately controlled.
  • a finely structured resist mask can be provided by photolithographic techniques. Etching is particularly advantageous when a finely structured mesh is desired. Etching also has the advantage that it is commonly used in the fabrication of leadframes. Therefore, a leadframe according to the invention can be produced by simply changing the pattern of the structured resist mask to provide a mesh die pad. The manufacturing costs of the leadframe of the invention are, therefore, not significantly higher than for leadframes which comprise a die pad of a single solid sheet.
  • leadframe fabrication methods may be modified to provide a leadframe including a mesh die pad according to one of the embodiments of the invention. Typical methods are stamping or milling.
  • the die pad is structured so that each of the plurality of through-openings has lateral dimensions which are sufficiently small that the effect of surface tension prohibits glue from flowing through the through-openings .
  • the die pad is, preferably, structured so that each of the plurality of through-openings has lateral dimensions sufficiently large that the mold compound is able to flow through the through- openings.
  • the through-holes produced may not be of exactly the same dimensions as the corresponding exposed areas in the structured resist mask. Therefore, the dimensions of the structured resist mask may be adjusted so that the through-openings produced have the desired lateral dimensions.
  • the metal sheet is structured to provide a plurality of leadframes, each leadframe being used in the manufacture of a single semiconductor package.
  • the plurality of lead- frames are normally connected to their adjacent neighbours by tie bars so that a mechanically stable strip is provided. This enables automated handling of the leadframe strip and improves the speed, efficiency and reliability of the assembly process.
  • the invention also provides a method to produce a semiconduc- tor package.
  • a leadframe strip comprising at least one leadframe according to one of the embodiment previously described is provided.
  • a semiconductor chip with an active surface and a passive surface is provided.
  • the passive surface of the semiconductor chip is attached to a region of the die pad of the leadframe by a layer of glue.
  • the semiconductor chip includes a plurality of integrated circuit devices and a plurality of chip contact pads on its active surface.
  • a plurality of bond wire connections are then formed between the plurality of chip contact pads and the inner portions of the plurality of leadfingers .
  • a bond wire is formed between each contact pad and its corresponding leadfinger so that crossing of the bond wires is avoided. This reduces the likelihood of short-circuiting between bond wires during the wire bonding process and during the molding process.
  • a molding process is then performed. At least the inner portion of the plurality of leadfingers, the active surface of the semiconductor chip and the plurality of bond wires are then encapsulated in a mold compound which, preferably, comprises an epoxy resin.
  • the outer surfaces of the mold compound provide the outer surfaces of the semiconductor package.
  • a plurality of packages may be formed on the leadframe strip and then the tie bars which mechanically link each leadframe to its adjacent neighbour or neighbours are removed. This separates the semiconductor package from the leadframe strip and separates the plurality of leadfingers from each other.
  • the outer portions of the leadfingers which remain exposed from the mold compound provide the outer contacts of the semiconductor package.
  • the package can then be mounted to a higher level substrate such as a printed circuit board.
  • the invention provides a semiconductor package in which the risk of delamination at the interfaces between the die pad, mold compound and glue is reduced.
  • Semiconductor packages typically undergo stress tests such as preconditioning, pressure cooker tests and thermal cycling tests. Due to the mismatch of the coefficients of thermal expansion of the different materials, delamination at the interfaces can occur.
  • the semiconductor package of the invention comprises a mesh die pad, which is similar to a wire mesh, and comprises a plurality of interconnected fibres which provide a plurality of through holes or through-openings .
  • This arrangement in which the glue and, in particular, the mold compound are em- bedded within the mesh die pad, provides a highly interlocked arrangement. Therefore, if the package is subjected to high humidity and high temperatures, the expansion/contraction and cambering effects are counteracted by the relief provided by the many through-openings as well is by the flexibility of the mesh die pad. The risk of delamination is reduced and a more reliable semiconductor package is provided.
  • a mesh die pad also has the advantage in that a larger range of chip sizes may be used for a single die pad size due to the improved interlocking between the mold compound, the glue and the die pad. This further reduces the cost of the semiconduc- tor package as the number of different types of leadframes which have to be manufactured and stocked is reduced. It is also simpler to change the package assembly line from one chip size to another.
  • leadframe strip in which the die pads comprise a mesh is also advantageous as changes to the existing package assembly line are not required. Therefore, leadframe of the invention can be used in the existing assembly line and package assembly costs are not increased.
  • Figure 1 shows a plan view of a package position of a lead- frame strip according to one embodiment of the invention
  • Figure 2 illustrates a cross-sectional view semiconductor package including a leadframe as shown in Figure 1.
  • Figure 1 shows the plan view of a portion of a leadframe strip 1 which includes a plurality of package positions 2 disposed at a regular periodic intervals along the length of the leadframe strip 1.
  • Each package position 2 provides a leadframe 3 for use in a semiconductor package and each package position 2 is mechanically connected to its adjacent neighbour in the leadframe strip 1 by tie bars 24.
  • Figure 1 depicts one package position 2 of the leadframe strip 1.
  • Each leadframe 3 comprises a die pad 4 laterally surrounded by a plurality of leadfingers 5.
  • the die pad 4 is essentially laterally square and comprises a mesh 6.
  • the mesh 6 comprises a plurality of interconnected fibres 7 which, in this embodiment of the invention, have a square grid arrangement.
  • the square grid arrangement of interconnected fibres 7 provide a plurality of through holes or openings 8, each of which is laterally essentially square.
  • the plurality of through- openings 8 are arranged in a regular grid array of rows and columns in the die pad 4.
  • Each of the plurality of through- openings 8 has essentially the same lateral dimensions.
  • the plurality of through-openings 8 has lateral dimensions sufficiently small that the effect of surface tension prohibits glue from flowing through the through-openings 8 and has lateral dimensions sufficiently large that the mold compound is able to flow through the through-openings 8.
  • the leadframe 3 also includes die pad leads 9 positioned at each of the four corners of the die pad 4.
  • the die pad leads 9 extend outwardly from the corner of the die pad 4 and mechanically link the die pad 4 with the leadframe strip 1 to provide mechanical stability for the die pad 4 during the assembly process.
  • Each leadfinger 5 comprises an inner portion 10 and the outer portion 11.
  • the inner portion 10 is positioned inside the plastic material which comprises the housing of the semiconductor package.
  • the outer portion in 11 of each of the leadfingers 5 extends outside of the package material and pro- vides the external contacts of the semiconductor package.
  • the plurality of leadfingers 5 are arranged in four sets 12, each set 12 being associated with a side of the die pad 4.
  • Each of the leadfingers 5 within a set 12 is arranged is so that the length of the leadfinger lies approximately orthogo- nal to the side of the die pad 4 and the inner end of the inner portion 10 lies at essentially the same distance from the side of the die pad 4.
  • Each leadfinger 5 is connected to its adjacent neighbour in the set 12 by a tie bar 13 which will be removed after the package has been assembled.
  • the tie bars 13 improve the mechanical robustness of the leadframe 3 during the assembly process .
  • the leadframe strip 1 further includes a plurality of locating means 14 positioned in the peripheral regions of the leadframe strip 1.
  • the locating means typically comprise a circular through holes or elongated slots which enable the leadframe strip to be handled by automated feeding equipment and to be accurately aligned.
  • FIG. 2 illustrates a semiconductor package 15 according to one embodiment of the invention.
  • the semiconductor package 15 includes a leadframe 3 comprising a die pad 4 which is laterally surrounded by a plurality of leadfingers 5.
  • the die pad 4 comprises a plurality of the fibres 7 which have an essentially square cross-section.
  • the die pad 4, therefore, also comprises a plurality of through holes 8 which have an essentially square cross-section.
  • the die pad 4 and the inner portion 10 of the plurality of leadfingers 5 are approximately coplanar.
  • an arrangement with a recessed die pad which lies in a plane lower than the leadfingers within the semiconductor package is also possible.
  • the semiconductor package 15 also includes a semiconductor chip 16 which has an active face including a plurality of integrated circuit devices and chip contact pads 17.
  • the oppos- ing passive surface of the semiconductor chip 16, which does not include integrated circuit devices, is attached to the upper surface of the die pad 4 by a layer of glue 18.
  • the semiconductor chip 16 is laterally smaller than the die pad 4 and is located in approximately the lateral centre of the die pad 4.
  • the through-openings 8 of the die pad are, therefore, of two types.
  • a first plurality of through-openings 19 are located towards the lateral centre of the die pad 4 and are positioned under the chip 16 and the glue 18.
  • the die pad 4 includes a second plurality of through holes 20 which are positioned in the peripheral regions of the die pad 4 and are positioned laterally adjacent the semiconductor chip 16 and the layer of glue 18.
  • the semiconductor chip 16 is electrically connected to the plurality of leadfingers 5 by a plurality of bond wires 21.
  • a contact pad 22 is positioned on the upper surface towards the inner end of the inner portion of the leadfinger 5.
  • a bond wire 21 extends between a chip contact pad 17 and the contact pad 22 located on the inner portion 10 of one of the plurality of leadfingers 5.
  • the semiconductor package 15 also include mold material 23 which encapsulates the inner portions 10 of the plurality of leadfingers 5, the semiconductor chip 16, the plurality of bond wires 21 and the upper and lower surfaces of the die pad 4.
  • mold material 23 which encapsulates the inner portions 10 of the plurality of leadfingers 5, the semiconductor chip 16, the plurality of bond wires 21 and the upper and lower surfaces of the die pad 4.
  • the second plurality of through holes 20 located in the peripheral regions of the die pad 4 are filled by the mold compound 23.
  • the first plurality of through holes 19 positioned towards the lateral centre of the die pad 4 include glue material 18 which is prohibited from flowing through the first plurality of through holes 19 by the effect of surface tension.
  • the die pad 4 which comprises a plurality of interconnected fibres 7 and a plurality of through-openings 8 provides an anchoring or interlocking of the mold material 23 and the die pad 4. This is achieved by increasing the interfacial area between the plurality of the fibres 7 and mold material 23 as well as by a uniformly distributed mechanical interlocking of the mold material 23 and the through holes 8.
  • the provision of a die pad 4 which comprises a mesh 6 also provides a package with a flexible die pad 4 in contrast to relatively rigid single sheet solid die pads. This further improves the reliability of the package 15.
  • the invention also provides methods of fabricating the lead- frame 3 and semiconductor package 15.
  • a leadframe strip 1 comprising a plurality of package positions 2 each providing a leadframe 3 for a semiconductor package 15 is manufactured by applying a structured resist mask on the surface of a metal sheet.
  • the areas of the metal sheet exposed from the structured resist ask are etched away in an etching process to provide a mesh die pad 4 comprising a plurality of interconnected the fibres 7 in a square grid arrangement and a plurality of through holes 8 arranged in rows and columns.
  • the die pad 4 is laterally surrounded by a plurality of leadfingers 5.
  • the semiconductor chip 16 is then attached to the upper surface of the die pad 4 by a layer of glue 18.
  • the integrated circuit devices of the active surface of the semiconductor chip 16 are accessed by bond wires 21 which are then provided between the chip contact pads 17 and the inner portions 10 of the plurality of leadfingers 5. Each of these steps is typically performed on a plurality of package positions 2 in the same process step.
  • Each package position 2 within the leadframe strip 1 then undergoes a molding process which encapsulates the semiconductor chip 16, bond wires 21, die pad 4 and inner portions 10 of the leadfingers 5 in mold material 23.
  • the tie bars 13 and 24 are then removed to separate the leadfingers 5 from each other and the semiconductor package 15 from the leadframe strip 1.
  • the semiconductor chip can then be tested and mounted to a high-level substrate such as a printed circuit board.

Abstract

A semiconductor package includes a leadframe (3) which comprises a die pad (4) and a plurality of leadfingers (5). The plurality of leadfingers (5) are arranged laterally adjacent the die pad (4) and each leadfinger (5) has an inner portion (10) and an outer portion (11). The die pad (4) comprises a mesh (6) which comprises a plurality of interconnected fibres (7). The plurality of interconnected fibres (7) provide a plurality of through-openings (8) in the die pad (4).

Description

Description
Leadframe, Semiconductor package and methods of producing the same
The invention relates to a leadframe, a semiconductor package including the leadframe and to methods of producing a leadframe and a semiconductor package.
Encapsulated or molded leadframe-based semiconductor packages suffer from reliability problems due to the formation of cracks in the package. Cracks are formed due to the difference in coefficient of thermal expansion (CTE) between the materials of the semiconductor chip, the die pad and the mold com- pound. As the materials expand and contract due to varying temperature, the mis-match in the coefficients of thermal expansion results in warping or cambering of the die pad. This causes cracks to form, typically, at the interface between the die pad and the mold material and the interface between the die pad and the semiconductor chip. The cracks can lead to de- lamination, moisture penetration and failure of the package. The reliability of leadframe-based semiconductor packages is, therefore, limited.
This problem has been addressed in US 5,150,193 by providing a single or, alternatively, a few relatively large slots in the die pad. The provision of a large slot is thought to reduce the stress at the outer edge of the die pad and to provide a mechanical anchoring effect between the mold compound and the die pad. However, these leadframe-based packages have the disadvantage that the reliability of the packages is still lim- ited since there is a risk of the die attach glue mixing with the mold compound under the die pad.
It is an object of the invention to provide a leadframe and a semiconductor package which overcome these problems and which can be easily produced.
This object is achieved by the subject matter of the independent claims. Further improvements arise from the subject matter of the dependent claims.
The invention provides a leadframe which comprises a die pad and a plurality of leadfingers. The die pad is positioned in approximately the lateral centre of the leadframe and the plu- rality of leadfingers are arranged laterally adjacent the die pad. Each leadfinger has an inner portion which will be located inside the plastic housing material of the semiconductor package and an outer portion which will be exposed from the plastic housing. The outer portion will provide the external contacts of the semiconductor package.
The die pad, according to the invention, comprises a mesh. The mesh comprises a plurality of interconnected fibres which provide a plurality of through-openings or apertures which extend from the upper surface to the lower surface of the die pad.
The advantages of a die pad comprising a mesh are observed when the die pad is used in the assembly of a molded semiconductor package. A die pad comprising a mesh has the advantage that a flexible die pad is provided in contrast to the die pads comprising a single solid sheet which are relatively rigid. The flexibility of the mesh die pad enables the warping or cambering effects caused, by the expansion and contraction of the die pad due to temperature variations to be counteracted. Additionally, the interfacial area between the mesh, which comprises the die pad, and the glue and molding compound is increased. The interconnected fibres and through-openings provide a highly interlocked system between the die pad and the mold compound. This improves the mechanical anchoring or inter-gripping effect between the die pad and the mold compound and the glue. This reduces the risk of delamination at the interfaces between the die pad and the glue and the die pad and the mold compound. The reliability of a semiconductor package including a leadframe with a mesh die pad is, therefore, improved.
A semiconductor chip is typically attached to the upper surface of the die pad in the assembly of the semiconductor package by a layer of glue. Each of the plurality of through- openings, preferably, has lateral dimensions which are sufficiently small that the effect of surface tension prohibits glue from flowing through the through-openings . Therefore, the problem of mixing of the glue and mold compound is avoided.
Additionally, if the through-openings are too large, glue can flow completely through the through-openings and attach the leadframe to an underlying carrier or support and contaminate the rear surface of the die pad. The package is then normally discarded. This problem is avoided in the invention by providing a plurality of through-openings which have lateral dimensions such that the effect of surface tension prevents the glue from flowing through the through-openings. The properties of the glue, such as its viscosity, wetting properties and setting properties as well as the effect of surface tension influence the optimum lateral dimensions of the plurality of through-openings. The optimum lateral dimen- sions of the through-openings provided by the plurality of interconnected fibres can be, therefore, simply determined by routine experimentation for a particular glue so that the effect of surface tension prohibits the glue from flowing through the through-openings and onto the rear surface of the die pad.
The semiconductor package typically also includes mold material or compound which encapsulates the semiconductor chip and die pad and provides the plastic package housing of the semi- conductor package. Each of the plurality of through-openings, preferably, has lateral dimensions sufficiently large that the mold compound is able to flow through the through-openings . This ensures that the formation of the air bubbles with in the mold compound which comprises the plastic housing of the semi- conductor package is avoided. The mold compound, preferably, comprises an epoxy resin and may further comprise filler particles .
The lateral dimensions of the plurality of through-openings are simply and easy determined by routine experimentation for a particular mold compound with particular properties so that the mold compound is able to flow through the through-openings and cover both the upper and lower surfaces of the die pad.
Therefore, in one embodiment of the invention, the lateral dimensions of each of the plurality of through-openings are chosen so that the lateral dimensions are sufficiently small that the effect of surface tension prohibits glue from flowing through the through holes and that each of the plurality of through-openings is sufficiently large that the mold compound is able to flow through the through-openings .
The plurality of interconnected fibres, preferably, lies in a single plane. This arrangement of the mesh has the advantage that the die pad is simply manufactured by using an etching or stamping method to form a plurality of through-openings which stretch from the upper surface to the lower surface of the die pad.
The plurality of interconnected fibres, preferably, has a regular grid array arrangement. More preferably, the plurality of interconnected fibres has a square or rectangular grid arrangement or a rhomboid grid arrangement or a diamond grid arrangement . Regular grid arrangements have the advantage that the surface area of the fibres is increased and a homogenous structure is provided which increases the homogeneity of the stress distribution. Therefore, the disadvantageous effects of the mismatch in coefficients of thermal expansion are more effectively reduced and the interlocking effect of the fibres within the package is more effectively improved. The reliability of the semiconductor package is, therefore, further in- creased.
Preferably, each of the plurality of through holes has essentially the same lateral dimensions. This further improves the reliability of a package and simplifies the optimisation proc- ess to determine appropriate lateral dimensions for the through-openings . The leadframe can comprise copper or a copper-based alloy or a nickel iron alloy such as alloy 42. These materials are widely used for leadframes for semiconductor packages and, therefore, the cost of the leadframe according to the invention is not increased.
The leadframe may also further include at least one die pad lead. The die pad lead may be used for grounding the rear surface of the semiconductor chip as well as the integrated cir- cuit devices in the active surface of the chip.
In one embodiment of the invention, the die pad is laterally essentially square and leadfingers are arranged adjacent to each of the four sides of the die pad. The leadfingers are ar- ranged so that the inner end of each leadfinger points towards a side of the die pad. Each of the inner ends is typically located at essentially the same distance from a side of the die pad. This simplifies the wire bonding process and provides conduction paths of a similar length which improves the per- formance of the package.
Alternatively, the die pad is laterally essentially rectangular and has two short sides and two long sides. In this embodiment of the invention, the leadfingers are arranged adja- cent to each of the two long sides of the die pad. The inner end of each of the plurality of leadfingers points towards, and is positioned at essentially the same distance from, the long sides of the die pad.
The invention also relates to a leadframe strip comprising a plurality of leadframes according to one of the embodiment is already described. The leadframe strip includes a plurality of individual component positions, each component position providing a leadframe for a semiconductor package. Each, leadframe is used in the manufacture of a single semiconductor package or electronic component.
Each leadframe is mechanically linked to its adjacent neighbour by at least one tie bar so that a strip is formed. The leadframe strip may also include a plurality of locating holes positioned towards the peripheral edges of the strip and, preferably, outside of the portion of the leadframe strip which will be used to manufacture a semiconductor package. The locating holes enable the strip to be handled by automated equipment and provide a means by which the orientation and alignment of the strip can be controlled and adjusted.
The plurality of leadframes are, preferably, arranged in at least one row in the leadframe strip. In one embodiment of the invention, the leadframe strip comprises a long tape including a plurality of leadframes arranged at regular, periodic inter- vals in a single row. In an alternative embodiment, the plurality of leadframes are arranged in a leadframe strip in a grid of rows and columns .
The invention also relates to semiconductor packages including a leadframe according to one of the embodiments previously described. The semiconductor package further comprises a semiconductor chip with an active surface and a passive surface. The active surface comprises a plurality of integrated circuit devices and a plurality of chip contact pads which provide electrical access to the integrated circuit devices. The passive surface of the semiconductor chip is attached to a region of the die pad by a layer of glue. The semiconductor package also includes a plurality of bond wires which electrically connect the plurality of chip contact pads and the inner portions of the plurality of leadfingers . Preferably, a contact pad is positioned towards the inner end of the inner portion of each of the plurality of leadfingers and a bond wire is disposed between a chip contact pad and its corresponding contact pad positioned on the leadfinger.
The semiconductor package also comprises mold compound which, preferably, comprises an epoxy resin. The mold compound encapsulates at least the inner portions of the plurality of lead- fingers, the active surface of the semiconductor chip and the plurality of bond wires . Preferably, the regions of the upper surface of the die pad which are not in contact with the glue layer, the through-openings and the rear surface of the die pad are also encapsulated by the mold compound.
A semiconductor package according to the invention, therefore, includes a leadframe comprising a die pad which comprises a mesh. The mesh comprises a plurality of interconnected fibres which provide a plurality of through-openings . The invention, therefore, provides a more reliable semiconductor package as the flexible mesh die pad reduces the risk of delamination at the interfaces between the die pad and the mold compound and the glue and the die pad as the effect of die pad warping due to temperature fluctuation is reduced.
The mesh die pad also improves the mechanical interlocking be- tween the die pad and the mold compound and glue as the inter- facial surface area is increased and a finely structured inter-locking anchoring structure is provided. This reduces the risk of crack formation at the interfaces between the die pad and the mold compound and the die pad and the glue.
The layer of glue may be located at least partially within at least one of the through-openings which is located in the region of the die pad vertically adjacent the semiconductor chip. In other words, the through-opening is located under the semiconductor chip. In addition to the lateral diemsions of the through-openings, the effect of the weight of the glue, wetting properties of the glue on the material of the die pad, the effect of surface tension and the speed of hardening or setting influence the degree to which the glue flows into the through-holes .
The combination of these effects result in a structure whereby the glue may at least partially flow into the through- openings. As previously discussed, the lateral dimensions of each of the plurality of through-openings are optimised to control the extent to which the glue flows into the through- openings of the mesh so that the effect of surface tensions prohibits the glue from flowing through the through-openings .
The mold compound, preferably, essentially fills the through- openings which are located in at least one region of the die pad which is laterally adjacent the semiconductor chip. This provides an improved interlocking of the mold compound with the die pad and avoids the formation of air bubbles within the mold compound. The likelihood of moisture penetration and de- lamination at the interface between the mold compound and the die pad is reduced and the reliability of the package improved. Typically, the semiconductor chip is located in the approximate lateral centre of the die pad. The peripheral regions of the die pad lie laterally adjacent the semiconductor chip and are in contact with the mold compound on the upper surface of as well as the lower surface of the die pad. The mold compound, preferably, essentially fills the through-openings located in these regions and provides an improved and more uniform interlocking between the mold compound and the die. This uniformity further improves the reliability of the semiconduc- tor package.
The invention also relates to methods to produce a leadframe and semiconductor packages. A method to produce a leadframe comprises the step of providing a metal or metal alloy sheet. The sheet is then structure to form at least one leadframe. Each leadframe comprises a die pad and plurality of lead- fingers which are located laterally adjacent the die pad. The die pad comprises a mesh which comprises a plurality of interconnected fibres which provide a plurality of through- openings.
In one embodiment of the invention, the metal sheet is structured by forming a structured resist mask on at least one surface of the sheet. An etching process is then performed to re- move the portions of the sheet which are exposed by a structured resist mask. The remaining portions provide a leadframe having the desired structured. The structured resist mask is then removed to provide a leadframe in which the die pad comprises a mesh.
This method has the advantage that the dimensions of the plurality of interconnected fibres and plurality of through- openings which comprise the mesh can be simply and accurately controlled. A finely structured resist mask can be provided by photolithographic techniques. Etching is particularly advantageous when a finely structured mesh is desired. Etching also has the advantage that it is commonly used in the fabrication of leadframes. Therefore, a leadframe according to the invention can be produced by simply changing the pattern of the structured resist mask to provide a mesh die pad. The manufacturing costs of the leadframe of the invention are, therefore, not significantly higher than for leadframes which comprise a die pad of a single solid sheet.
Alternatively, other known leadframe fabrication methods may be modified to provide a leadframe including a mesh die pad according to one of the embodiments of the invention. Typical methods are stamping or milling.
Preferably, the die pad is structured so that each of the plurality of through-openings has lateral dimensions which are sufficiently small that the effect of surface tension prohibits glue from flowing through the through-openings . The die pad is, preferably, structured so that each of the plurality of through-openings has lateral dimensions sufficiently large that the mold compound is able to flow through the through- openings. Depending on the etching conditions used, the through-holes produced may not be of exactly the same dimensions as the corresponding exposed areas in the structured resist mask. Therefore, the dimensions of the structured resist mask may be adjusted so that the through-openings produced have the desired lateral dimensions. Typically, the metal sheet is structured to provide a plurality of leadframes, each leadframe being used in the manufacture of a single semiconductor package. The plurality of lead- frames are normally connected to their adjacent neighbours by tie bars so that a mechanically stable strip is provided. This enables automated handling of the leadframe strip and improves the speed, efficiency and reliability of the assembly process.
The invention also provides a method to produce a semiconduc- tor package. A leadframe strip comprising at least one leadframe according to one of the embodiment previously described is provided. A semiconductor chip with an active surface and a passive surface is provided. The passive surface of the semiconductor chip is attached to a region of the die pad of the leadframe by a layer of glue. The semiconductor chip includes a plurality of integrated circuit devices and a plurality of chip contact pads on its active surface.
A plurality of bond wire connections are then formed between the plurality of chip contact pads and the inner portions of the plurality of leadfingers . Typically, a bond wire is formed between each contact pad and its corresponding leadfinger so that crossing of the bond wires is avoided. This reduces the likelihood of short-circuiting between bond wires during the wire bonding process and during the molding process.
A molding process is then performed. At least the inner portion of the plurality of leadfingers, the active surface of the semiconductor chip and the plurality of bond wires are then encapsulated in a mold compound which, preferably, comprises an epoxy resin. The outer surfaces of the mold compound provide the outer surfaces of the semiconductor package. A plurality of packages may be formed on the leadframe strip and then the tie bars which mechanically link each leadframe to its adjacent neighbour or neighbours are removed. This separates the semiconductor package from the leadframe strip and separates the plurality of leadfingers from each other. The outer portions of the leadfingers which remain exposed from the mold compound provide the outer contacts of the semiconductor package. The package can then be mounted to a higher level substrate such as a printed circuit board.
The invention provides a semiconductor package in which the risk of delamination at the interfaces between the die pad, mold compound and glue is reduced. Semiconductor packages typically undergo stress tests such as preconditioning, pressure cooker tests and thermal cycling tests. Due to the mismatch of the coefficients of thermal expansion of the different materials, delamination at the interfaces can occur.
However, the semiconductor package of the invention comprises a mesh die pad, which is similar to a wire mesh, and comprises a plurality of interconnected fibres which provide a plurality of through holes or through-openings . This arrangement, in which the glue and, in particular, the mold compound are em- bedded within the mesh die pad, provides a highly interlocked arrangement. Therefore, if the package is subjected to high humidity and high temperatures, the expansion/contraction and cambering effects are counteracted by the relief provided by the many through-openings as well is by the flexibility of the mesh die pad. The risk of delamination is reduced and a more reliable semiconductor package is provided. A mesh die pad also has the advantage in that a larger range of chip sizes may be used for a single die pad size due to the improved interlocking between the mold compound, the glue and the die pad. This further reduces the cost of the semiconduc- tor package as the number of different types of leadframes which have to be manufactured and stocked is reduced. It is also simpler to change the package assembly line from one chip size to another.
The use of a leadframe strip in which the die pads comprise a mesh is also advantageous as changes to the existing package assembly line are not required. Therefore, leadframe of the invention can be used in the existing assembly line and package assembly costs are not increased.
Embodiments of the invention will now be described with reference to the diagrams .
Figure 1 shows a plan view of a package position of a lead- frame strip according to one embodiment of the invention, and Figure 2 illustrates a cross-sectional view semiconductor package including a leadframe as shown in Figure 1.
Figure 1 shows the plan view of a portion of a leadframe strip 1 which includes a plurality of package positions 2 disposed at a regular periodic intervals along the length of the leadframe strip 1. Each package position 2 provides a leadframe 3 for use in a semiconductor package and each package position 2 is mechanically connected to its adjacent neighbour in the leadframe strip 1 by tie bars 24. Figure 1 depicts one package position 2 of the leadframe strip 1. Each leadframe 3 comprises a die pad 4 laterally surrounded by a plurality of leadfingers 5. The die pad 4 is essentially laterally square and comprises a mesh 6. The mesh 6 comprises a plurality of interconnected fibres 7 which, in this embodiment of the invention, have a square grid arrangement. The square grid arrangement of interconnected fibres 7 provide a plurality of through holes or openings 8, each of which is laterally essentially square. The plurality of through- openings 8 are arranged in a regular grid array of rows and columns in the die pad 4. Each of the plurality of through- openings 8 has essentially the same lateral dimensions.
The plurality of through-openings 8 has lateral dimensions sufficiently small that the effect of surface tension prohibits glue from flowing through the through-openings 8 and has lateral dimensions sufficiently large that the mold compound is able to flow through the through-openings 8.
The leadframe 3 also includes die pad leads 9 positioned at each of the four corners of the die pad 4. The die pad leads 9 extend outwardly from the corner of the die pad 4 and mechanically link the die pad 4 with the leadframe strip 1 to provide mechanical stability for the die pad 4 during the assembly process. Each leadfinger 5 comprises an inner portion 10 and the outer portion 11. The inner portion 10 is positioned inside the plastic material which comprises the housing of the semiconductor package. The outer portion in 11 of each of the leadfingers 5 extends outside of the package material and pro- vides the external contacts of the semiconductor package. The plurality of leadfingers 5 are arranged in four sets 12, each set 12 being associated with a side of the die pad 4. Each of the leadfingers 5 within a set 12 is arranged is so that the length of the leadfinger lies approximately orthogo- nal to the side of the die pad 4 and the inner end of the inner portion 10 lies at essentially the same distance from the side of the die pad 4. Each leadfinger 5 is connected to its adjacent neighbour in the set 12 by a tie bar 13 which will be removed after the package has been assembled. The tie bars 13 improve the mechanical robustness of the leadframe 3 during the assembly process .
The leadframe strip 1 further includes a plurality of locating means 14 positioned in the peripheral regions of the leadframe strip 1. The locating means typically comprise a circular through holes or elongated slots which enable the leadframe strip to be handled by automated feeding equipment and to be accurately aligned.
Figure 2 illustrates a semiconductor package 15 according to one embodiment of the invention. The semiconductor package 15 includes a leadframe 3 comprising a die pad 4 which is laterally surrounded by a plurality of leadfingers 5. As shown in the cross-sectional view in figure 2, the die pad 4 comprises a plurality of the fibres 7 which have an essentially square cross-section. The die pad 4, therefore, also comprises a plurality of through holes 8 which have an essentially square cross-section. In this embodiment of the invention, the die pad 4 and the inner portion 10 of the plurality of leadfingers 5 are approximately coplanar. However, an arrangement with a recessed die pad which lies in a plane lower than the leadfingers within the semiconductor package is also possible. The semiconductor package 15 also includes a semiconductor chip 16 which has an active face including a plurality of integrated circuit devices and chip contact pads 17. The oppos- ing passive surface of the semiconductor chip 16, which does not include integrated circuit devices, is attached to the upper surface of the die pad 4 by a layer of glue 18.
The semiconductor chip 16 is laterally smaller than the die pad 4 and is located in approximately the lateral centre of the die pad 4. The through-openings 8 of the die pad are, therefore, of two types. A first plurality of through-openings 19 are located towards the lateral centre of the die pad 4 and are positioned under the chip 16 and the glue 18. The die pad 4 includes a second plurality of through holes 20 which are positioned in the peripheral regions of the die pad 4 and are positioned laterally adjacent the semiconductor chip 16 and the layer of glue 18.
The semiconductor chip 16 is electrically connected to the plurality of leadfingers 5 by a plurality of bond wires 21. A contact pad 22 is positioned on the upper surface towards the inner end of the inner portion of the leadfinger 5. A bond wire 21 extends between a chip contact pad 17 and the contact pad 22 located on the inner portion 10 of one of the plurality of leadfingers 5.
The semiconductor package 15 also include mold material 23 which encapsulates the inner portions 10 of the plurality of leadfingers 5, the semiconductor chip 16, the plurality of bond wires 21 and the upper and lower surfaces of the die pad 4. As can be seen in the cross-sectional view of figure 2, the second plurality of through holes 20 located in the peripheral regions of the die pad 4 are filled by the mold compound 23. In contrast, the first plurality of through holes 19 positioned towards the lateral centre of the die pad 4 include glue material 18 which is prohibited from flowing through the first plurality of through holes 19 by the effect of surface tension.
The die pad 4 which comprises a plurality of interconnected fibres 7 and a plurality of through-openings 8 provides an anchoring or interlocking of the mold material 23 and the die pad 4. This is achieved by increasing the interfacial area between the plurality of the fibres 7 and mold material 23 as well as by a uniformly distributed mechanical interlocking of the mold material 23 and the through holes 8. The provision of a die pad 4 which comprises a mesh 6 also provides a package with a flexible die pad 4 in contrast to relatively rigid single sheet solid die pads. This further improves the reliability of the package 15.
The invention also provides methods of fabricating the lead- frame 3 and semiconductor package 15. A leadframe strip 1 comprising a plurality of package positions 2 each providing a leadframe 3 for a semiconductor package 15 is manufactured by applying a structured resist mask on the surface of a metal sheet. The areas of the metal sheet exposed from the structured resist ask are etched away in an etching process to provide a mesh die pad 4 comprising a plurality of interconnected the fibres 7 in a square grid arrangement and a plurality of through holes 8 arranged in rows and columns. The die pad 4 is laterally surrounded by a plurality of leadfingers 5. The semiconductor chip 16 is then attached to the upper surface of the die pad 4 by a layer of glue 18. The integrated circuit devices of the active surface of the semiconductor chip 16 are accessed by bond wires 21 which are then provided between the chip contact pads 17 and the inner portions 10 of the plurality of leadfingers 5. Each of these steps is typically performed on a plurality of package positions 2 in the same process step.
Each package position 2 within the leadframe strip 1 then undergoes a molding process which encapsulates the semiconductor chip 16, bond wires 21, die pad 4 and inner portions 10 of the leadfingers 5 in mold material 23. The tie bars 13 and 24 are then removed to separate the leadfingers 5 from each other and the semiconductor package 15 from the leadframe strip 1.
The semiconductor chip can then be tested and mounted to a high-level substrate such as a printed circuit board.
Reference numbers
1 leadframe strip 2 package position
3 leadframe
4 die pad
5 leadfinger
6 mesh 7 fibre
8 through-opening
9 die pad leads
10 inner portion of leadfinger
11 outer portion of leadfinger 12 set of leadfingers
13 tie bar
14 locating means
15 semiconductor package
16 semiconductor chip 17 chip contact pad
18 glue
19 first through-opening
20 second through-opening 21 wire 22 leadfinger contact pad
23 mold material
24 leadframe tie bar

Claims

Patent Claims
1. Leadframe (3) comprising: a die pad (4) ; and a plurality of leadfingers (5) arranged laterally adjacent the die pad (4) , each leadfinger (5) having an inner portion (10) and an outer portion (11), wherein the die pad (4) comprises a mesh (6) , the mesh (6) comprising a plurality of interconnected fibres (7) which provide a plurality of through-openings (8).
2. Leadframe (3) according to claim 1 characterised in that each of the plurality of through-openings (8) has lateral dimensions sufficiently small that the effect of surface tension prohibits glue (18) from flowing through the through-openings (8).
3. Leadframe (3) according to claim 1 or claim 2 characterised in that each of the plurality of through-openings (8) has lateral dimensions sufficiently large that mold compound (23) is able to flow through the through-openings (8).
4. Leadframe (3) according to one of the previous claims characterised in that the plurality of interconnected fibres (7) lies in a single plane.
5. Leadframe (3) according to one of the previous claims characterised in that the plurality of interconnected, fibres (7) has a regular grid array arrangement .
6. Leadframe (3) according to claim 5 characterised in that the plurality of interconnected fibres (7) has a square grid arrangement or a rhomboid grid arrangement.
7. Leadframe (3) according to one of the previous claims characterised in that each of the plurality of through holes (8) has essentially the same lateral dimensions.
8. Leadframe (3) according to one of the previous claims characterised in that the leadframe (3) comprises copper or a copper based alloy or a nickel-iron alloy.
9. Leadframe (3) according to one of the previous claims characterised in that the leadframe (3) further includes at least one die pad lead (9) .
10. Leadframe (3) according to one of the previous claims characterised in that the die pad (4) is laterally essentially square and lead- fingers (5) are arranged adjacent to each of the four sides of the die pad (4) .
11. Leadframe (3) according to one of claims 1 to 9 characterised in that the die pad (4) is laterally essentially rectangular and leadfingers (5) are arranged adjacent to each of the two long sides of the die pad (4) .
12. Leadframe strip (1) comprising: a plurality of leadframes (3) of one of claims 1 to 11, each leadframe (3) being attached to its adjacent neighbour by at least one tie bar (24) .
13. Leadframe strip (1) according to claim 12 characterised in that the plurality of leadframes (3) are arranged in at least one row.
14. Semiconductor package (15) comprising: a leadframe (3) of one of claims 1 to 11; a semiconductor chip (16) , the semiconductor chip (16) having an active surface with a plurality of chip contact pads (17) and a passive surface, the passive sur- face being attached to a region of the die pad (4) by a layer of glue (18) ; a plurality of bond wires (21) , the plurality of bond wires (21) electrically connecting the plurality of the chip contact pads (17) and the inner portions (10) of the plurality of leadfingers (5), and mold compound (23), the mold compound (23) encapsulating at least the inner portion (10) of the plurality of leadfingers (5), the active surface of the semiconductor chip (16) and the plurality of bond wires (21) .
15. Semiconductor package (15) according to claim 14 characterised in that the layer of glue (18) is located at least partially within at least one of the through-openings (19) located in the region of the die pad (4) vertically adjacent the semiconductor chip (16) .
16. Semiconductor package (15) according to claim 14 or claim 15 characterised in that the mold compound (23) essentially fills the through- openings (20) located in at least one region of the die pad (4) which is laterally adjacent the semiconductor chip (16) .
17. Method to produce a leadframe (3) comprising: - providing a metal or metal alloy sheet; and structuring the sheet to form at least one leadframe (3), wherein each leadframe (3) comprises a die pad (4) and a plurality of leadfingers (5) located laterally adjacent the die pad (4) , and wherein the die pad (4) comprises a mesh (6) , the mesh (6) comprising a plurality of interconnected fibres (7) which provide a plurality of through-openings (8) .
18. Method to produce a leadframe (3) according to claim 17 characterised in that the sheet is structured by: forming a structured resist mask on a surface of the sheet; performing an etching process to remove portions of the sheet exposed by the structured resist mask, and removing the structured resist mask.
19. Method to produce a leadfraine (3) according to claim 17 or claim 18 characterised in that the die pad (4) is structured so that each of the plural- ity of through-openings (8) has lateral dimensions sufficiently small that the effect of surface tension prohibits glue (18) from flowing through the through-openings (8) .
20. Method to produce a leadfraine according to on of claims 17 to 19 characterised in that the die pad (4) is structured so that each of the plurality of through-openings (8) has lateral dimensions sufficiently large that the mold compound (23) is able to flow through the through-openings (8).
21. Method to produce a semiconductor package (15), comprising: providing a leadframe strip according to claim 12 or claim 13; providing a semiconductor chip (16), the semiconductor chip (16) having an active surface with a plurality of chip contact pads (17) and a passive surface; attaching the passive surface of the semiconductor chip (16) to a region of the die pad (4) by a layer of glue (18); forming a plurality of bond wires (21) between the plurality of chip contact pads (17) and the inner portions (10) of the plurality of leadfingers (5) ; - encapsulating at least the inner portion (10) of the plurality of leadfingers (5) , the active surface of the semiconductor chip (16) and the plurality of bond wires (21) in a mold compound (23); and removing the tie bars (13; 24) to separate the semiconductor package (15) from the leadframe strip (1) .
PCT/IB2005/001628 2005-06-10 2005-06-10 Leadframe, semiconductor package and methods of producing the same WO2006131776A1 (en)

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WO2018152378A1 (en) * 2017-02-15 2018-08-23 Texas Instruments Incorporated Semiconductor package with a wire bond mesh

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JPH04146658A (en) * 1990-10-09 1992-05-20 Toshiba Corp Lead frame
JP2000031371A (en) * 1998-07-09 2000-01-28 Seiko Epson Corp Lead frame and semiconductor device comprising the same
US6326243B1 (en) * 1995-08-15 2001-12-04 Kabushiki Kaisha Toshiba Resin sealed semiconductor device including a die pad uniformly having heat conducting paths and circulating holes for fluid resin

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JPH0319261A (en) * 1989-06-15 1991-01-28 Matsushita Electron Corp Lead frame for semiconductor
JPH04146658A (en) * 1990-10-09 1992-05-20 Toshiba Corp Lead frame
US6326243B1 (en) * 1995-08-15 2001-12-04 Kabushiki Kaisha Toshiba Resin sealed semiconductor device including a die pad uniformly having heat conducting paths and circulating holes for fluid resin
JP2000031371A (en) * 1998-07-09 2000-01-28 Seiko Epson Corp Lead frame and semiconductor device comprising the same

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018152378A1 (en) * 2017-02-15 2018-08-23 Texas Instruments Incorporated Semiconductor package with a wire bond mesh
US10204842B2 (en) 2017-02-15 2019-02-12 Texas Instruments Incorporated Semiconductor package with a wire bond mesh
US11121049B2 (en) 2017-02-15 2021-09-14 Texas Instruments Incorporated Semiconductor package with a wire bond mesh

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