WO2006115819A1

WO2006115819A1 - Electronic differential buses utilizing the null state for data transfer

Info

Publication number: WO2006115819A1
Application number: PCT/US2006/014017
Authority: WO
Inventors: Iu-Meng Tom Ho
Original assignee: Iota Technology, Inc.
Priority date: 2005-04-21
Filing date: 2006-04-14
Publication date: 2006-11-02

Abstract

An electronic data system comprising: a differential data system bus comprising true and complement signal wires; a write circuit for writing a Logic 0, a Logic 1 and a NULL state to the differential data system bus, wherein the NULL state is a state where Vdiff = 0; and a read circuit for reading the Logic 0, the Logic 1 and the NULL state from the the differential data system bus. In one embodiment, there are two differential data buses making a data bus pair, and at least one data bit is determined by an electronic state of the first bus and an electronic state of the second bus. In this embodiment, the write circuit is capable of placing each of the first and second data bus pairs in three electronic states for a total of nine possible electronic state combinations.

Description

ELECTRONIC DIFFERENTIAL BUSES UTILIZING THE NULL STATE FOR

DATA TRANSFER

BACKGROUND OF THE INVENTION 1. Field of the Invention

The invention in general relates to electronic signal transfer which can be used for differential data bus transfer or differential control signal transfer, and in particular such signals are capable of transferring data in a plurality of binary states. 2. Statement of the Problem Electronic signal buses comprising pairs of differential signal wires are well known. Most or all of such differential wire pairs are capable of transferring a single bit of data in each transfer or symbol which is apparent from the transmission Eye- diagram of the respective system. For speed, reliability and robustness in a noisy and un-predictable environment, differential signal buses are used to transfer the true and complementary data at the same time, where normally just one of the single signal wire is enough to transfer the data for a single-ended wire at a lower performance requirement; e.g. CML bus, XDR from Rambus, LVDS, BLVDS, M- LVDS, LVDM, SERDES, etc. Each of these differential signals consists of two signal wires and they are all transmitting one bit of data per symbol or per transfer. It seems a little wasteful in a system with a lot of parallel communications between components and modules; e.g. Network switches, Multi-core CPUs, graphic processors etc. to use two signal wires to transfer 1-bit of data or V∑ bit of data per signal wire.

For a serial system like a SerDes channel using differential buses where parallel data is serialized into data bit streams to be transferred on the designated serial data channels, it is also a little wasteful that each symbol or each transfer is only for one bit of data.

It is also well known that to improve speed and power of a single signal wire that it be replaced by a differential signal wires pair. The number of bus wires used will be 2x if single-ended signal wires are converted to differential signal wires pair directly to improve speed and reduce power consumption. Since a differential bus has two bus wires, it can have four binary logic states, "00", "01", "10" and "11". It uses the polarity of the voltage difference Vdiff between the two bus wires to determine a binary "0" or binary "1" data, e.g. +Vdiff = "Logic 1" and -Vdiff = "Logic 0". Currently, e.g. only the "01" (-Vdiff) and "10" (+Vdiff) states are used to represent a robust Logic-0, or a robust Logic-1. The "00" and "11" states, which can be both represented by "Vdiff = 0", are not being use to represent data. Herein, this state is called the NULL state. The voltage level of Vdiff is determined by the bus system specification. It is normally set to the smallest possible for the target system and technology. It is a huge challenge to circuit designers to utilize fractions of Vdiff to transmit more data on the differential bus especially at high speed. On single- ended or pseudo differential buses, circuit designers have been using multi-level signaling, like the PAM4 2-bit-per-clock Multi-level bus signaling from Rambus, to transfer more data on a bus. Multiple very accurate reference voltages are needed for these multi-level buses. To provide healthy Signal-to-Noise margin, the signaling specification will have to be relaxed and transfer speed slow down. In most cases, the multi-level signal would end up losing out to the simple bi-level signal bus. It is generally considered as unsafe circuit design practices to designers when multiple very accurate reference voltages are required to make a system work.

SUMMARY OF THE INVENTION

The invention provides a solution to the above problems by utilizing the NULL state of a differential signal bus to transmit more data on a differential bus pair. The invention recognizes that "Vdiff = 0", called a "NULL" state, which represents the "00" or "11" states or whenever the two bus wires of the differential bus have the same voltage, is a much more distinguishable state without requiring stable and accurate reference voltages at all. It is also immune to common mode offset noises and variations. Designers have long been using "Retum-to-Null" technique to speed up high speed data channel designs especially for Clock and Data Recovery. In such circuits, the basic three states transmit and receive circuitries are already there. Yet, the NULL state of a differential bus has not been used to represent data value for a differential bus system for data transfer. Hf the NULL state could be used, it would provide an extra half a bit of data.

Being able to transfer more than Vz bit of data per wire with minimum additional circuit design effort can be a big advantage in many aspects. It can help reduce the number of bus wires required both on chip or off chip wherever such differential buses are used. It can also help save transmission power. It can transfer more data using the same set of bus wire.

All the Current Mode Logic CML buses, ECL buses, Low-Voltage- Differential-Signaling LVDS type buses, etc. can be easily converted to support the three states transmission. These differential buses include; e.g. XDR from Rambus, BLVDS, M-LVDS, LVDM, SERDES, differential HSTL, differential SSTL, ECL, PECL, LVECL, etc. The differential buses can be used to transmit data and control signals on chip or off chip. They can also be point-to-point, multi-drops or multi- points. The differential buses can be of type fiber Optical, Capacitive Coupled, Inductive MC, Pulse Charged, Open-drain, Open-collector, Directly Driven, DC coupled, AC coupled etc. It can also be used in Single-Data-Rate (SDR), Double- Data-Rate (DDR), Quart-Data-Rate (QDR), Octal-Data-Rate (ODR or XDR by Rambus) etc. There are a lot of advantages to use the NULL state of a differential bus to transmit data or control signals. All the differential buses described above can all take advantage of the NULL state. With e.g. +Vdiff "1 state" and -Vdiff "0 state", and the NULL state, there are three states available for each differential bus transfer or symbol. Since data or control signal streams can be transmitted in serial or in parrallel, both can be used for three states data transfer. For a serial differential bus system like the SerDes type bus, each data transfer or symbol will have three states. Two related data symbols or data transfers, adjacent or not depending on the implementation architecture, can be combined together to produce nine states which would be enough to represent three bits of data with an extra state e.g. NULL-NULL left to be used for e.g. Un-driven, Violation, No-data etc. By utilizing three states on a differential bus, serial transfer throughput can be improved by as much as 1.5x at the same power consumption or lower depending on the specific implementation. Because of the additional NULL-NULL state available which normally can be used when the bus is not driven or no-data, the START bit = NOT(NULL-NULL) state and STOP bit = NULL-NULL state of a data stream can be saved. The 8B/10B type encoding/decoding algorithms to avoid run length problem can be avoided which further improve the data transmission efficiency. The three states differential bus could increase the data transfer rate by 1.667x for a byte oriented serial data stream. For a parallel differential bus system like the Rambus XDR data bus, two differential buses can be used to transmit three bits of data with an extra state e.g. NULL-NULL left to be used for e.g. Un-driven, Violation, No-data etc. Up to one third of the physical bus wires can be saved, and at least one third to one half of the data transmission power consumption depending on how the NULL state is being generated can be saved. On a 8 bit parallel differential bus system, a free parity is available when three pairs of three states differential buses are used or the extra bit can be used for the adjacent buses. Because of the additional NULL-NULL state available which normally can be used when the bus is not driven or no-data, the state of NOT(NULL-NULL) can always represent valid data or bus is driven. The NULL state of the two differential bus wires can be "Logical = 00"

"Logical = 11" "Logical = xx" when the voltage of both bus wires are equal or close to equal to cancel out neighboring or reflective noises. In the case of Inductive Inter-chip Communication, the NULL state is the state when the drivers on the two ends of the transmitting antenna are not being driven to transmit a Logic 0 or 1 , i.e. a ÷Vdiff or -Vdiff at the receiving antenna and receiver circuit. They could be not driven or just slightly driven in a way to cancel out the neighboring inductive noise during the NULL state. This same technique is also applicable to CML type bus, LVDS bus, ECL bus, Capacitive Pulsed Charged bus, etc. when the NULL state can be that the two different bus wires are in the same voltage or slightly different to cancel out neighboring and reflected noise. The idea is to achieve a close to zero Vdiff or Vi_D at the input of the receiver circuit. The invention provides a solution to the above problems by utilizing the NULL state of a differential signal bus to transmit more data on a differential bus pair, while each bus wire can be transmitting ³A bit of data rather than Y∑ bit of data. Numerous other features, objects, and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows two data eye patterns of Return-to-NULL differential bus for regular two states data transfer and the new three states data transfer; FIG. 2 is a block circuit diagram illustrating the architecture of a parallel

Three States Differential Bus Pair TSDBP;

FIG. 3 shows two sets of data eye patterns for transferring three bits serial data stream using Non-Return-to-Zero and Return-to-NULL modes;

FIG. 4 shows the waveforms of a Retum-to-NULL Three States Differential Bus Pair in all nine states;

FIG. 5 shows the waveforms of a Return-to-NULL Three States Differential Bus transferring different eight bits data streams;

FIG. 6 is a sample architecture of a Three States Differential Bus SerDes circuit for serial data transmitting and receiving; FIG. 7 is a sample architecture of a Three States Differential Bus Pair circuit for transmitting and receiving three bits width data stream;

FIG. 8 is a sample architecture of a Three States Differential Bus Pair circuit for receiving eight bits width data stream; and

FIG. 9 is a sample architecture of a Three States Differential Bus Pair circuit for transmitting eight bits width data stream.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 1. Overview

The invention relates to electronic differential buses. These differential buses can be used for both data and control signal transfer. The signal streams can be serial or parallel. These differential buses include differential True and Complement bus wires and components which can be direct drive, inductive coupled, AC coupled etc. These bus wires and components connect the corresponding drivers, receivers, and associated circuitries for transmitting and receiving data.

FIG. 1 shows two Retum-to-NULL (RN) data eye patterns (101 ) and (102).

The data eye pattern (101 ) is the existing RN differential bus eye pattern with two states. The data eye pattern (102) shows how the NULL state (103) can be added onto the existing two states data eye pattern to become a three states data eye pattern.

Since there are nine combinations or states can be formed when two of the three states data are combined together in serial or in parallel, the nine states are good enough to represent three data bits with one extra state left; e.g. NULL-NULL state, which can be used for e.g. Un-driven, Violation, No-data etc. By utilizing three states on a differential bus, serial transfer throughput can be improved by as much as 1.5x at the same power consumption or lower depending on the specific implementation. Because of the additional NULL-NULL state available which normally can be used when the bus is not driven or no-data, the START bit = NOT(NULL-NULL) state and STOP bit = NULL-NULL state of a data stream can be saved. The 8B/10B type encoding/decoding algorithms to avoid run length problem can be avoided which further improve the data transmission efficiency. The three states differential bus could increase the data transfer rate by 1.667x for a byte oriented serial data stream. For a parallel differential bus system, upto one third of the physical bus wires can be saved, and at least one third to one half of the data transmission power consumption depending on how the NULL state is being generated can be saved. On a 8 bit parallel differential bus system, a free parity is available when three pairs of three states differential buses are used or the extra bit can be used for the adjacent buses. Because of the additional NULL-NULL state available which normally can be used when the bus is not driven or no-data, the state of NOT(NULL-NULL) can always represent valid data or bus is driven.

FIG. 2 is a differential bus system like the LVDS buses. Each bus data bit is composed of True and a Complement bus wires (204). They would normally be terminated with a resistive network (203), which could be connected to a terminating voltage V_term- When True=1 and Complements, it is a Logic-1 (+Vdiff). When True=0 and Complements , it is a Logic-0 (-Vdiff). The NULL state (Vdiff = O) can be represented by True=Complement. In order to reduce power consumption and maintain a stable offset voltage, the NULL state for a differential bus can be slightly driven, "Undriven", driven to a Vt_erm voltage by the drivers or by the corresponding termination resistive network (203). For the common CML type differential output drivers (201 ), both True and Complement outputs can be driven to the same voltage with both of the output drivers being on at the same drawing the same amount of current. In the case of Inductive Inter-chip Communication, the NULL state is the state when the drivers on the two ends of the transmitting antenna are not being driven to transmit a Logic 0 or 1 , i.e. a +Vdiff or -Vdiff at the receiving antenna and receiver circuit. They could be not driven or just slightly driven in a way to cancel out the neighboring inductive noise during the NULL state. This same technique is also applicable to CML type bus, LVDS bus, ECL bus, Capacitive Pulsed Charged bus, etc. when the NULL state can be that the two different bus wires are in the same voltage or slightly different to cancel out neighboring and reflected noise. The idea is to achieve a close to zero Vdiff or VID at the input of the receiver circuit.

On the driving side of the Three States Differential Bus Pair TSDBP, three bits of data D{0,1 ,2} (206) are being encoded by the "TSDBP Encoder And Driver" (200) and the results being driven by TSDBP drivers (201 ) onto the bus pair BUS1 , and BUS2 (204) being synchronized and controlled by some "Send CNTL" (210) signals. If the data on the driving side comes encoded with SO and S1 pair (S01 , S11 , S02, S12), the "TSDBP Encoder And Driver" (200) may not be needed. If the bus driver (201) is open-drain or open-collector style, LogicO can be Open, Logid can be full strength Pulldown, and the NULL state can be both Open which is driven by the termination network or both Pulldown. On the receiving side of the TSDBP, the bus pair (204) are being sampled by the TSBR "Three States Bus Receiver" (202) controlled by some enable signals "en" (211 ). The "en" signals are synchronized with the "Send CNTL" (210) signals from the driving side through some internal circuits, e.g. CDR "Clock and Date Recovery", PLL "Phase Lock Loop" or DLL "Delay Lock Loop" circuits. Each TSBR (202) would normally generate two output SO and S1 representing the states on the BUS1 or BUS2, which will in turn be optionally decoded by the Three State Differential Bus Pair TSDBP Decoder (205) to generate the corresponding three data bits Y{0,1 ,2} (207). For a parallel data bus with bit width, e.g. 8 or 9, three pairs of TLBP circuits are needed. The ninth bit can be used as parity bit or other applications depending on the implementation details. Since the bit width for a parallel bus system may not always be divisible by three, e.g. 8, 16, 32, 64, etc. it is always possible that a pair of TSDBP circuit is taking care of only two bits of data. The Three States encoder and decoder circuitry can be simplified. For parallel bus system with bit width, e.g. 9, 18, 24, 36, 48, 54, 66, 72 etc., the TSDBP will provide the maximum savings of bus wire reduction.

The TSDBP can also be used to convert single-ended full swing signals to low swing high speed differential signals to improve speed and save power; e.g. three full swing signals with three individual signal wires can be converted to TSDBP three states differential bus pair with four signal wires. The cost is one wire out of every three signal. It would have taken six wires if the TSDBP is not used.

This is especially important for designing very high speed circuits with lower power.

The Three States Bus Receiver TSBR (202) consists of differential sense amplifiers outputing two signals SO and S1. Two pairs of such signals S01 , S11 , S02, S12 (212) are driven onto the TSDSP Decoder (205). An example of how the two output signals SO and S1 mapped for the decoder is shown in Table 1 :

SO S1 three states

0 0 NULL

0 1 logic one

1 0 loqic zero

Table 1

In Table 1 , the representation of the values of SO and S1 three States and the zeros "0" and ones "1" represent corresponding logic states. Depending on the bit width mode, differential sense amplifiers can be optimized to generate the corresponding SO, and S1 signals.

Two different samples of decoding maps from the S01 , S11 , S02, and S12 signals (212) for the TSDBP Decoder (205) to generate the YO₁ Y1, and Y2 signals are shown in Table 2 and Table 3.

S01 S11 S02 S12 YO Y1 Y2

0 X 0 X 0 0 0

0 X 1 0 0 0 1

0 X 1 1 0 1 0

1 0 0 X 0 1 1

1 0 1 0 1 0 0

1 0 1 1 1 0 1

1 1 0 X 1 1 0

1 1 1 X 1 1 1

1 1 1 1 (Extra State)

Table 2

S01 S11 S02 S12 YO Y1 Y2

0 0 0 0 (Error flag)

0 0 1 0 0 0 0

1 0 0 0 1 0 0

1 0 1 0 0 1 0

1 0 0 1 1 1 0

0 1 1 0 0 0 1

0 1 0 1 1 0 1

0 1 0 0 0 1 1

0 0 0 1 1 1 1 Table 3

The decoding maps are selected depending on circuit design considerations. The Extra states can be ignored or optimally used to simplify the design of the differential sense amplifiers, and the decoding circuits. FIG. 3 shows two sets of data eye patterns for transferring three bits serial data stream. The vertical lines (301 ) represent the clock ticks. The Three States Differential Bus Data Pair TSDP versions on the right side are significantly different from the (Prior Art) binary versions on the left. The TSDP needs two clock ticks to transfer three data bits while the regular differential bus would need all three clock ticks. For the NRZ versions (302) and (303), the NULL state is shown in the middle of VIH, and V|_L representing Vdiff = 0. For Return-to-Null RN mode (304) and (305) at the bottom, the differential buses are returned to NULL state after every transfer or clock tick.

FIG. 4 shows a parallel Three States Differential Bus Pair waveform with nine clock ticks. The first clock tick (405) shows the NULL-NULL state which could represent No-data on the bus in this case. Clock ticks 2 to 9 (403) represent the eight different states (404) of the three data bits represented in Table 3 above.

FIG. 5 shows how four different serial eight bit data streams can be transmitting using the Three States Differential Bus Data Pair in Retum-to-NULL mode. The first two clock ticks transmit a NULL-NULL pair. The third clock tick can be the start of data if NULL state is not used. The beginning of data can be signaled by the logic state of NOT(NULL). The first two data bits on clock ticks 3 and 4 are transmitted without the NULL state. The rest of clock ticks would transmit with NULL states. At clock ticks 9 and 10, a NULL-NULL state is used and it also signals the END of the serial data transfer.

FIG. 6 shows a sample architecture of a Three States Differential Bus SerDes circuit for serial data transmitting and receiving. The top row of circuits (916) are for transmitting and the bottom row of circuits (915) are for receiving. Circuits (913)(911 ) is for receiving parallel data (DIN) to be sent out to the TSDB channel (901 ). Circuit (909) is an alignment FIFO to prepare the parallel data (R) for the serializer register (920). Circuit (907) is the TSDBP Encoder to generate two sets of SO and S1 from the data bits YO, Y1 , Y2 for the synchronization Flip-flops (905) to be driven out by the Three States Differential Bus Driver TSD (903).

For the receiving ciruit, circuits (902) (904) are the Clock and Data recovery circuit and differential sense amplifiers to amplify and receive the high speed data stream. Circuit (906) decodes the SO, S1 signal pair to generate YO, Y1 , Y2 to the deserializer register (908). Circuit (910) is an alignment FIFO for the (PO) data for parallel transfer through the Output Register (912) and Parallel data out drivers (914).

FIG. 7 shows a sample architecture of a Three States Differential Bus Pair for a three bit data width data stream. The top row of circuits (1016) are for transmitting and the bottom row of circuits (1015) are for receiving. Circuits (1013)(1011 ) is for receiving parallel data (DIN) to be sent out to the TSDB channel (1001 ). Circuit (1009) is an alignment FIFO to prepare the parallel data (R) for the serializer register (1020). Circuit (1007) is the TSDBP Encoder to generate two sets of SO and S1 from the data bits YO, Y1 , Y2 for the synchronization Flip-flops (1005) to be driven out by the Three States Differential Bus Driver TSD (1003).

For the receiving ciruit, circuits (1002) (1004) are the Clock and Data recovery circuit and differential sense amplifiers to amplify and receive the high speed data stream. Circuit (1006) decodes the SO, S1 signal pair to generate YO, Y1 , Y2 to the deserializer register (1008). Circuit (1010) is an alignment FIFO for the (PO) data for parallel transfer through the Output Register (1012) and Parallel data out drivers (1014).

FIG. 8 and 9 show a sample architecture of a Three States Differential Bus Pair system for transmitting and receiving eight bit parallel data stream. Circuits on FIG. 9 (1216) are for transmitting and circuits on FIG. 8 (1115) are for receiving. Circuits (1213)(1211 ) is for receiving parallel data (DIN) to be sent out to the TSDB channel (1201 ). Circuit (1209) is an alignment FIFO to prepare the parallel data (R) for the serializer register (1220). Circuit (1207) is the TSDBP Encoder to generate two sets of SO and S1 from the data bits YO, Y1 , Y2 for the synchronization Flip- flops (1205) to be driven out by the Three States Differential Bus Driver TSD (1203). For the receiving ciruit, circuits (1102) (1104) are the Clock and Data recovery circuit and differential sense amplifiers to amplify and receive the high speed data stream. Circuit (1106) decodes the SO, S1 signal pair to generate YO, Y1 , Y2 to the deserializer register (1108). Circuit (1110) is an alignment FIFO for the (PO) data for parallel transfer through the Output Register (1112) and Parallel data out drivers (1114).

There have been described novel electronic differential bus architectures utilizing the NULL state of a true-and-complement differential bus to transfer three states per clock tick. Now that the various differential bus architectures using the three states to transfer have been described, those skilled in the electronics arts may make many variations. It should be understood that the particular embodiments shown in the drawings and described within this specification are for purposes of example and should not be construed to limit the invention, which will be described in the claims below. Further, it is evident that those skilled in the art may now make numerous uses and modifications of the specific embodiments described, without departing from the inventive concepts. It is also evident that the methods recited may, in many instances, be performed in a different order, or equivalent components may be used in the memories, and/or equivalent processes may be substituted for the various processes described. Consequently, the invention is to be construed as embracing each and every novel feature and novel combination of features present in and/or possessed by the invention herein described.

Claims

CLAIMSWhat is claimed is:

1. An electronic data system comprising: a differential data system bus comprising true and complement signal wires; a write circuit for writing a Logic 0, a Logic 1 and a NULL state to said differential data system bus, wherein said NULL state is a state where Vdiff = 0; and a read circuit for reading said Logic 0, said Logic 1 and said NULL state from the said differential data system bus.

2. An electronic data system as in claim 1 ; a first said differential data bus and a second said differential data bus, said first and second data busses making a data bus pair; and wherein said write circuit comprises a circuit for writing three or more data bits to said data bus pair, wherein at least one of said data bits is used to determine an electronic state of said first bus and an electronic state of said second bus; and said read circuit comprises a circuit for reading three or more data bits from said data bus pair, wherein at least one data bit is determined by an electronic state of said first bus and an electronic state of said second bus.

3. An electronic data system as in claim 2 wherein said write circuit is capable of placing seach of said first and second data bus pairs in three electronic states for a total of nine possible electronic state combinations.

4. An electronic data system as in claim 3 wherein one of said nine possible electronic state combinations is not used in directly recording said three data bits.

5. An electronic data system as in claim 1 wherein said read circuit includes a sense amplifier for sensing three electronic states and for outputting two logic signals.

6. An electronic data system as in claim 5 and further including two of said three state sense amplifiers and a decoder for decoding the four logic signals output by said sense amplifiers into three data bits.

7. An electronic data system as in claim 2 wherein said first and second differential data system buses are included in an integrated circuit and are separated by at least one other active integrated circuit element.

8. An electronic data system as in claim 1 wherein said system bus is selected from the group consisting of a serial bus and parallel bus.

9. An electronic data system as in claim 1 wherein said bus transmits data between continents or cities.

10. An electronic data system as in claim 1 wherein said differential data system bus transmits data between hardware systems.

11. An electronic data system as in claim 1 wherein said differential data system bus transmits data between circuit boards.

12. An electronic data system as in claim 1 wherein said differential data system bus transmits data between circuit modules, which are selected from the group consisting of: DRAM modules, CPU modules, DSP modules, GPU modules, ASIC modules, FPGA modules, and memory modules.

13. An electronic data system as in claim 1 wherein said differential data system bus transmits data between IC chips, which IC chips are selected from the group consisting of DRAMs, SRAMs, CPUs, Controllers, ASICs, FPGAs, PALs, and Gate Arrays.

14. An electronic data system as in claim 1 wherein said differential data system bus transmits data inside IC chips, which IC chips are selected from the group consisting of DRAMs, SRAMs, CPUs, Controllers, ASICs, FPGAs, PALs, and Gate Arrays.

15. An electronic data system as in claim 1 wherein said differential data system bus transmits data between circuit modules inside IC chips.

16. An electronic data system as in claim 1 wherein said differential data system bus is selected from the group consisting of: Single-Data-Rate, Double- Data-Rate, Quad-Data-Rate, Octal-Data-Rate and multiple Data Rate buses.

17. An electronic data system as in claim 1 wherein said differential data system bus is selected from the group consisting of: point-to-point buses, multi-drop buses and multi-point buses.

18. An electronic data system as in claim 1 wherein said differential data system bus is selected from the group consisting of capacitive coupled buses, inductive buses, pulse charged buses, open-drain buses, open-collector buses or directly driven buses.

19. An electronic data system as in claim 2 wherein said differential data system bus pair is selected from the group consisting of data buses, address buses, control buses, flag buses, and status buses.

20. An electronic data system as in claim 1 wherein said differential data system bus is used for serial data transfer.

21. An electronic data system as in claim 20 wherein said differential data system bus is used as a SerDes channel bus.

22. An electronic data system as in claim 20 wherein there are two of said serial transfer buses each capable of transferring said three states, said two serial transfer buses making a serial transfer bus pair and said states are combined together to obtain a total of nine possible electronic state combinations from which three of said data bits can be extracted.

23. An electronic data system as in claim 22 wherein one of said nine electronic states is a NULL-NULL state which can be used to represent No-data, and Un-driven.

24. An electronic data system as in claim 22 wherein the first two bits of the serial data stream are transferred without using the NULL state so that a

START bit can be skipped.

25. An electronic data system as in claim 22 wherein the END bit of the serial data stream is represented by the NULL-NULL state of the differential data pair after the last data pair being transferred.

26. A method of reading an electronic data system, said method comprising: reading three electronic states from each of 2N data system buses, where N is an integer; and decoding said electronic levels into 2N + N data bits.

27. A method as in claim 26 where said reading comprising reading three electronic states from each of two data system buses and said decoding comprises decoding said electronic states into three data bits.

28. A method of writing to an electronic data system, said method comprising: receiving 2N + N bits of data, where N is an integer; and writing said bits of data into three electronic levels in each of 2N data system buses.

29. A method as in claim 28 wherein said receiving comprises receiving three data bits and said writing comprises writing three electronic states into each of two data system buses.

30. A method for designing an electronic circuit in which two differential data system bus circuit sets are used to transmit 3 bits of data, said method comprising: designing each of said differential data system bus circuit sets to transmit three logic states; and designing said electronic circuit to transmit nine logic states over said two buses, which nine logic states represent three data bits.

31. A circuit design method as in claim 30 wherein one of said nine logic states is an extra state can be used as no-data, undriven, unprogrammed, unknown, violation, or privileged state.

32. A circuit design method as in claim 30 wherein the two differential data system bus pair circuit sets are placed in different locations due to layout and circuit design considerations.

33. A circuit design method as in claim 30 wherein said busses are selected from the group consisting of a serial bus system and parallel bus system.

34. A circuit design method as in claim 30 wherein said buses transmit data between continents or cities.

35. A circuit design method as in claim 30 wherein said differential data system buses transmit data between hardware systems.

36. A circuit design method as in claim 30 wherein said differential data system buses transmit data between circuit boards.

37. A circuit design method as in claim 30 wherein said differential data system buses transmit data between circuit modules, which can be DRAM modules, CPU modules, DSP modules, GPU modules, ASIC modules, FPGA modules, or memory modules.

38. A circuit design method as in claim 30 wherein said differential data system buses transmit data between IC chips, which can be DRAMs, SRAMs,

CPUs, Controllers, ASICs, FPGAs, PALs, or Gate Arrays.

39. A circuit design method as in claim 30 wherein said differential data system buses transmit data inside IC chips, which can be DRAMs, SRAMs, CPUs, Controllers, ASICs, FPGAs, PALs, or Gate Arrays.

40. A circuit design method as in claim 30 wherein said differential data system buses transmit data between circuit modules inside IC chips.

41. A circuit design method as in claim 30 wherein said differential data system buses are Single-Data-Rate, Double-Data-Rate, Quad-Data-Rate, Octal- Data-Rate or multiple Data Rate busses.

42. A circuit design method as in claim 30 wherein said differential data system buses are point-to-point buses, multi-drop buses or multi-point buses.

43. A circuit design method as in claim 30 wherein said differential data system buses are selected from the group consisting of optical buses, capacitive coupled buses, inductive buses, pulse charged buses, open-drain buses, open- collector buses or directly driven buses.

44. A circuit design method as in claim 30 wherein said differential data system buses are point-to-point buses, multi-drop buses or multi-point buses.

45. A circuit design method as in claim 30 wherein said two differential data system bus data circuit sets are selected from the group consisting of data buses, address buses, control buses, flag buses, and status buses.