WO2006113420A3 - System and method wherein conditional instructions unconditionally provide output - Google Patents

System and method wherein conditional instructions unconditionally provide output Download PDF

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Publication number
WO2006113420A3
WO2006113420A3 PCT/US2006/014042 US2006014042W WO2006113420A3 WO 2006113420 A3 WO2006113420 A3 WO 2006113420A3 US 2006014042 W US2006014042 W US 2006014042W WO 2006113420 A3 WO2006113420 A3 WO 2006113420A3
Authority
WO
WIPO (PCT)
Prior art keywords
target
condition
output
satisfied
instruction
Prior art date
Application number
PCT/US2006/014042
Other languages
French (fr)
Other versions
WO2006113420A2 (en
Inventor
Thomas Andrew Sartorius
James Norris Dieffenderfer
Jeffrey Todd Bridges
Kenneth Alan Dockser
Michael Scott Mcilvaine
Rodney Wayne Smith
Original Assignee
Qualcomm Inc
Thomas Andrew Sartorius
James Norris Dieffenderfer
Jeffrey Todd Bridges
Kenneth Alan Dockser
Michael Scott Mcilvaine
Rodney Wayne Smith
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc, Thomas Andrew Sartorius, James Norris Dieffenderfer, Jeffrey Todd Bridges, Kenneth Alan Dockser, Michael Scott Mcilvaine, Rodney Wayne Smith filed Critical Qualcomm Inc
Priority to EP06750153.6A priority Critical patent/EP1869547B1/en
Priority to BRPI0610222-0A priority patent/BRPI0610222A2/en
Priority to CN2006800203461A priority patent/CN101194225B/en
Priority to JP2008506733A priority patent/JP2008537231A/en
Publication of WO2006113420A2 publication Critical patent/WO2006113420A2/en
Publication of WO2006113420A3 publication Critical patent/WO2006113420A3/en
Priority to IL186632A priority patent/IL186632A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.
PCT/US2006/014042 2005-04-14 2006-04-14 System and method wherein conditional instructions unconditionally provide output WO2006113420A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP06750153.6A EP1869547B1 (en) 2005-04-14 2006-04-14 System and method wherein conditional instructions unconditionally provide output
BRPI0610222-0A BRPI0610222A2 (en) 2005-04-14 2006-04-14 system and method in which conditional statements give unconditional output
CN2006800203461A CN101194225B (en) 2005-04-14 2006-04-14 System and method wherein conditional instructions unconditionally provide output
JP2008506733A JP2008537231A (en) 2005-04-14 2006-04-14 System and method in which conditional instructions provide output unconditionally
IL186632A IL186632A (en) 2005-04-14 2007-10-14 System and method wherein conditional instructions unconditionally provide output

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/106,803 2005-04-14
US11/106,803 US7624256B2 (en) 2005-04-14 2005-04-14 System and method wherein conditional instructions unconditionally provide output

Publications (2)

Publication Number Publication Date
WO2006113420A2 WO2006113420A2 (en) 2006-10-26
WO2006113420A3 true WO2006113420A3 (en) 2006-12-21

Family

ID=37016156

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/014042 WO2006113420A2 (en) 2005-04-14 2006-04-14 System and method wherein conditional instructions unconditionally provide output

Country Status (9)

Country Link
US (1) US7624256B2 (en)
EP (1) EP1869547B1 (en)
JP (3) JP2008537231A (en)
KR (1) KR100953856B1 (en)
CN (1) CN101194225B (en)
BR (1) BRPI0610222A2 (en)
IL (1) IL186632A (en)
TW (1) TWI317906B (en)
WO (1) WO2006113420A2 (en)

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US7624256B2 (en) * 2005-04-14 2009-11-24 Qualcomm Incorporated System and method wherein conditional instructions unconditionally provide output
US8078846B2 (en) * 2006-09-29 2011-12-13 Mips Technologies, Inc. Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated
CN101324838A (en) * 2008-07-31 2008-12-17 华为技术有限公司 Method and apparatus for executing instruction
US8140780B2 (en) * 2008-12-31 2012-03-20 Micron Technology, Inc. Systems, methods, and devices for configuring a device
JP5072889B2 (en) * 2009-03-16 2012-11-14 株式会社東芝 Precondition generation apparatus and postcondition generation apparatus, and methods thereof
GB2480285A (en) * 2010-05-11 2011-11-16 Advanced Risc Mach Ltd Conditional compare instruction which sets a condition code when it is not executed
GB2484654B (en) * 2010-10-12 2013-10-09 Advanced Risc Mach Ltd Conditional selection of data elements
US9032189B2 (en) * 2011-04-07 2015-05-12 Via Technologies, Inc. Efficient conditional ALU instruction in read-port limited register file microprocessor
US9292470B2 (en) 2011-04-07 2016-03-22 Via Technologies, Inc. Microprocessor that enables ARM ISA program to access 64-bit general purpose registers written by x86 ISA program
US9146742B2 (en) 2011-04-07 2015-09-29 Via Technologies, Inc. Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA
US9317288B2 (en) 2011-04-07 2016-04-19 Via Technologies, Inc. Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
US8924695B2 (en) * 2011-04-07 2014-12-30 Via Technologies, Inc. Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor
US9898291B2 (en) 2011-04-07 2018-02-20 Via Technologies, Inc. Microprocessor with arm and X86 instruction length decoders
US9141389B2 (en) 2011-04-07 2015-09-22 Via Technologies, Inc. Heterogeneous ISA microprocessor with shared hardware ISA registers
US9244686B2 (en) 2011-04-07 2016-01-26 Via Technologies, Inc. Microprocessor that translates conditional load/store instructions into variable number of microinstructions
US8880851B2 (en) 2011-04-07 2014-11-04 Via Technologies, Inc. Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
US9176733B2 (en) 2011-04-07 2015-11-03 Via Technologies, Inc. Load multiple and store multiple instructions in a microprocessor that emulates banked registers
US9274795B2 (en) 2011-04-07 2016-03-01 Via Technologies, Inc. Conditional non-branch instruction prediction
US9128701B2 (en) 2011-04-07 2015-09-08 Via Technologies, Inc. Generating constant for microinstructions from modified immediate field during instruction translation
US9378019B2 (en) 2011-04-07 2016-06-28 Via Technologies, Inc. Conditional load instructions in an out-of-order execution microprocessor
US9336180B2 (en) 2011-04-07 2016-05-10 Via Technologies, Inc. Microprocessor that makes 64-bit general purpose registers available in MSR address space while operating in non-64-bit mode
US8880857B2 (en) 2011-04-07 2014-11-04 Via Technologies, Inc. Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor
US9043580B2 (en) 2011-04-07 2015-05-26 Via Technologies, Inc. Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)
US9645822B2 (en) 2011-04-07 2017-05-09 Via Technologies, Inc Conditional store instructions in an out-of-order execution microprocessor
JP6422381B2 (en) * 2015-03-18 2018-11-14 ルネサスエレクトロニクス株式会社 Processor, program code conversion device and software
JP7081922B2 (en) * 2017-12-28 2022-06-07 株式会社バンダイナムコエンターテインメント Programs, game consoles and methods for running games
CN111209039B (en) * 2018-11-21 2022-08-02 展讯通信（上海）有限公司 Instruction processing method and device

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US20050066151A1 (en) * 2003-09-19 2005-03-24 Sailesh Kottapalli Method and apparatus for handling predicated instructions in an out-of-order processor

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Also Published As

Publication number Publication date
WO2006113420A2 (en) 2006-10-26
KR20070121842A (en) 2007-12-27
EP1869547A2 (en) 2007-12-26
TW200705266A (en) 2007-02-01
TWI317906B (en) 2009-12-01
BRPI0610222A2 (en) 2010-06-08
US7624256B2 (en) 2009-11-24
CN101194225B (en) 2013-10-23
EP1869547B1 (en) 2016-09-21
IL186632A (en) 2012-04-30
US20060236078A1 (en) 2006-10-19
JP2012212433A (en) 2012-11-01
JP6009608B2 (en) 2016-10-19
JP2015164048A (en) 2015-09-10
IL186632A0 (en) 2008-01-20
JP2008537231A (en) 2008-09-11
CN101194225A (en) 2008-06-04
KR100953856B1 (en) 2010-04-20

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