WO2006107356A3 - Method of adding fabrication monitors to integrated circuit chips - Google Patents

Method of adding fabrication monitors to integrated circuit chips Download PDF

Info

Publication number
WO2006107356A3
WO2006107356A3 PCT/US2005/047083 US2005047083W WO2006107356A3 WO 2006107356 A3 WO2006107356 A3 WO 2006107356A3 US 2005047083 W US2005047083 W US 2005047083W WO 2006107356 A3 WO2006107356 A3 WO 2006107356A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
shapes
monitors
circuit chips
fill
Prior art date
Application number
PCT/US2005/047083
Other languages
French (fr)
Other versions
WO2006107356A2 (en
Inventor
James W Adkisson
Greg Bazan
John M Cohn
Matthew S Grady
Thomas G Sopchak
David P Vallett
Original Assignee
Ibm
James W Adkisson
Greg Bazan
John M Cohn
Matthew S Grady
Thomas G Sopchak
David P Vallett
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm, James W Adkisson, Greg Bazan, John M Cohn, Matthew S Grady, Thomas G Sopchak, David P Vallett filed Critical Ibm
Priority to JP2008504019A priority Critical patent/JP5052501B2/en
Priority to EP05855609.3A priority patent/EP1869595B1/en
Priority to CN2005800492611A priority patent/CN101147148B/en
Publication of WO2006107356A2 publication Critical patent/WO2006107356A2/en
Publication of WO2006107356A3 publication Critical patent/WO2006107356A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design (300) of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shaped (305) between the adjacent integrated circuit elements based on fill shape rules (310), the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes (320) of a monitor structure (315) in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.
PCT/US2005/047083 2005-04-04 2005-12-22 Method of adding fabrication monitors to integrated circuit chips WO2006107356A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008504019A JP5052501B2 (en) 2005-04-04 2005-12-22 Method for adding a manufacturing monitor to an integrated circuit chip
EP05855609.3A EP1869595B1 (en) 2005-04-04 2005-12-22 Method of adding fabrication monitors to integrated circuit chips
CN2005800492611A CN101147148B (en) 2005-04-04 2005-12-22 Method of adding fabrication monitors to integrated circuit chips

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/907,494 2005-04-04
US10/907,494 US7240322B2 (en) 2005-04-04 2005-04-04 Method of adding fabrication monitors to integrated circuit chips

Publications (2)

Publication Number Publication Date
WO2006107356A2 WO2006107356A2 (en) 2006-10-12
WO2006107356A3 true WO2006107356A3 (en) 2007-11-22

Family

ID=37072118

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/047083 WO2006107356A2 (en) 2005-04-04 2005-12-22 Method of adding fabrication monitors to integrated circuit chips

Country Status (6)

Country Link
US (3) US7240322B2 (en)
EP (1) EP1869595B1 (en)
JP (1) JP5052501B2 (en)
CN (1) CN101147148B (en)
TW (1) TWI362598B (en)
WO (1) WO2006107356A2 (en)

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Also Published As

Publication number Publication date
TWI362598B (en) 2012-04-21
CN101147148A (en) 2008-03-19
CN101147148B (en) 2010-07-07
EP1869595B1 (en) 2013-08-07
TW200705229A (en) 2007-02-01
WO2006107356A2 (en) 2006-10-12
JP2008535239A (en) 2008-08-28
US20070160920A1 (en) 2007-07-12
EP1869595A4 (en) 2009-12-16
US7240322B2 (en) 2007-07-03
EP1869595A2 (en) 2007-12-26
US7323278B2 (en) 2008-01-29
JP5052501B2 (en) 2012-10-17
US20060225023A1 (en) 2006-10-05
US20080017857A1 (en) 2008-01-24
US7620931B2 (en) 2009-11-17

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