WO2006056473A2 - Improved matched-impedance surface-mount technology footprints - Google Patents
Improved matched-impedance surface-mount technology footprints Download PDFInfo
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- WO2006056473A2 WO2006056473A2 PCT/EP2005/012691 EP2005012691W WO2006056473A2 WO 2006056473 A2 WO2006056473 A2 WO 2006056473A2 EP 2005012691 W EP2005012691 W EP 2005012691W WO 2006056473 A2 WO2006056473 A2 WO 2006056473A2
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- Prior art keywords
- signal
- vias
- arrangement
- circuit board
- pad
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
- H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
- H01R13/6461—Means for preventing cross-talk
- H01R13/6471—Means for preventing cross-talk by special arrangement of ground and signal conductors, e.g. GSGS [Ground-Signal-Ground-Signal]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
- H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
- H01R13/6473—Impedance matching
- H01R13/6477—Impedance matching by variation of dielectric properties
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3405—Edge mounted components, e.g. terminals
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
- H05K2201/09163—Slotted edge
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
- H05K2201/0919—Exposing inner circuit layers or metal planes at the side edge of the PCB or at the walls of large holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09845—Stepped hole, via, edge, bump or conductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10287—Metal wires as connectors or conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/1034—Edge terminals, i.e. separate pieces of metal attached to the edge of the PCB
Definitions
- the invention relates to electrical connector / circuit board systems.
- the invention relates to methodologies for defining surface-mount-technology footprints on such circuit boards wherein vias are disposed relative to one another in a via arrangement that differs from the pad arrangement and provides for a routing density of electrically conductive traces disposed on the substrate that is greater than the routing density the circuit board would have if the signal via arrangement were the same as the signal pad
- an electrical component such as an electrical connector, for example, may include a plurality of electrically-conductive contacts, the terminal portions of which may be arranged in a matrix of rows and columns, for example.
- the contacts L may be signal conductors or ground conductors, and may be arranged along columns in a signal-signal-ground arrangement. Adjacent signal contacts may form differential signal pairs, though the signal contacts may be single-ended signal conductors.
- Such a component may include any combination of differential signal pairs and single-ended signal conductors.
- Terminal portions of the contacts may be received by a substrate, such as a backplane or printed circuit board.
- the contact leads may be terminated in plated through-holes (PTHs).
- PTH technology is a method of PCB manufacture whereby traces on one layer may be electrically connected through previously-drilled through- holes to traces on another layer using a plating method.
- the footprint, or arrangement of through-holes must align with the arrangement of the terminal portions of the leads so that the terminal portions of the leads may be received by corresponding through-holes in the substrate.
- Plated through-holes constrain routing density ⁇ i.e., the number of traces that may be disposed onto the surface of a board layer). Plated through-holes, therefore, tend to increase the number of board layers necessary to provide required routing. Increasing the number of layers, however, increases board thickness and manufacturing cost. It also increases capacitance due to the increased number of ground planes. Increasing capacitance decreases impedance. Consequently, the board impedance may be driven lower than the component impedance, which creates a undesirable discontinuity between the board impedance and the component impedance. It is desirable that the component impedance and the board impedance be matched as nearly as possible to avoid signal reflections that occur because of the impedance discontinuity. Such reflections created unwanted noise that degrades signal integrity.
- an electrical component may be mounted to a circuit board using surface mount technology (SMT).
- SMT involves electrically connecting terminal ends of the contacts to the surface of the substrate by electrically connecting each terminal end to a respective SMT pad located on the surface of the substrate.
- the terminal ends of the contacts which may include electrically-conductive solder balls, for example, are typically soldered to the pads.
- the SMT pads are typically electrically connected to vias that extend between the layers of the board and electrically connect SMT pads or traces on one layer to traces on another layer.
- FIG. 1 depicts a typical SMT connector footprint comprising a plurality of SMT pads P arranged in a pad arrangement and a plurality of vias V arranged in a via arrangement.
- Each of the vias V is electrically connected to a respective one of the SMT pads P.
- the SMT pads P and vias V may be arranged in a so-called “dog-bone” pattern, as shown.
- a "dog bone” may include an SMT pad P, a via V, a via pad VP, and an electrically conductive via trace VT that electrically connects the via pad and the SMT pad.
- vias and SMT pads need not be arranged in such a dog-bone pattern.
- an SMT pad may overlap partially or completely with a corresponding via pad such that there is a direct connection between the SMT pad and the via pad. Such a configuration is typically referred to as "via-in-pad.”
- the SMT pads and vias may be arranged into rows and columns. As shown in
- FIG. 1 columns extend along the horizontal direction, perpendicular to the board edge E. Rows extend along the vertical direction, parallel to the board edge E.
- the spacing between the centerlines of adjacent rows may be referred to as the row pitch P R .
- the spacing between the centerlines of adjacent columns may be referred to as the column pitch Pc.
- the SMT pads P and vias V may be ground conductors or signal conductors.
- Signal conductors may be used in either single-ended or differential signal transmission.
- High- speed (i.e., greater than 1 GHz) connectors typically use differential signal pairs for signal transmission.
- each signal conductor may be paired with an adjacent signal conductor.
- a respective ground conductor may be disposed between adjacent pairs of signal conductors.
- ground conductors may be included to decrease cross-talk among the signal conductors, and to promote impedance-matching.
- the pad arrangement depicted in FIG. 1 may be the same as the lead arrangement in the component to be surface-mounted onto the board.
- the SMT pads may be arranged into rows and columns just as the terminal portions of the leads are arranged into rows and columns.
- the row pitch PR and column pitch Pc of the pad arrangement may be the same as the row pitch and column pitch of the lead arrangement.
- the via arrangement may be the same as the pad arrangement. That is, the vias V may be arranged into rows and columns, for example, just as the SMT pads P are arranged into rows and columns. Further, the row pitch P VR and column pitch Pvc of the via arrangement may be the same as the row pitch PR and column pitch Pc of the pad arrangement.
- a horizontal routing channel i.e., the board space between adjacent columns
- a typical connector having a 3 mm column pitch may be wide enough to include two pairs of traces.
- a vertical routing channel i.e., the board space between adjacent rows
- a first trace must be disposed between a first pair of rows and a second trace must be disposed between a different pair of rows. It is usually desirable, however, to have the traces associated with a signal pair disposed as closely to each other as possible.
- SMT connector footprints for a substrate, such as a printed circuit board, for example.
- the substrate may be any substrate that is adapted to receive an electrical component having an arrangement of terminal lead portions (i.e., the terminal portions of the leads).
- Such a footprint may include an arrangement of electrically-conductive SMT pads.
- a respective SMT pad may be associated with each terminal lead portion.
- the SMT pads may be arranged in an arrangement that corresponds to the lead arrangement (i.e., the arrangement of the terminal lead portions).
- the footprint may also include an arrangement of electrically-conductive vias. Each via may be electrically connected to a respective one of the SMT pads.
- the vias may be arranged in an arrangement that differs from the pad arrangement (and, therefore, from the lead arrangement).
- the vias may be arranged in any of a number of ways that increase routing density of traces on the substrate, while limiting cross-talk among signal conductors and providing for matched impedance between the connector and the substrate.
- the via arrangement may be altered, i.e., the vias may be moved relative to one another, to achieve a desired routing density on a layer of the board. Increasing the routing density may decrease the number of board layers, thereby decreasing capacitance and increasing impedance.
- ground vias and signal vias may be arranged with respect to one another in such a manner as to affect impedance and cross-talk. The distance between the signal conductors that form a pair may affect the impedance between them. The distance between the pair and an associated ground conductor may also affect impedance.
- the via arrangement may be also be altered to achieve an acceptable level of cross-talk among adjacent signal conductors. Thus, according to the invention, the via arrangement may be altered to achieve a desired balance between routing density, impedance-matching, and cross-talk.
- Rows of adjacent SMT pads may be in a signal-signal-ground configuration. Such an arrangement may be suitable for edge card applications, for example.
- the pads may be coupled to respective vias or plated through-holes arranged in columns. Adjacent columns of vias or plated through-holes, however, may be staggered such that a ground via or through-hole of one column may be adjacent to a signal via or plated through-hole of an adjacent column. In this way, for example, unstaggered horizontal rows of SMT pads may break-out to staggered vertical columns of vias or plated through-holes.
- a circuit board may include a substrate, a plurality of electrically conductive pads disposed on the substrate in a row, a first ground via and a first signal via arranged in a first column, and a second ground via and a second signal via arranged in a second column, the second column adjacent to the first column.
- Each via of the first and second columns may be electrically connected to a respective one of the plurality of pads in the row.
- the first ground via may be adjacent to the second signal via.
- Each of the first and second ground vias may be a plated through hole.
- Each of the first and second signal vias may be a plated through hole.
- the plurality of pads may be arranged in repeating three-pad cells of signal, signal, ground.
- the first ground contact and the second ground contact may form a first diagonal with respect to at least one of the first and second columns.
- the first signal contact and the second signal contact may form a second diagonal with respect to at least one of the first and second columns.
- the first diagonal may be adjacent to the second diagonal.
- Electrical performance (i.e. t impedance, cross-talk, and insertion loss) of SMT connector footprints can be optimized by varying certain parameters of the footprint.
- Example of such parameters include relative position of signal and ground via holes, the size of the drilled holes, the size of the pads, etc.
- Routing density may also be optimized for eliminating layers in the PCB (to improve impedance-matching and reduce manufacturing cost). Reducing via hole size increases available routing channel width, which may be used for routing more or wider traces.
- SMT connector footprints may be designed for any application that uses a high ⁇ speed, high-density SMT connector (e.g., SATA, SAS, DDR, PCI-Express, backplane, etc.).
- a high ⁇ speed, high-density SMT connector e.g., SATA, SAS, DDR, PCI-Express, backplane, etc.
- the hole diameter and signal/ground configurations are determined, a number of parameters remain that can be optimized to maximize the footprint performance. These parameters include via pad size, via anti-pad size and shape, and via stub length.
- FIG. 1 depicts a substrate having a typical SMT connector footprint disposed thereon.
- FIGs. 2A and 2B illustrate modifications that may be made to the footprint of
- FIG. 1 in accordance with the invention.
- FIGs. 3A and 3B illustrate modifications that may be made to the footprint of FIG. 1 in accordance with the invention.
- FIG. 4A depicts a partial view of an example embodiment of a prior art SMT connector footprint.
- FIGs. 4B-4D depict partial views of example embodiments of SMT connector footprints in accordance with of the invention to show optimization of column pitch and distance between vias of adjacent rows, and the rotation of the vias within and between columns.
- FIGs. 5 A and 5B depict an example connector footprint.
- FIGs. 6A and 6B depict a footprint wherein the via arrangement depicted in
- FIGs. 5 A and 5B has been altered within a column.
- FIGs. 7A and 7B depict a footprint wherein pads from different pad columns are coupled to vias in the same via column.
- FIGs. 8A and 8B depict an example connector footprint.
- FIGs. 9A and 9B depict a footprint wherein the via arrangement depicted in
- FIGs. 8A and 8B has been altered within a column.
- FIGs. 1OA and 1OB depict a footprint wherein the via arrangement depicted in FIGs. 8A and 8B has been altered to halve the via column pitch.
- FIGs. 1 IA and 1 IB depict a footprint wherein pads from different pad columns are coupled to vias in the same via column.
- FIGs. 12A and 12B depict a footprint that provides for double-density routing with split signal pairs.
- FIGs. 14A and 14B depict a footprint wherein two columns of pads are coupled to a single column of vias.
- FIGs. 16A and 16B depict a footprint that provides for two-and-a-half times routing density.
- FIGs. 17 - 21 illustrate example modifications that may be made to via arrangements in accordance with the invention.
- FIGs. 22A and 22B depict an example footprint.
- FIGs. 23A-C depict a footprint with signal pairs redirected to vias in different columns.
- FIGs. 24A and 24B depict a footprint that provides for double-density routing.
- FIGs. 25 A and 25B depict a footprint that provides for one-and-a-half times routing density.
- FIGs. 26A and 26B depict a footprint that provides for one-and-a-half times routing density.
- FIGs. 27A and 27B depict a footprint that provides for serpentine routing.
- FIGs. 28A and 28B depict a footprint that provides for double-density routing.
- FIGs. 28C depicts a footprint that provides for two-and-a-half times routing density.
- FIG. 29 depicts an example footprint wherein pads are arranged in rows, and corresponding vias are arranged in staggered columns.
- FIGs. 3OA and 3OB illustrate various ground via hole sizes for an arrangement of signal conductor vias.
- FIGs. 31 A and 3 IB illustrate various ground via hole sizes for another arrangement of signal conductor vias.
- FIGs. 32A and 32B provide example plots of differential impedance and cross- talk, respectively, for various ground via hole sizes.
- FIGs. 2A and 2B depict partial views of example embodiments of SMT connector footprints in accordance with an aspect of the invention.
- the via arrangement depicted in FIG. 1 may be modified in accordance with the embodiments depicts in FIGs. 2A and 2B to increase routing density, match impedance, and improve electrical performance of the system.
- FIG. 2A depicts first and second ground conductor vias G 1 and G 2 and first and second signal conductor vias S 1 and S 2 disposed in a linear arrangement, such as a column or row.
- the signal conductor vias S 1 and S 2 may be used for either single-ended or differential signal transmission.
- the pitch A between the adjacent signal conductor vias S 1 and S 2 may be less than the pitch A 1 between the signal conductor via S 1 and the ground conductor via G 1 that is adjacent to the signal conductor via S 1 .
- the pitch A between the signal conductor vias S 1 and S 2 may be less than the pitch A 2 between the signal conductor via S 2 and the ground conductor via G 2 that is adjacent to the signal conductor via S 2 .
- the pitch A 1 may be the same as, or different from, the pitch A 2 .
- the actual distances A, A 1 , and A 2 may be chosen to achieve a desired routing density and/or to optimize signal transmission performance through better impedance-matching and cross-talk reduction.
- FIG. 2B depicts first and second signal conductor vias S 1 , S 2 and a single ground conductor via G 3 disposed in a linear arrangement, such as a column or row.
- the signal conductor vias S 1 , S 2 may be used for either single-ended or differential signal transmission.
- the pitch A between the adjacent signal conductor vias S 1 and S 2 may be less than the pitch A 3 between the signal conductor via S 1 and the ground conductor via G 3 that is adjacent to the signal conductor via S 1 .
- the actual distances A and A 3 may be chosen to achieve a desired routing density, while optimizing signal transmission performance through better impedance-matching and cross-talk reduction.
- FIGs. 3Aand 3B depict partial views of example embodiments of SMT connector footprints in accordance with an aspect of the invention.
- the via arrangement depicted in FIG. 1 may be modified in accordance with the embodiments depicted in FIGs. 3A and 3B to improve routing density and/or electrical performance of the system.
- FIG. 3A depicts first and second ground conductor vias G 1 , G 2 and first and second signal conductor vias S 1, S 2 .
- the signal conductor vias S 1 , S 2 may be used in either single-ended or differential signal transmission.
- the signal conductor vias S 1 and S 2 may be staggered relative to a centerline C along which the vias are disposed. That is, the signal conductor via S 1 may be offset by a distance B 1 from the centerline C in a first direction, and the signal conductor via S 2 may be offset by a distance B 2 from the centerline C in a second direction.
- the second direction may be opposite the first direction, as shown in FIG. 3 A, or both signal vias may be offset from the centerline C in the same direction.
- the offset B 1 may be the same as, or different from, the offset B 2 .
- the ground conductor vias G 1 and G 2 may be located on the centerline C, as shown.
- the signal conductor vias S 1 and S 2 may be staggered with respect to each other in such a way as to be symmetrical with respect to the ground conductor vias G 1 and G 2 adjacent, respectively, to the signal conductor vias S 1 and S 2 .
- the actual distances B 1 , and B 2 may be chosen to achieve a desired routing density, while optimizing signal transmission performance through better impedance-matching and cross-talk reduction.
- the pitch D (taken along the centerline C) between the adjacent signal conductor vias S 1 and S 2 may be less than the pitch D 1 between the signal conductor via S 1 and the ground conductor via G 1 that is adjacent to the signal conductor via S 1 .
- the pitch D may be less than the pitch D 2 between the signal conductor via S 2 and the ground conductor via G 2 that is adjacent to the signal conductor via S 2 .
- the pitch D 1 may be the same as, of different from, the pitch D 2 .
- the actual distances D, D 1 , and D 2 may be chosen to achieve a desired routing density, while optimizing signal transmission performance through better impedance-matching and cross-talk reduction.
- FIG. 3B depicts first and second signal conductor vias S 1 , S 2 and a single ground conductor via G 3 .
- the signal conductor via S 1 may be offset by a distance B 1 from the centerline C in a first direction
- the signal conductor via S 2 may be offset by a distance B 2 from the centerline C in a second direction.
- the second direction may be opposite the first direction, as shown in FIG. 3B, or both signal vias may be offset from the centerline C in the same direction.
- the offset B 1 may be the same as, or different from, the offset B 2 .
- the ground conductor via G 3 may be located on the centerline C, as shown.
- the pitch D (taken along the centerline C) between the adjacent signal conductor vias S 1 and S 2 may be less than the pitch D 3 between the signal conductor via S 1 and the ground conductor via G 3 that is adjacent to the signal conductor via S 1 .
- the actual distances D and D 3 may be chosen to achieve a desired routing density, while optimizing signal transmission performance through better impedance-matching and cross-talk reduction.
- FIG. 4A depicts a via arrangement having a fixed column pitch y. That is, adjacent columns are spaced apart from one another by a distance y. Each column includes a plurality of vias arranged in a linear array in a ground-signal-signal configuration. The vias may be equally spaced from one another.
- each ground via may be spaced apart from its adjacent signal via by a distance d, and adjacent signal vias may also be spaced apart from one another by a distance d.
- adjacent columns may be staggered relative to one another. That is, a column may be offset from an adjacent column by a distance e.
- the offset distance e may be the same as the distance d (i.e., one row pitch). It should be understood, however, that the offset may more or less than one row pitch (i.e., the offset distance e need not be the same as the distance d).
- FIG. 4B illustrates optimization of column pitch distance and distance between vias of adjacent rows. It should be understood that the methodologies of the invention may be useful for optimizing signal integrity and routing density, even if neither is always maximized.
- the signal conductor vias may be moved relative to one another along the centerlines (as described above in connection with FIGs. 2A and 2B, for example). Moving the vias nearer to one another provides for increased routing density between adjacent rows.
- the values Of D 1 , D 2 , and D which may be chosen to optimize routing density between rows, may be the same or different from one another.
- the signal conductor vias may also be offset from their respective centerlines (as described above in connection with FIGs. 3A and 3B, for example).
- the values Of B 1 and B 2 which may be chosen to achieve a desired limit on cross-talk, may be the same or different from one another.
- Adjacent columns may be moved closer together. That is, the distance Y between column centerlines as depicted in FIG. 4B may be greater than the distance y between column centerlines as depicted in FIG. 4A. This provides for an increase in routing density between adjacent columns by widening the routing channels that exist to the left and right (as shown in FIG. 4B) of the via arrangement. That is, the distance A 1 shown in FIG. 4A may be greater than the distance A 2 shown in FIG. 4B.
- the values of Y and Y 1 as well as the amount of offset E between adjacent columns, may be chosen to balance the impedance, cross-talk, and routing density requirements of the system.
- two adjacent ground vias such as the circumscribed ground vias, for example, may be replaced by a single ground via
- FIGs. 4C and 4D illustrate rotation of vias within and between columns.
- each signal conductor via may be offset from its respective centerline in a direction opposite the direction it is offset in the arrangement depicted in FIG. 4B.
- each signal pair may be rotated 90° around its centerpoint, as compared with the arrangement depicted in FIG. 4B.
- FIG. 4D depicts an arrangement wherein only some of the pairs have been rotated relative to the arrangement depicts in FIG. 4B.
- the arrangement of ground vias is the same as the arrangement of ground vias depicted in FIGs 4A and 4B.
- FIGs. 5A and 5B depict an example connector footprint.
- FIG. 5A depicts a top- layer configuration including two columns of vias V and pads P in a dog-bone configuration.
- the row pitch P VR of the via arrangement is the same as the row pitch P R of the SMT pad arrangement.
- the column pitch Pvc of the via arrangement is the same as the column pitch P c of the SMT pad arrangement.
- the offset Ovc between adjacent columns of vias is the same as the offset Oc between adjacent columns of SMT pads.
- the column pitch Pc might be about 2 mm in such a footprint.
- the via arrangement is the same as the pad arrangement.
- FIG. 5B depicts the arrangement of vias V on an inner layer, including an example arrangement of via anti-pads AP. As shown in FIG. 5B, one pair of traces T may be routed along the routing channel between adjacent columns. Via anti-pads would be disposed on a ground layer, and not on the same layer(s) as the traces.
- FIGs. 6A and 6B depict a footprint wherein a via arrangement such as depicted in FIGs. 5 A and 5B has been altered within a column in a manner such as described above in connection with FIGs. 2A and 2B.
- the pad arrangement depicted in FIG. 6A is the same as the pad arrangement depicted in FIG. 5 A.
- Adjacent columns of SMT pads are offset from one another by a distance Oc-
- the via column pitch Pvc is the same as the SMT pad column pitch
- the via arrangement has been altered, however, such that the pitch A between adjacent signal conductor vias may be greater than the pitch A 1 , A 2 between a signal conductor via and an adjacent ground conductor via. It is expected that an arrangement such as depicted in FIGs. 6 A and 6B, will yield a higher impedance, and, consequently, a better impedance match, than an arrangement such as depicted in FIGs. 5A and 5B, even if routing density is unchanged. Also, the distance A between adjacent vias may be larger than the pad row pitch P R . Thus, routing density may be improved because one or more traces Ty may be disposed between adjacent rows as shown.
- FIGs. 7A and 7B depict a footprint wherein a via arrangement such as depicted in FIGs. 5A and 5B has been altered in accordance with an aspect of the invention.
- the pad arrangement depicted in FIG. 7A is the same as the pad arrangement depicted in FIG. 5A.
- the via column pitch Pvc is the same as the pad column pitch P c .
- the footprint has been altered, however, such that pads P disposed in different columns are coupled to vias V disposed along a single column. For example, as shown in FIG.
- a pair of signal conductor pads P 1 , P 2 in a first pad column may be connected to a first pair of signal conductor vias V 1 , V 2 in a via column ⁇ e.g., the middle via column), while a pair of signal conductor pads P 3 , P 4 in a second pad column ⁇ e.g., the lower pad column) may be connected to a second pair of signal conductor vias V 3 , V 4 in the same via column.
- FIGs. 8 A and 8B depict an example connector footprint.
- FIG. 8 A depicts two columns of vias V and pads P in a dog-bone configuration.
- FIG. 8B depicts the arrangement of vias V on an inner layer, including an example arrangement of via anti-pads AP.
- the row pitch P VR of the via arrangement is the same as the row pitch PR of the SMT pad arrangement.
- the column pitch Pvc of the via arrangement is the same as the column pitch Pc of the SMT pad arrangement.
- the stagger Ovc between adjacent columns of vias is the same as the offset Oc between adjacent columns of SMT pads.
- the via arrangement is the same as the
- the column pitch Pc might be about 3 mm in such a footprint.
- FIGs. 9A and 9B depict a footprint wherein a via arrangement such as depicted in FIGs. 8A and 8B has been altered within a column in a manner such as described above in connection with FIGs. 2A and 2B.
- the pitch A between adjacent signal conductor vias within a column may be greater than the pitch A 1 , A 2 between a signal conductor via and an adjacent ground conductor via.
- the anti-pads depicted in FIGs. 8B, 9B, 1OB, and HB may be smaller than the anti-pads depicted in FIGs. 5B, 6B, and 7B. It is expected that, consequently, signal integrity will not be as good using a footprint as depicted in FIGs. 9A and
- FIGs. 9A and 9B as it would be using a footprint as depicted in FIGs. 6 A and 6B.
- a pair of traces Tv maybe routed along each such routing channel as shown.
- increasing routing density can tend to increase impedance by reducing the number of board layers.
- the footprint depicted in FIGs. 9A and 9B provides for a trade-off between signal integrity and impedance matching.
- FIGs. 1OA and 1OB depict a footprint wherein a via arrangement such as depicted in FIGs. 9A and 9B has been further altered to halve the via column pitch. That is, the via column pitch Pvc depicted in FIGs. 1OA and 1OB is about half of the via column pitch Pvc depicted in FIGs. 9A and 9B (and, therefore, about half the SMT pad column pitch P c ). Consequently, the width of the routing channels between adjacent via columns is also halved. Because there are twice as many columns, however, and, consequently, twice as many routing channels, there is no decrease in routing density. By arranging the vias into four columns instead of two, however, the signal vias may be farther apart from one another, which tends to improve signal integrity.
- FIGs. HA and HB depict a footprint wherein a via arrangement such as depicted in FIGs. 8A and 8B has been altered in a manner such as described above in connection with FIGs. 2A and 2B and such that pads disposed in different columns are coupled to vias disposed along a single via column.
- the pad arrangement depicted in FIGs. 1 IA and 1 IB is the same as the pad arrangement depicted in FIGs. 8A and 8B.
- the via column pitch Pvc depicted in FIGs. 1 IA and 1 IB is the same as the via column pitch P V c depicted in FIGs. 8A and 8B.
- the pitch A between adjacent signal conductor vias within a column may be greater than the pitch A 1 , A 2 between a signal conductor via and an adjacent ground conductor via.
- a pair of signal conductor SMT pads P in a first pad column e.g., the upper pad column shown in FIG. HA
- a first pad column e.g., the upper pad column shown in FIG. HA
- a second pad column e.g., the lower pad column
- FIGs. 7A and 7B it is expected that an arrangement such as depicted in FIGs. 1 IA and 1 IB will yield a lower cross-talk than an arrangement such as depicted in FIGs. 8A and 8B, even if routing density is unchanged.
- the routing channels between rows provide for relatively straight traces Ty, rather than serpentine traces as depicted in FIGs. 9A and 9B.
- FIGs. 12A and 12B depict a footprint wherein a via arrangement such as depicted in FIGs. 8A and 8B has been altered to provide for double-density routing between adjacent rows while maintaining double-density routing between adjacent columns (e.g., four pairs rather than two).
- signal pairs may be split.
- signal conductors 1 and 3 may form a first pair
- signal conductors 2 and 4 form a second pair
- the vias may be arranged such that adjacent signal conductor vias are associated with different differential signal pairs.
- the vias may be arranged as shown such that via 2 is located between vias 1 and 3.
- the differential signal pair formed by signal conductor vias 1 and 3 may be "split.” It should be understood that increasing the distance between the conductors that form a pair increases impedance.
- adjacent vias may be separated from one another by a distance that allows for routing of traces between the vias that form the pairs. As shown, two pairs of traces may be routed between the vias that form the pairs.
- the arrangement also permits two ground pads, e.g., AP 1 and AP 2 , to be coupled to the same ground via G. Thus, a number of ground vias may be eliminated.
- the via arrangement may be altered to achieve an acceptable level of differential cross-talk.
- differential cross-talk within a column is a function of the sum of individual cross-talks.
- differential cross-talk may be computed by summing the individual cross-talks between signal conductors 1 and 2, 2 and 3, 3 and 4, and 1 and 4.
- the via arrangement may be altered, e.g., the vias may be moved around relative to one another, until the sum of all the individual cross-talks is near-zero (or at least below an acceptable level).
- FIGs. 13A and 13B depict another footprint that provides for double-density routing without split signal pairs.
- the pad arrangement depicted in FIG. 13A is the same as the pad arrangement depicted in FIG. 12 A.
- FIGs. 13 A and 13B illustrate that the principle applied within a column as described in connection with the arrangement depicted in FIGs. 12A and 12B, can be applied between columns. That is, the vias may be moved around relative to one another until the differential cross-talk is below an acceptable level.
- neighboring signal pairs 3,4 and 5,6 are separated from one another, but the signal pairs are not split (that is, each signal conductor is adjacent to the other signal conductor with which it forms a pair).
- adjacent via pairs may be separated from one another by a distance that allows for routing between them.
- four pairs of traces may be routed between via pairs 3,4 and 5,6.
- Differential cross-talk between pairs may be computed by summing the individual cross-talks between the signal conductors.
- differential cross-talk between pairs 1,2 and 3,4 may be computed by summing the individual cross-talks between signal conductors 1 and 3, 2 and 3, 2 and 4, and 1 and 4.
- the vias may be moved around until the differential cross-talk is below an acceptable level.
- FIGs. 14A and 14B depict a footprint wherein two columns of pads are coupled to one column of vias.
- the via column pitch Pvc may be twice the pad column pitch Pc-
- the routing channel between adjacent via columns may be twice as wide, though there may be only half as many such routing channels.
- four pairs may be routed in one channel, rather than two pairs in each of two channels.
- the via row pitch P VR may be half the pad row pitch P R .
- Signal pairs may be split, however, to improve signal integrity. That is, adjacent signal conductor vias in a via column may belong to different signal pairs.
- signal conductor visas 1 and 3 may form a first pair
- signal conductor vias 2 and 4 may form a second pair.
- two signal pairs may be disposed adjacent to one another without an intervening ground.
- a number of ground vias may be eliminated, as two grounds pads may be coupled to a single ground via.
- FIGs. 15A and 15B depict a footprint wherein two columns of pads are coupled to one column of vias, without split signal pairs.
- the via column pitch Pvc may be twice the pad column pitch Pc.
- the routing channel between adjacent via columns may be twice as wide, though there may be only half as many such routing channels.
- four pairs may be routed in one channel, rather than two pairs in each of two channels.
- FIGs. 16A and 16B depict a footprint that provides for two-and-a-half times routing density. Though the footprint depicted in FIGs.
- FIG. 16A and 16B is depicted without split signal pairs, it should be understood that the signal pairs could be split.
- the routing channels depicted in FIG. 16B are the same as the routing channels depicted in FIG. 15B.
- the footprint depicted in FIG. 16B differs from the footprint depicted in FIG. 15B, however, in that the traces depicted in FIG. 16B may be narrower than the traces depicted in FIG. 15B.
- Traces may have widths in the range of about 100-300 ⁇ m, preferably in the range of about 100-200 ⁇ m.
- 14B, 15B, and 16B may be modified in accordance with the embodiments depicted in FIGs. 17- 21 to improve routing density and electrical performance of the connector/substrate system.
- FIG. 17 depicts a partial view of a connector footprint that includes a first pair of signal conductor vias S 1 and S 2 and a second pair of signal conductor vias S 3 and S 4 .
- Vias S 1 and S 2 may form a first differential signal pair and signal conductor vias S 3 and S 4 may form a second differential signal pair. As shown, the vias may be disposed in a linear arrangement.
- the pitch E 1 between the signal conductor vias S 1 and S 2 , and the pitch E 3 between the signal conductor vias S 3 and S 4 each may be less than the pitch E 2 between the signal conductor vias S 2 and S 3 .
- the pitch E between the signal conductor via S 1 and the ground conductor via G 1 , and the pitch E 4 between the signal conductor via S 4 and the ground conductor G 2 may be less than the pitch E 2 .
- the pitches E, E 1 , E 3 , and E 4 may, in general, be the same as, or different from, one another.
- FIG. 18 depicts a partial view of an alternative embodiment of a connector footprint that includes two ground conductor vias G 1 and G 2 , and four signal conductor vias S 1 , S 2 , S 3 , and S 4 .
- the signal conductor vias S 1 , S 2 , S 3 , and S 4 may be staggered relative to one another along the centerline C along which the vias are disposed.
- the signal conductor vias S 1 and S 3 may be offset by a distance B 1 from the centerline C in a first direction
- the signal conductor vias S 2 and S 4 may be offset by a distance B 2 from the centerline C in a direction that is opposite to the first direction.
- the offset B 1 may be the same as, or different from, the offset B 2 .
- the ground conductor vias G 1 and G 2 may be located on the centerline C, as shown.
- the signal conductor vias S 1 , S 2 , S3, and S 4 may be staggered with respect to each other in such a way as to be symmetrical with respect to the ground conductor vias G 1 and G 2 adjacent, respectively, to the signal conductor vias S 1 and S 4 .
- the actual distances B 1 and B 2 may be chosen to achieve a desired routing density, while optimizing signal transmission performance through better impedance-matching and cross-talk reduction.
- the pitches F, F 1 , F 2 , F 3 , and F 4 may, in general, be the same as, or different from, one another.
- the actual distances F, F 1 , F 2 , F 3 , and F 4 may be chosen to achieve a desired routing density, while optimizing signal transmission performance through better impedance- matching and cross-talk reduction. It is also expected that the sum of the distances F, F 1 , F 2 , F 3 , and F 4 may be less than the sum of the distances E, E 1 , E 2 , E 3 , and E 4 depicted in FIG. 17 to achieve the same electrical performance for the same connector lead arrangement.
- FIG. 19 depicts a partial view of an example embodiment of a connector footprint that includes two ground conductor vias G 1 and G 2 , and four signal conductor vias S 1 , S 2 , S 3 , and S 4 .
- the signal conductor vias S 1 , S 2 , S 3 , and S 4 may be staggered relative to one another along the centerline C along which the vias are disposed. That is, the signal conductor vias S 1 and S 3 , for example, may be offset by a distance B 1 from the centerline C in a first direction, and the signal conductor vias S 2 and S 4 may be offset by a distance B 2 from the centerline C in a direction that is opposite to the first direction.
- the offset B 1 may be the same as, or different from, the offset B 2 .
- the ground conductor vias G 1 and G 2 may also be offset relative to the centerline C.
- the ground conductor G 1 may be offset a distance B 3 from the centerline C, and may be offset in the same direction as the signal conductor vias S 2 and S 4 .
- the ground conductor G 2 may be offset a distance B 4 from the centerline C, and may be offset in the same direction as the signal conductor vias S 1 and S 3 .
- the offsets B 1 , B 2 , B 3 , and B 4 may be the same as, or different from, one another.
- the vias may be staggered with respect to each other in such a way as to be symmetrical with respect to the centerline C.
- the actual distances B 1 , B 2 , B 3 , and B 4 may be chosen to achieve a desired routing density, while optimizing signal transmission performance through better impedance-matching and cross-talk reduction.
- the pitches H, H 1 , H 2 , H 3 , and H 4 may, in general, be the same as, or different from, one another.
- the actual distances H, H 1 , H 2 , H 3 , and H 4 may be chosen to achieve a desired routing density, while optimizing signal transmission performance through better impedance-matching and cross-talk reduction. It is also expected that the sum of the distances H, H 1 , H 2 , H 3 , and H 4 may be less than the sum of the distances F, F 1 , F 2 , F 3 , and F 4 depicted in FIG. 19 to achieve the same electrical performance for the same connector lead arrangement.
- FIG. 20 depicts a partial view of a connector footprint including a plurality of pads P arranged to correspond with the arrangement of the terminal portions of the leads of an electrical connector (not shown) that is to be received by the substrate.
- the substrate may also include pluralities of vias V arranged into two-pair column cells. As shown, each column cell may include two pairs of signal conductor vias S 5 and two ground conductor vias G. Each via V is electrically connected to a respective pad P.
- the vias V may be offset relative to the via column centerline C, such as described in connection with FIG. 19.
- the spacing between adjacent column cells may be large compared to the spacing between adjacent vias or pairs within the column. Accordingly, the connector footprint depicted in FIG. 20 may improve routing density as it allows for additional traces Ty to be disposed between adjacent column cells.
- FIG. 21 depicts a partial view of an example embodiment of a connector footprint that includes two ground conductor vias G 1 and G 2 , and four signal conductor vias S 1 , S 2 , S 3 , and S 4 .
- the signal conductor vias S 1 , S 2 , S 3 , and S 4 may be staggered relative to the centerline C along which the vias are disposed. That is, the signal conductor vias S 1 and S 2 , for example, may be offset by a distance B 1 from the centerline C in a first direction, and the signal conductor vias S 3 and S 4 may be offset by a distance B 2 from the centerline C in a direction that is opposite to the first direction.
- the offset B 1 may be the same as, or different from, the offset B 2 .
- the ground conductor vias G 1 , G 2 may be located on the centerline C, as shown.
- the signal conductor vias S 1 , S 2 , S 3 , and S 4 may be offset with respect to each other in such a way as to be symmetrical with respect to the ground conductor vias.
- the pitches I, I 1 , 1 3 , and I 4 may, in general, be the same as, or different from, one another.
- the pitch I 4 between the signal conductor S 4 and the ground conductor G 2 may be larger than any of the pitches I, I 1 , I 2 , and I 3 .
- FIGs. 22A and 22B depicts a typical prior art footprint wherein the via arrangement is the same as the pad arrangement. That is, the vias V may be arranged into rows and columns, for example, just as the SMT pads P are arranged into rows and columns. Further, the row pitch P VR and column pitch Pvc of the via arrangement may be the same as the row pitch P R and column pitch P c of the pad arrangement. As shown, adjacent via columns are not staggered relative to one another.
- FIGs. 23A and 23B depict a footprint as depicted in FIGs. 22A and 22B, modified by redirecting certain signal pairs to different vias.
- the routing may be the same as that depicted in FIG. 22B, but the traces may route different signals.
- traces may be made narrow enough such that two pairs of traces may be routed in the routing channel between adjacent columns, rather than only one pair as depicted in FIGs. 22B and 23B.
- FIGs. 24A and 24B depict a footprint that provides for double-density routing, wherein adjacent signal pairs have been separated into different via columns. As shown, there may be twice as many via columns as pad columns.
- the via row pitch P VR may be the same as the pad row pitch P R
- the via column pitch Pyc may be half the pad column pitch Pc. Consequently, though the routing channel between adjacent via columns may be only half as wide, there may be twice as many such routing channels. Accordingly, one pair of traces T may be routed in each channel, rather than two pairs in each of half-as-many channels. Consequently, the routing density may be unchanged. However, moving the pairs farther apart tends to improve signal integrity.
- FIG. 25 A and 25B depict a footprint that provides for one-and-a-half times routing density.
- a first via column e.g, the upper via column depicted in FIG. 25B
- a second via column e.g., the second via column from the top
- the second via column may be offset from the first via column by a distance Oy along the direction along which the column extends.
- the second via column may be separated from the a third via column (e.g., the third via column from the top) by a second via column pitch Py 2 that is larger than the first via column pitch Py 1 .
- a first, relatively narrow routing channel (having column pitch Py 1 ) may be formed between the first via column and the second via column
- a second, relatively wide routing channel (having column pitch Py 2 ) may be formed between the second via column and the third via column.
- One pair of traces T may be routed along the first routing channel.
- Two pairs of traces T may be routed along the second routing channel.
- the arrangement provides two adjacent routing channels that, combined, provide routing space for three pairs of traces. [0103] FIGs.
- 26 A and 26B depict a footprint that provides for one-and-a-half times routing density.
- a first via column e.g, the upper via column depicted in FIG. 26B
- the second via column may be separated from a second via column (e.g., the second via column from the top) by a first via column pitch Py 1 .
- the second via column may be offset from the first via column by an offset Oy.
- the second via column may be separated from the a third via column (e.g., the third via column from the top) by a second via column pitch Py 2 that is larger than the first via column pitch Py 1 .
- a routing channel may be formed between the second and third via columns, as depicted in FIG. 26B, that is wide enough to route three pairs of traces. Accordingly, instead of two routing channels, each of which is capable of routing one pair of traces, the arrangement provides a single routing channel capable of routing three pairs of traces.
- FIGs. 27 A and 27B depict a footprint that provides for serpentine routing.
- a first via column e.g, the upper via column depicted in FIG. 27B
- a second via column e.g., the second via column from the top
- a first via column pitch Pv 1 e.g., the first via column pitch
- a first via row e.g, the leftmost via row depicted in FIG. 27B
- a distance which may be, as shown, the same as a via column pitch Py 1 .
- the second via column may be separated from the a third via column (e.g., the third via column from the top) by a second via column pitch Py 2 that is larger than the first via column pitch Py 1 .
- Adjacent rows may be staggered. That is, a first row maybe offset by a distance O from an adjacent row. As shown, every third row may be offset.
- a serpentine routing channel may be formed between the second and third via columns.
- One or more serpentine traces T may be disposed along the serpentine routing channel.
- FIGs. 28A and 28B depict a footprint that provides for double-density routing.
- the vias V associated with the SMT pads P that form a first pad column e.g, the upper pad column depicted in FIG. 28A
- the vias V associated with the pads P that form a second pad column e.g., the second via column from the top
- the vias V associated with the pads P that form a second pad column may be arranged in a single via column, which may be disposed between the first and second pad columns. Consequently, no vias need be disposed between the second pad column and a third pad column that is adjacent to the second pad column.
- pad columns may be separated by a distance Pc- Pad rows may be separated by a distance P R .
- Via columns maybe separated by a distance P vc , which may be approximately twice the pad column pitch Pc- Via rows may be separated by a distance PyR, which may be approximately half the pad row pitch P R .
- a routing channel may be formed between the second and third via columns, as depicted in FIG. 28B, that is wide enough to route four pairs of traces. Accordingly, instead of two routing channels, each of which is capable of routing one pair of traces, a single routing channel capable of routing four pairs of traces may be provided. [0107] Note that, as shown in FIG. 28B, one ground via may be eliminated for every two pairs of signal conductor vias.
- the arrangement provides for routing channels between adjacent via cells (where each via cell includes a ground conductor via and two adjacent pairs of signal conductor vias).
- adjacent via cells may be separated by a distance P VR2 , which may be approximately twice the via row pitch PV R .
- the traces T may be made narrow enough such that five pairs of traces T may be routed in the routing channel between the adjacent via columns, rather than only four pairs as depicted in FIG. 28B. Thus, two-and-a-half times routing density may be achieved.
- FIGs. 29A and 29B depict example connector footprints wherein pads P s , P G are arranged in rows and vias Vs, VQ are coupled with the pads Ps, P G and are arranged in columns. Two rows of pads Ps, P G are shown, each row in a signal-signal-ground configuration.
- the hatched circles denote ground pads PQ and the open circles denote signal pads Ps-
- the signal pads Ps of one row may be aligned with (i.e., in the same column as) signal pads Ps of the adjacent row but may also be offset by, for example, a one position shift.
- the ground pads PQ of one row may be aligned with the ground pads P G of the other row.
- the signal and ground pads Ps, P G of one row may be vertically aligned with, respectively, the signal and ground pads Ps, P G of another row.
- Each of the pads Ps, P G may be coupled to a respective via Vs, VQ by traces T.
- the vias Vs, VQ may be arranged vertically, that is, in columns.
- the vias Vs, V G may be located in an inside area IA located between the two rows of pads Ps, P G and/or may be located in outside areas OA, the outside areas OA being areas adjacent to a row on a side opposite the inside area IA.
- the columns of vias may extend across both rows of pads and contain vias associated with pads in both rows.
- the vias associated with the pads are preferably arranged in a plurality of side by side, generally parallel columns.
- the vias Vs, V G of each column may be in signal-signal-ground configuration.
- the shaded vias denote ground vias V G and the unshaded vias denote signal vias V s .
- Adjacent columns of vias V s , V G may be staggered such that each ground via V G in a column is adjacent to a signal via Vs in an adjacent column.
- each column of vias Vs, VQ may be in a signal-signal-ground configuration, but the ground vias VQ may be staggered with respect to ground vias VQ in adjacent columns.
- the traces T may thus be routed in a manner to couple the staggered ground vias VQ in the columns with the unstaggered ground pads PQ in the rows.
- V 29 may create four columns of staggered vias Vs, V G from two rows of unstaggered pads Ps, P G - This results in increased routing space between the vertical columns of vias. It will be understood that embodiments of the invention are envisioned for single-ended signaling as well and that the pad and via arrangement may be adjusted accordingly.
- the via configuration of FIG. 29 shows an arrangement of ground vias VQ in a linear arrangement on a diagonal across the four columns of staggered vias Vs, VQ.
- This diagonal arrangement is denote by a dotted line g. hi between each diagonal linear arrangement of ground vias V G may be diagonal rows of signal vias Vs-
- the diagonal arrangement of signal vias Vs is denoted by dotted lines si and s2. It will be understood, however, that alternative arrangements are envisioned to provide the staggering of the ground vias V G relative to adjacent via columns.
- the vias Vs and V G are shown in FIG.
- the spacing and relative positions of the vias may be arranged in accordance with embodiments previously described.
- the relative spacing between vias may be as shown in FIG. 2B, with the distance between the signal vias being less than the distance between the ground via and the next adjacent signal via.
- the vias can be arranged as shown in FIGs. 3B or 4B, with the signal vias being laterally offset from the column centerline.
- the pads P s , P G may be coupled with columns of plated through-holes, where the plated through-holes are in a staggered configuration similar to the configuration of the vias Vs, VQ.
- the signal pads Ps may be coupled to signal vias Vs and the ground pads PQ may be coupled to ground plated through-holes, and vice versa.
- FIG. 29B depicts such a pad arrangement that may be suitable for SMT edge card applications, for example.
- the arrangement of pads is ideally suited for a differential pair edge card connector.
- the two connector terminals carrying the differential signals may be terminated to adjacent pads P s and these pairs of pads are separated from adjacent pairs of pads by ground pads PQ.
- FIGs. 3OA depicts two pairs of signal-conducting vias S, with a ground via Gs disposed between the pairs.
- the pairs may be differential signal pairs.
- the vias are arranged in a linear array disposed along a centerline C. Each via hole may be approximately the same size.
- FIG. 3 IB depicts the two pairs of signal-conducting vias S, with a relatively large ground via G L disposed between the pairs. As shown in FIG. 3OB, the ground via hole may be larger than any of the signal via holes.
- FIGs. 31A depicts two pairs of signal-conducting vias S, with a ground via G s disposed between the pairs.
- the pairs may be differential signal pairs.
- the vias are arranged into two adjacent columns, separated by a distance P V o The columns are offset from one another by a distance Oy- As shown in FIG. 3 IA, each via hole may be approximately the same size.
- FIGs. 3 IB depicts the two pairs of signal-conducting vias S, with a relatively large ground via G L disposed between the pairs. As shown in FIG. 3 IB, the ground via hole may be larger than any of the signal via holes.
- FIGs. 32A and 32B provide example plots of differential impedance and cross ⁇ talk, respectively, for various ground via hole sizes. The data was gathered for footprints having signal via holes with diameters of about 0.5 mm, and ground via holes of about 0.5, 0.9, and 1.3 mm in diameter. It can be seen from FIG. 32 A that differential impedance ⁇ i.e., impedance between the signal vias that form a differential signal pair) is relatively unaffected by the change in ground via hole size. It can be seen from FIG. 32B that cross-talk performance improves significantly as the ground via hole diameter increases.
Abstract
Description
Claims
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EP05823915A EP1839466A2 (en) | 2004-11-29 | 2005-11-28 | Improved matched-impedance surface-mount technology footprints |
CN2005800473019A CN101112135B (en) | 2004-11-29 | 2005-11-28 | Improved matched-impedance surface-mount technology footprints |
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CN117440595A (en) * | 2022-09-27 | 2024-01-23 | 中兴智能科技南京有限公司 | Differential arrangement structure and printed circuit board |
CN115696737A (en) * | 2022-11-01 | 2023-02-03 | 超聚变数字技术有限公司 | Circuit board and computing device |
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- 2005-11-28 CN CN2009102040695A patent/CN101673885B/en not_active Expired - Fee Related
- 2005-11-28 EP EP05823915A patent/EP1839466A2/en not_active Withdrawn
- 2005-11-28 CN CN2009102040727A patent/CN101674707B/en not_active Expired - Fee Related
- 2005-11-28 CN CN2005800473019A patent/CN101112135B/en not_active Expired - Fee Related
- 2005-11-28 CN CN2009102040712A patent/CN101673887B/en not_active Expired - Fee Related
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EP3123619A4 (en) * | 2014-03-24 | 2018-03-14 | Sentinel Connector Systems Inc. | Testing apparatus for a high speed cross over communications jack and methods of operating the same |
Also Published As
Publication number | Publication date |
---|---|
CN101673887A (en) | 2010-03-17 |
CN101112135B (en) | 2010-12-29 |
CN101673885A (en) | 2010-03-17 |
EP1839466A2 (en) | 2007-10-03 |
CN101674707A (en) | 2010-03-17 |
CN101673885B (en) | 2012-07-18 |
CN101673886A (en) | 2010-03-17 |
CN101673886B (en) | 2012-07-25 |
CN101674707B (en) | 2012-02-22 |
CN101112135A (en) | 2008-01-23 |
CN101673887B (en) | 2013-04-10 |
WO2006056473A3 (en) | 2006-09-08 |
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