WO2006055890A2 - Surface pairs - Google Patents

Surface pairs Download PDF

Info

Publication number
WO2006055890A2
WO2006055890A2 PCT/US2005/042093 US2005042093W WO2006055890A2 WO 2006055890 A2 WO2006055890 A2 WO 2006055890A2 US 2005042093 W US2005042093 W US 2005042093W WO 2006055890 A2 WO2006055890 A2 WO 2006055890A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
precursor
electrode
electrode pair
indents
Prior art date
Application number
PCT/US2005/042093
Other languages
French (fr)
Other versions
WO2006055890A3 (en
Inventor
Avto Tavkhelidze
Misha Vepkhvadze
Original Assignee
Borealis Technical Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Borealis Technical Limited filed Critical Borealis Technical Limited
Priority to GB0711420A priority Critical patent/GB2436246B/en
Priority to US11/667,882 priority patent/US8574663B2/en
Publication of WO2006055890A2 publication Critical patent/WO2006055890A2/en
Publication of WO2006055890A3 publication Critical patent/WO2006055890A3/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02Main electrodes
    • H01J1/30Cold cathodes, e.g. field-emissive cathode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02Manufacture of electrodes or electrode systems
    • H01J9/022Manufacture of electrodes or electrode systems of cold cathodes

Definitions

  • the present invention relates to methods for making electrode pairs in which the distribution of energy states within them is altered and for promoting the transfer of elementary particles across a potential energy barrier.
  • US6281514, US6117344, US6531703 and US6495843 disclose a method for promoting the passage of elementary particles at or through a potential barrier comprising providing a potential barrier having a geometrical shape for causing de Broglie interference between said elementary particles is disclosed. Also disclosed is an elementary particle-emitting surface having a series of indents. The depth of the indents is chosen so that the probability wave of the elementary particle reflected from the bottom of the indent interferes destructively with the probability wave of the elementary particle reflected from the surface. This results in the increase of tunnelling through the potential barrier. When the elementary particle is an electron, and potential barrier is surface of the substance electrons tunnel through the potential barrier, thereby leading to a reduction in the effective work function of the surface.
  • WO03083177 discloses modification of a metal surface with patterned indents that increases the Fermi energy level inside the metal, leading to a decrease in electron work function. Also disclosed is a method for making nanostructured surfaces having perpendicular features with sharp edges.
  • the present invention is a method for fabricating an electrode pair precursor which comprises the steps of creating on one surface of a substrate one or more indents of a depth less than 10 nm and a width less than 1 ⁇ m; depositing a layer of material on the top of this structured substrate to forming a first electrode precursor; depositing another layer the first electrode precursor to form a second electrode precursor; and finally forming a third layer on top of the second electrode precursor.
  • the method additionally comprises creating on the surface of the second electrode precursor one or more indents of a depth less than 10 nm and a width less than 1 ⁇ m. In a further embodiment the method additionally comprises the deposition of a another layer between said first and second electrode precursor layers.
  • the present invention is also directed towards an electrode pair precursor comprising a substrate having on one surface one or more indents of a depth less than 10 nm and a width less than 1 ⁇ m; having a layer of material formed on the top of this structured substrate to form a first electrode precursor; having another layer formed on the first electrode precursor to form a second electrode precursor; and finally having a third layer formed on top of the second electrode precursor.
  • the electrode pair precursor has on the surface of the second electrode precursor one or more indents of a depth less than 10 nm and a width less than 1 ⁇ m.
  • the electrode pair precursor additionally comprises another layer between said first and second electrode precursor layers.
  • Figure 1 shows the shape and dimensions of a surface structure utilised in the present invention
  • Figure 2 and 3 show in a diagrammatic form processes for making the electrode pair precursors of the present invention
  • Figures 4a and 4b show how the electrode pair precursors may be split to create electrode pairs;
  • Figures 4c and 4d show electrode pair precursors in which only one of the electrode precursors has a structured undersurface.
  • FIG. 1 shows a substrate 104.
  • the substrate has an indent 106 on one surface. Whilst the structure shown in
  • Figure 1 is a single indented region, this should not be considered to limit the scope of the invention, and dotted lines have been drawn to indicate that in further embodiments the structure shown may be extended in one or both directions (i.e. to the left and/or to the right) to form features on the surface of the substrate that have a repeating, or periodic, nature.
  • the configuration of the surface may resemble a corrugated pattern of sguared-off, "u"-shaped ridges and/or valleys.
  • the pattern may be a regular pattern of rectangular “plateaus” or "holes,” where the pattern resembles a checkerboard.
  • the walls of said indents should be substantially perpendicular to one another, and the edges of the indents should be substantially sharp.
  • the surface configuration may be achieved using conventional approaches known in the art, including without limitation lithography and e-beam milling.
  • Indent 106 has a width 108 and a depth 112 and the separation between the indents is 110.
  • distances 108 and 110 are substantially equal.
  • distance 108 is of the order of 1 ⁇ m or less. Utilization of e- beam lithography to create structures of the kind shown in Figure 1 may allow indents to be formed in which distance 108 is 100 nm or less.
  • Distance 112 is of the order of 10 nm or less, and is preferably of the order of 5 rnn.
  • a surface of substrate 202 is modified to form a series of indents or channels 224 across the substrate.
  • Substrate 202 may be for example and without limitation any substrate conventionally used in microelectronic or thermionic applications.
  • Substrate 202 is preferably silica or silicon, which may optionally be doped to increase thermal or electrical conductivity.
  • the indents or channels are formed for example and without limitation by any approach conventionally used in microelectronic applications, including stamping, milling, photolithography, e-beam lithography and ion-beam lithography. The dimensions of the indents are chosen to cause wave interference in a material, as disclosed above.
  • a layer of first material 232 is formed on the substrate in such a way that the indented regions are filled and so that the surface of the layer of a first material opposing said indented region 234 is substantially flat.
  • Material 232 may be any material in which the Fermi level can be shifted using wave properties of electrons in material having a periodic structured surface.
  • the material is one that, under stable conditions, will not form an oxide layer, or will form an oxide layer of a known and reliable thickness.
  • Preferred materials include, but are not restricted to, metals such as gold and chrome, and materials that under stable conditions form an oxide layer preferably of less than about ten nanometers, and more preferably of less than about five nanometers. We suggest that using gold as the material, may allow the apparent work function to be reduced to as little as 1 eV, and using calcium may allow an apparent work function as little as 0.2 eV.
  • a layer of second material 242 is formed on the substantially flat surface 234 of layer 232.
  • material 242 is silver, but may be any material whose adhesion to material 232 may be carefully controlled.
  • Layer 242 is sufficiently thin that the structure of layer 232 is maintained on its surface.
  • Step 240 is optional, and may be omitted, as is shown In Figure 3.
  • a layer of third material 252 is formed on layer 242.
  • Material 232 may be any material in which the Fermi level can be shifted by altering the wave behavior of electrons in a material having a periodic structured surface.
  • the material is one that, under stable conditions, will not form an oxide layer, or will form an oxide layer of a known and reliable thickness.
  • Preferred materials include, but are not restricted to, metals such as gold and chrome, and materials that under stable conditions form an oxide layer preferably of less than about ten nanometers, and more preferably of less than about five nanometers. We suggest that using gold as the material, may allow the apparent work function to be reduced to as little as 1 eV, and using calcium may allow an apparent work function as little as 0.2 eV. If step 240 has been omitted, as shown in Figure 3, then conditions used for step 250 are controlled so that adhesion to material 232 may be carefully controlled
  • a surface of said third material is modified to form a series of indents or channels 254 across said surface.
  • the indents or channels are formed for example and without limitation by any approach conventionally used in microelectronic applications, including stamping, milling, photolithography, e-beam lithography and ion-beam lithography.
  • the dimensions of the indents are chosen to cause wave interference in a material, as disclosed above.
  • fourth material 272 is formed on the third material in such a way that the indented regions are filled and so that the surface of the layer of a fourth material opposing said indented region 274 is substantially flat.
  • material 272 is copper, and is formed by an electrochemical process.
  • conditions for forming layers 232, 242 and 252 are carefully chosen so that the adhesion between the layers may be controlled.
  • step 240 is omitted, as in Figure 3, then conditions for forming layers 232 and 252 are carefully chosen so that the adhesion between the layers may be controlled.
  • the composite formed from the steps above may be mounted in a suitable housing that permits the composite to be opened in a controlled environment.
  • a suitable housing is disclosed in WO03/090245, which is incorporated herein by reference in its entirety.
  • the housing may include a getter, either for oxygen or water vapour.
  • the housing may also include positioning means to control the separation of the two parts of the split composite.
  • the electrodes will be positioned approximately 0.5 ⁇ m apart to overcome space charge effects.
  • the housing may also include thermal pathway elements that allow a heat source to be contacted to one half of the composite, and a heat sink to be contacted to the other.
  • the housing may also include electrical connections to allow a voltage to be applied across the pair of electrodes, or to allow a current flowing between the electrodes to be applied to an external load.
  • FIG 4a the composite formed as a result of the process disclosed above and shown in Figure 2, is separated and layer 242 is removed to yield a pair of electrodes as shown.
  • Figure 4b illustrates this separation step for a composite formed as a result of the process disclosed above and shown in Figure 3.
  • the separation may be achieved using any of the methods disclosed in WO03/021663 which is incorporated herein by reference in its entirety, and is preferably a thermal treatment step, which introduces tension sufficiently strong to overcome adhesion between the layers.
  • any minor imperfections on the surface of electrode 402 are matched on electrode 404.
  • step 260 is omitted, which leads to a composite having only one modified layer, as shown in Figures 4c and 4d.
  • one electrode has a surface having an indented under surface, whilst the other electrode is of more conventional construction.

Abstract

The present invention is a method for fabricating an electrode pair precursor which comprises the steps of creating on one surface of a substrate one or more indents of a depth less than approximately 100 nm and a width less than approximately 1 µm; depositing a layer of material on the top of this structured substrate to forming a first electrode precursor; depositing another layer the first electrode precursor to form a second electrode precursor; and finally forming a third layer on top of the second electrode precursor.

Description

Surface Pairs
Field of Invention
The present invention relates to methods for making electrode pairs in which the distribution of energy states within them is altered and for promoting the transfer of elementary particles across a potential energy barrier.
Background of the Invention
US6281514, US6117344, US6531703 and US6495843 disclose a method for promoting the passage of elementary particles at or through a potential barrier comprising providing a potential barrier having a geometrical shape for causing de Broglie interference between said elementary particles is disclosed. Also disclosed is an elementary particle-emitting surface having a series of indents. The depth of the indents is chosen so that the probability wave of the elementary particle reflected from the bottom of the indent interferes destructively with the probability wave of the elementary particle reflected from the surface. This results in the increase of tunnelling through the potential barrier. When the elementary particle is an electron, and potential barrier is surface of the substance electrons tunnel through the potential barrier, thereby leading to a reduction in the effective work function of the surface. WO03083177 discloses modification of a metal surface with patterned indents that increases the Fermi energy level inside the metal, leading to a decrease in electron work function. Also disclosed is a method for making nanostructured surfaces having perpendicular features with sharp edges.
Disclosure of Invention The present invention is a method for fabricating an electrode pair precursor which comprises the steps of creating on one surface of a substrate one or more indents of a depth less than 10 nm and a width less than 1 μm; depositing a layer of material on the top of this structured substrate to forming a first electrode precursor; depositing another layer the first electrode precursor to form a second electrode precursor; and finally forming a third layer on top of the second electrode precursor.
In a further embodiment the method additionally comprises creating on the surface of the second electrode precursor one or more indents of a depth less than 10 nm and a width less than 1 μm. In a further embodiment the method additionally comprises the deposition of a another layer between said first and second electrode precursor layers.
The present invention is also directed towards an electrode pair precursor comprising a substrate having on one surface one or more indents of a depth less than 10 nm and a width less than 1 μm; having a layer of material formed on the top of this structured substrate to form a first electrode precursor; having another layer formed on the first electrode precursor to form a second electrode precursor; and finally having a third layer formed on top of the second electrode precursor. In a further embodiment the electrode pair precursor has on the surface of the second electrode precursor one or more indents of a depth less than 10 nm and a width less than 1 μm.
In a further embodiment the electrode pair precursor additionally comprises another layer between said first and second electrode precursor layers.
Brief Description of Drawings
For a more complete explanation of the present invention and the technical advantages thereof, reference is now made to the following description and the accompanying drawing in which:
Figure 1 shows the shape and dimensions of a surface structure utilised in the present invention;
Figure 2 and 3 show in a diagrammatic form processes for making the electrode pair precursors of the present invention;
Figures 4a and 4b show how the electrode pair precursors may be split to create electrode pairs; Figures 4c and 4d show electrode pair precursors in which only one of the electrode precursors has a structured undersurface.
Best Mode for Carrying Out the Invention
Embodiments of the present invention and their technical advantages may be better understood by referring to Figure 1 which shows a substrate 104. The substrate has an indent 106 on one surface. Whilst the structure shown in
Figure 1 is a single indented region, this should not be considered to limit the scope of the invention, and dotted lines have been drawn to indicate that in further embodiments the structure shown may be extended in one or both directions (i.e. to the left and/or to the right) to form features on the surface of the substrate that have a repeating, or periodic, nature.
The configuration of the surface may resemble a corrugated pattern of sguared-off, "u"-shaped ridges and/or valleys. Alternatively, the pattern may be a regular pattern of rectangular "plateaus" or "holes," where the pattern resembles a checkerboard. The walls of said indents should be substantially perpendicular to one another, and the edges of the indents should be substantially sharp. Further, one of ordinary skill in the art will recognize that other configurations are possible which may produce the desired interference of wave probability functions. The surface configuration may be achieved using conventional approaches known in the art, including without limitation lithography and e-beam milling.
Indent 106 has a width 108 and a depth 112 and the separation between the indents is 110. Preferably distances 108 and 110 are substantially equal. Preferably distance 108 is of the order of 1 μm or less. Utilization of e- beam lithography to create structures of the kind shown in Figure 1 may allow indents to be formed in which distance 108 is 100 nm or less. Distance 112 is of the order of 10 nm or less, and is preferably of the order of 5 rnn.
Referring now to Figure 2, which shows in a diagrammatic form a process for making a pair of electrodes for use in a thermionic device, in a step 220 a surface of substrate 202 is modified to form a series of indents or channels 224 across the substrate. Substrate 202 may be for example and without limitation any substrate conventionally used in microelectronic or thermionic applications. Substrate 202 is preferably silica or silicon, which may optionally be doped to increase thermal or electrical conductivity. The indents or channels are formed for example and without limitation by any approach conventionally used in microelectronic applications, including stamping, milling, photolithography, e-beam lithography and ion-beam lithography. The dimensions of the indents are chosen to cause wave interference in a material, as disclosed above.
In a step 230, a layer of first material 232 is formed on the substrate in such a way that the indented regions are filled and so that the surface of the layer of a first material opposing said indented region 234 is substantially flat. Material 232 may be any material in which the Fermi level can be shifted using wave properties of electrons in material having a periodic structured surface. Preferably the material is one that, under stable conditions, will not form an oxide layer, or will form an oxide layer of a known and reliable thickness. Preferred materials include, but are not restricted to, metals such as gold and chrome, and materials that under stable conditions form an oxide layer preferably of less than about ten nanometers, and more preferably of less than about five nanometers. We suggest that using gold as the material, may allow the apparent work function to be reduced to as little as 1 eV, and using calcium may allow an apparent work function as little as 0.2 eV.
In a step 240, a layer of second material 242 is formed on the substantially flat surface 234 of layer 232. Preferably material 242 is silver, but may be any material whose adhesion to material 232 may be carefully controlled. Layer 242 is sufficiently thin that the structure of layer 232 is maintained on its surface. Step 240 is optional, and may be omitted, as is shown In Figure 3.
In a step 250, a layer of third material 252 is formed on layer 242. Material 232 may be any material in which the Fermi level can be shifted by altering the wave behavior of electrons in a material having a periodic structured surface. Preferably the material is one that, under stable conditions, will not form an oxide layer, or will form an oxide layer of a known and reliable thickness. Preferred materials include, but are not restricted to, metals such as gold and chrome, and materials that under stable conditions form an oxide layer preferably of less than about ten nanometers, and more preferably of less than about five nanometers. We suggest that using gold as the material, may allow the apparent work function to be reduced to as little as 1 eV, and using calcium may allow an apparent work function as little as 0.2 eV. If step 240 has been omitted, as shown in Figure 3, then conditions used for step 250 are controlled so that adhesion to material 232 may be carefully controlled
In a step 260, a surface of said third material is modified to form a series of indents or channels 254 across said surface. The indents or channels are formed for example and without limitation by any approach conventionally used in microelectronic applications, including stamping, milling, photolithography, e-beam lithography and ion-beam lithography. The dimensions of the indents are chosen to cause wave interference in a material, as disclosed above.
In a step 270, fourth material 272 is formed on the third material in such a way that the indented regions are filled and so that the surface of the layer of a fourth material opposing said indented region 274 is substantially flat. This yields a composite. Preferably material 272 is copper, and is formed by an electrochemical process. As disclosed above, conditions for forming layers 232, 242 and 252 are carefully chosen so that the adhesion between the layers may be controlled. Where step 240 is omitted, as in Figure 3, then conditions for forming layers 232 and 252 are carefully chosen so that the adhesion between the layers may be controlled.
The composite formed from the steps above may be mounted in a suitable housing that permits the composite to be opened in a controlled environment. Such a housing is disclosed in WO03/090245, which is incorporated herein by reference in its entirety. The housing may include a getter, either for oxygen or water vapour. The housing may also include positioning means to control the separation of the two parts of the split composite. Preferably the electrodes will be positioned approximately 0.5 μm apart to overcome space charge effects.
The housing may also include thermal pathway elements that allow a heat source to be contacted to one half of the composite, and a heat sink to be contacted to the other. The housing may also include electrical connections to allow a voltage to be applied across the pair of electrodes, or to allow a current flowing between the electrodes to be applied to an external load.
Referring now to Figure 4a, the composite formed as a result of the process disclosed above and shown in Figure 2, is separated and layer 242 is removed to yield a pair of electrodes as shown. Figure 4b illustrates this separation step for a composite formed as a result of the process disclosed above and shown in Figure 3. The separation may be achieved using any of the methods disclosed in WO03/021663 which is incorporated herein by reference in its entirety, and is preferably a thermal treatment step, which introduces tension sufficiently strong to overcome adhesion between the layers. As a result of this step, any minor imperfections on the surface of electrode 402 are matched on electrode 404.
In a further embodiment, step 260 is omitted, which leads to a composite having only one modified layer, as shown in Figures 4c and 4d. When these are separated as described above, one electrode has a surface having an indented under surface, whilst the other electrode is of more conventional construction.

Claims

Claims
1. A method of fabricating an electrode pair precursor comprising the steps:
(a) providing a substrate; (b) creating on one surface of said substrate one or more indents of a depth less than approximately 100 nm and a width less than approximately 1 μm; (c) depositing a first layer forming a substantially plane slab on said substrate and forming a first electrode precursor; (d) depositing a second layer on said first layer and forming a second electrode precursor; (e) forming a third layer on said second electrode precursor.
2. The method of claim 1 additionally comprising the step of creating on one surface of said second electrode precursor one or more indents of a depth less than approximately 100 nm and a width less than approximately 1 μm.
3. The method of claims 1 or 2 additionally comprising the step of depositing a fourth layer between said first and second layer.
4. The method of claim 3 wherein said fourth layer comprises silver.
5. The method of claims 1 to 3 wherein said first layer is substantially homogenous .
6. The method of claims 1 to 3 wherein said first layer is substantially free of granular irregularities.
7. The method of claims 1 to 3 wherein said substance is a monocrystal.
8. The method of claims 1 to 3 wherein said first layer comprises an oxidation-resistant material.
9. The method of claims 1 to 3 wherein said first layer is selected from the group consisting of: lead, tin, calcium, gold, silica and silicon.
10. The method of claims 1 to 3 wherein said third layer comprises copper.
11. The method of claim 10 wherein the method for forming said third layer of copper comprises electrolytic growth of copper.
12. The method of claims 1 to 3 in which said depth is approximately 20 nm.
13. The method of claims 1 to 3 in which said width is less than approximately 100 nm.
14. The method of claims 1 to 3 in which walls of said indents are substantially perpendicular to one another.
15. The method of claims 1 to 3 in which edges of said indents are substantially sharp.
16. An electrode pair precursor, comprising:
(a) a substrate having on one surface one or more indents of a depth less than approximately 100 nm and a width less than approximately
1 μm,-
(b) a first layer formed on said surface having one or more indents, said first layer being a first electrode precursor;
(c) a second layer formed on said first layer, said second layer being a second electrode precursor;
(d) a third layer formed on said second electrode precursor
17. The electrode pair precursor of claim 16 wherein said second electrode precursor has one or more indents of a depth less than approximately 100 nm and a width less than approximately 1 μm.
18. The electrode pair precursor of claims 16 or 17 additionally comprising a fourth layer deposited between said first and second layer.
19. The electrode pair precursor of claim 18 wherein said fourth layer comprises silver.
20. The electrode pair precursor of claims 16 to 18 wherein said first layer is substantially homogenous.
21. The electrode pair precursor of claims 16 to 18 wherein said first layer is substantially free of granular irregularities.
22. The electrode pair precursor of claims 16 to 18 wherein said substance is a monocrystal.
23. The electrode pair precursor of claims 16 to 18 wherein said first layer comprises an oxidation-resistant material.
24. The electrode pair precursor of claims 16 to 18 wherein said first layer is selected from the group consisting of: lead, tin, calcium, gold, silica and silicon.
25. The electrode pair precursor of claims 16 to 18 wherein said third layer comprises copper.
26. The electrode pair precursor of claims 16 to 18 in which said depth is approximately 20 nm.
27. The electrode pair precursor of claims 16 to 18 in which said width is less than approximately 100 nm.
28. The electrode pair precursor of claims 16 to 18 in which walls of said indents are substantially perpendicular to one another.
29. The electrode pair precursor of claims 16 to 18 in which edges of said indents are substantially sharp.
PCT/US2005/042093 2002-03-22 2005-11-17 Surface pairs WO2006055890A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB0711420A GB2436246B (en) 2004-11-17 2005-11-17 An electrode pair precursor
US11/667,882 US8574663B2 (en) 2002-03-22 2005-11-17 Surface pairs

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0425260.7 2004-11-17
GB0425260A GB0425260D0 (en) 2004-11-17 2004-11-17 Electrode pairs

Publications (2)

Publication Number Publication Date
WO2006055890A2 true WO2006055890A2 (en) 2006-05-26
WO2006055890A3 WO2006055890A3 (en) 2009-04-09

Family

ID=33523815

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/042093 WO2006055890A2 (en) 2002-03-22 2005-11-17 Surface pairs

Country Status (2)

Country Link
GB (2) GB0425260D0 (en)
WO (1) WO2006055890A2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7566897B2 (en) 2006-09-18 2009-07-28 Borealis Technical Limited Quantum interference device
US8594803B2 (en) 2006-09-12 2013-11-26 Borealis Technical Limited Biothermal power generator
US8816192B1 (en) 2007-02-09 2014-08-26 Borealis Technical Limited Thin film solar cell

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091339A (en) * 1990-07-23 1992-02-25 Microelectronics And Computer Technology Corporation Trenching techniques for forming vias and channels in multilayer electrical interconnects
JP2001196703A (en) * 2000-01-14 2001-07-19 Sony Corp Printed wiring board and manufacturing method for the same
JP2001352147A (en) * 2000-06-06 2001-12-21 Mitsui Chemicals Inc Comb-shaped electrode and its manufacturing method
US20040126547A1 (en) * 2002-12-31 2004-07-01 Coomer Boyd L. Methods for performing substrate imprinting using thermoset resin varnishes and products formed therefrom
US20040135182A1 (en) * 2002-11-11 2004-07-15 Hyeong-Geun An Ferroelectric capacitors including a seed conductive film and methods for manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091339A (en) * 1990-07-23 1992-02-25 Microelectronics And Computer Technology Corporation Trenching techniques for forming vias and channels in multilayer electrical interconnects
JP2001196703A (en) * 2000-01-14 2001-07-19 Sony Corp Printed wiring board and manufacturing method for the same
JP2001352147A (en) * 2000-06-06 2001-12-21 Mitsui Chemicals Inc Comb-shaped electrode and its manufacturing method
US20040135182A1 (en) * 2002-11-11 2004-07-15 Hyeong-Geun An Ferroelectric capacitors including a seed conductive film and methods for manufacturing the same
US20040126547A1 (en) * 2002-12-31 2004-07-01 Coomer Boyd L. Methods for performing substrate imprinting using thermoset resin varnishes and products formed therefrom

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8594803B2 (en) 2006-09-12 2013-11-26 Borealis Technical Limited Biothermal power generator
US7566897B2 (en) 2006-09-18 2009-07-28 Borealis Technical Limited Quantum interference device
US8816192B1 (en) 2007-02-09 2014-08-26 Borealis Technical Limited Thin film solar cell

Also Published As

Publication number Publication date
GB2436246A (en) 2007-09-19
GB0425260D0 (en) 2004-12-15
GB2436246A8 (en) 2007-10-16
GB2436246B (en) 2011-01-05
GB0711420D0 (en) 2007-07-25
WO2006055890A3 (en) 2009-04-09

Similar Documents

Publication Publication Date Title
US7074498B2 (en) Influence of surface geometry on metal properties
US7659165B2 (en) Method of fabricating a field effect transistor
US7375368B2 (en) Superlattice for fabricating nanowires
US20110210259A1 (en) Micro-channel plate detector
US7985469B2 (en) Particle network comprising particles disposed on a substrate and method for realizing such a network
US8258672B2 (en) Composite structure gap-diode thermopower generator or heat pump
WO2014131043A1 (en) Methods for fabricating graphite-based structures and devices made therefrom
CN108217591A (en) A kind of method of heterogeneous alternative stacked step guiding growing three-dimensional slope surface nano-wire array
US20090202787A1 (en) Method for manufacturing a nanostructure in-situ, and in-situ manufactured nanostructure devices
Sökmen et al. Shallow and deep dry etching of silicon using ICP cryogenic reactive ion etching process
JP2005186270A (en) Manufacture of nano-object array
WO2003083177A2 (en) Influence of surface geometry on metal properties
WO2006055890A2 (en) Surface pairs
US8574663B2 (en) Surface pairs
KR100973522B1 (en) Manufacturing method for ruthenium nano-structures by anodic aluminum oxide and atomic layer deposition
JP3211752B2 (en) Structure of MIM or MIS electron source and method of manufacturing the same
US20110034008A1 (en) Method for forming a textured surface on a semiconductor substrate using a nanofabric layer
KR100810983B1 (en) Vertical Nanowire Growth Method at Selectve Locations, Semiconductor Nanodevice comprising Vertical Nanowire, and Fabrication Method thereof
KR20130137441A (en) Core-shell nanowire array, manufacturing method for the same, and application device using the same
US20050145836A1 (en) Influence of surface geometry
KR102423791B1 (en) Nano structure with selectively deposited nano materials and method for selective deposition of nanomaterials on nano structure
US11486056B2 (en) Low work function materials
KR100425347B1 (en) Single electron transistor utilizing nano particle
CN114613844B (en) Miniaturized array preparation method of nano air channel electronic device
KR102430078B1 (en) Nano heater based on suspended nano structure and manufacturing method thereof

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KN KP KR KZ LC LK LR LS LT LU LV LY MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

WWE Wipo information: entry into national phase

Ref document number: 11667882

Country of ref document: US

NENP Non-entry into the national phase in:

Ref country code: DE

ENP Entry into the national phase in:

Ref document number: 0711420

Country of ref document: GB

Kind code of ref document: A

Free format text: PCT FILING DATE = 20051117

WWE Wipo information: entry into national phase

Ref document number: 0711420.0

Country of ref document: GB

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 05849274

Country of ref document: EP

Kind code of ref document: A2

WWP Wipo information: published in national office

Ref document number: 11667882

Country of ref document: US

122 Ep: pct application non-entry in european phase

Ref document number: 05849274

Country of ref document: EP

Kind code of ref document: A2