WO2006047028A2 - Packaged device and method of forming same - Google Patents

Packaged device and method of forming same Download PDF

Info

Publication number
WO2006047028A2
WO2006047028A2 PCT/US2005/034261 US2005034261W WO2006047028A2 WO 2006047028 A2 WO2006047028 A2 WO 2006047028A2 US 2005034261 W US2005034261 W US 2005034261W WO 2006047028 A2 WO2006047028 A2 WO 2006047028A2
Authority
WO
WIPO (PCT)
Prior art keywords
die
balls
conductive balls
integrated circuit
packaging
Prior art date
Application number
PCT/US2005/034261
Other languages
French (fr)
Other versions
WO2006047028A3 (en
Inventor
Chee Seng Foong
Original Assignee
Freescale Semiconductor, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from MYPI20044381A external-priority patent/MY136179A/en
Application filed by Freescale Semiconductor, Inc. filed Critical Freescale Semiconductor, Inc.
Publication of WO2006047028A2 publication Critical patent/WO2006047028A2/en
Publication of WO2006047028A3 publication Critical patent/WO2006047028A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/45164—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/45169—Platinum (Pt) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Definitions

  • the present invention relates to integrated circuit packaging, and more particularly to an improved process for fabricating a Ball Grid Array (BGA) packaged device.
  • BGA Ball Grid Array
  • An integrated circuit (IC) die is a small device formed on a semiconductor wafer, such as a silicon wafer.
  • a leadframe is a metal frame that usually includes a paddle that supports the IC die that has been cut from the wafer. The leadframe also has lead fingers that provide external electrical connections. That is, the die is attached to the die paddle and then bonding pads of the die are connected to the lead fingers via wire bonding or flip chip bumping to provide the external electrical connections . Encapsulating the die and wire bonds or flip chip bumps with a protective material forms a package.
  • the external electrical connections may be used as-is, such as in a Thin Small Outline Package (TSOP) , or further processed, such as by attaching spherical solder balls for a BGA.
  • TSOP Thin Small Outline Package
  • These terminal points allow the die to be electrically connected with other circuits, such as on a printed circuit board.
  • it can be expensive and time-consuming to form a leadframe and package a device if steps like chemical etching and etch back are required.
  • FIG. 1 is an enlarged cross-sectional view of a packaged integrated circuit in accordance with a first embodiment of the present invention
  • FIG. 2 is an enlarged cross-sectional view of a packaged integrated circuit in accordance with a second embodiment of the present invention
  • FIG. 3 is an enlarged cross-sectional view of a packaged integrated circuit in accordance with a third embodiment of the present invention.
  • FIGS. 4A-4H are perspective views illustrating ⁇ the steps for fabricating packaged semiconductor devices in accordance with the present invention.
  • FIGS. 5A and 5B are cross-sectional views illustrating the formation of a plurality of packaged semiconductor devices in accordance with the present invention.
  • the present invention provides a method of packaging an integrated circuit die, including the steps of:
  • a heat sink may be located coplanar with the conductive balls and the die attached to a surface of the heat sink.
  • the present invention further provides a packaged integrated circuit die having a plurality of conductive balls having a top, flattened surface and a first mold compound that holds the plurality of conductive balls together.
  • the top, flattened surfaces of the balls are generally coplanar with a top surface of the first mold compound, and bottom, opposing surfaces of the balls are exposed.
  • An integrated circuit die having a first side is attached to a plurality of the conductive balls.
  • the die is surrounded by others of the conductive balls.
  • the die is electrically coupled to the others of the conductive balls.
  • a second mold compound encapsulates at least a second side of the die opposing the die first side, and the top surfaces of the conductive balls.
  • FIG. 1 an enlarged cross-sectional view of a packaged semiconductor device 10 formed in accordance with an embodiment of the present invention is shown.
  • the packaged device 10 includes a plurality of conductive balls 12 having a top, flattened surface 14 and bottom, opposing surface 16.
  • a first mold compound 18 holds the plurality of conductive balls 12 together.
  • the top, flattened surfaces 14 of the balls 12 are generally coplanar with a top surface of the first mold compound 18, and the bottom, opposing surfaces 16 of the balls 12 are exposed.
  • An integrated circuit die 20 has a first side thereof 22 attached to a plurality of the conductive balls 12.
  • the die 20 is surrounded by others of the conductive balls 12 and the die 20 is electrically coupled to the others of the conductive balls 12.
  • a second mold compound 24 encapsulates at least a second side 26 of the die 20 opposing the die first side 22, and the top surfaces 14 of the conductive balls 12.
  • the second mold compound 24 is of a type known to those of skill in the art that is commonly used for packaging integrated circuits.
  • the conductive balls 12 preferably are C5 (Controlled Collapse Chip Carrier Connection) solder balls.
  • the balls 12 are made with an electrically conductive material so that electrical signals can be passed therethrough.
  • the conductive material may be a metal, such as copper or gold, or an alloy thereof, or a soft solder, such as 63/37 material (63% tin, 37% lead) or 90/10 (90% lead, 10% tin) .
  • the soft balls 14 may be formed of a polymer base material with metallic surface finish. A lead free package can be achieved by using lead free metallic balls .
  • the bottom surfaces 16 of the balls 12 are exposed and allow the integrated circuit die 12 to be connected to a printed circuit board.
  • the balls 12 are used to pass data, power and ground signals to/from the die 20 and a substrate or printed, circuit board (not shown) , as is known by those of skill in the art, while others of the balls 12 to which the die 20 is attached can conduct heat from the die 20 (i.e., thermal management) and enhance board level solder joint strength. That is, the balls 12 under the die 20 provide a solderable surface that enhances board level solder strength. It is noted that balls at the corners and even along the package edges also can provide connections that enhance the mechanical strength of the package.
  • the top surfaces 16 of the balls 12 are flattened and coplanar. The top surfaces 16 may be flattened by pressing, as discussed in more detail below.
  • the balls 12 are held together with the first mold compound 18.
  • the first mold compound 18 is of a type known to those of skill in the art that is commonly used for packaging integrated circuits.
  • the integrated circuit die 20 may be any type of known- die, such as one cut from a silicon wafer, and may be any type of circuit, such as a digital signal processor, a special purpose circuit, etc. Such circuits are well known to those of skill in the art.
  • the bottom surface 22 of the die 20 is attached to the top flattened surfaces 14 of one or more of the conductive balls 12 with a die attach material (not shown) .
  • the die attach material may be an adhesive of a type well known in the semiconductor art for attaching dies to substrates, such as an epoxy.
  • the top surface 26 of the integrated circuit die 20 includes a plurality of die bonding pads 28.
  • the die bonding pads 28 are electrically connected to ones of the conductive balls 12 that surround the die 20.
  • the die bonding pads 28 are connected to the conductive balls 12 with wires 30 via wirebonding.
  • wirebonding processes such as thermosonic wire bonding may be used to connect the wires 30 to the die bonding pads 28 and the top surface 14 of the balls 12.
  • the bond wire 30 has a diameter of between about 15urn to about 55um, although other diameter bond wires may be used and the invention should not be limited to a particular bond wire diameter. For example, 63um pitch applications use 25um diameter wire, while 52um and 44um pitch applications use 20.3um diameter wire. Development is being done for a 37um pitch application using 17um diameter wire. Thus, as is known in the art, fine pitch and ultra-fine pitch wire bonding processes may be performed depending on the pad pitch. In one embodiment of the invention, insulated bond wire is used.
  • Insulated bond wire comprises a conductive core coated with an electrically insulating material and is suitable for fine pitch and ultra- fine pitch wirebonding.
  • the insulating material prevents the wire from shorting to other wires or other conductive structures.
  • gold and aluminum are the most commonly used elements to make the conductive core of the bonding wire. Both gold and aluminum are strong and ductile and have similar resistance in most environments.
  • Gold wire is sometimes doped with a dopant, such as beryllium, calcium in order to stabilize it. Small-diameter aluminum wire is often doped with silicon or sometimes magnesium to improve its breaking load and elongation parameters.
  • copper, palladium-alloy, platinum and silver bonding wire are also known.
  • insulated wires having a diameter of less than about 25 um are used.
  • the insulative coating preferably is an organic insulative coating having a thickness of about 0.5um to about 2.0um that can be thermally decomposed during free air ball formation.
  • the wires 30 preferably have a melting temperature (Tg) of about 180° to 350 0 C.
  • the balls 12 are made of a soft material so that the wires 30 can be readily wirebonded thereto.
  • the wires 30 are made of a stiffer or more rigid material, such as copper or a hard gold alloy so that during wirebonding, the wires 30 penetrate into and are embedded within the balls 12.
  • a harder material for the wires 30 allows the wires 30 to penetrate into the balls 12, hence forming a connection by embedding the hard wires 30 in the softer balls 12.
  • FIG. 2 another embodiment of a packaged device 32 is shown.
  • the die 20 is attached to a heat sink 34.
  • the heat sink 34 preferably is coplanar with and surrounded by a plurality of the balls 12. More particularly, a first surface of the heat sink 32 to which the die is attached is coplanar with the top surface of the balls 12 and a second, opposing surface of the heat sink 34 is coplanar with the bottom surface 16 of the balls 12. Thus, the second side of the heat sink 34 is exposed.
  • the heat sink 34 preferably has a thickness that is equal to a diameter of the balls 12 as measured from the top, flat surface 14 to the bottom surface 16.
  • the die 20 may be attached to the heat sink 34 with a die attach adhesive or solder (not shown) .
  • the heat sink 34 preferably is formed of a solid metal plate, such as copper slug. The heat sink 34 further improves the thermal performance and increases the solderable area of the package 32.
  • FIG. 3 yet another alternative of a packaged device 36 is shown.
  • the packaged device 36 is similar to the packaged device 32 (FIG. 2) except that a second mold compound 38 has been formed over the die 20, wires 30 and top surfaces 14 of the balls 12 as a glob top.
  • dams or flanges 40 are formed at the sides of the package to retain the second mold compound 38.
  • the dams 40 may be formed of the first mold compound 18. It will be appreciated that the glob top encapsulation process may be performed on a package with or without the heat sink 34. That is, although the packaged device 36 includes the heat sink 34, the heat sink 34 is not required.
  • FIGS. 4A-4H are enlarged cross-sectional views illustrating a platen or fixture 50 into which a plurality of conductive balls 12 is loaded.
  • the platen 50 is a block of metal having a large flat surface with a plurality of cavities or recesses 52 in which the balls 12 are loaded.
  • the cavities 52 are laid out in a grid or array on the surface of the platen 50.
  • FIG. 4A shows the balls 12 being loaded into the platen 50 and
  • FIG. 4B shows the balls 12 disposed within the cavities 52.
  • the cavities 52 are generally circular, as shown.
  • the cavities 52 may have a flat or partially flattened bottom surface so that the bottoms of the balls 12 can be flattened or partially flattened, such as by pressing.
  • the balls 12 may be loaded into the recesses 52 using known technology, such as a shaker.
  • the recesses 52 are spaced at a pitch to match the required ball pitch for a packaged device, such as 1.27mm apart.
  • the entire platen 50 is transferred into a mold cavity.
  • An alternative to using the platen 50 is to load the balls 12 into an array of holes located in the bottom of a mold cavity.
  • the balls 12 could be placed in such holes in a number of ways, such as with a mask. FIG.
  • the balls 14 are formed of a soft, conductive material that can be deformed, such as a soft metal.
  • Example metals are solder or gold.
  • most BGA balls are made out of 63/37 material (63% tin, 37% lead), which is very soft. Even when 90/10 (90% lead, 10% tin) material is used, the ball shape can deform. Referring now to FIGS.
  • the top surfaces 14 of the balls 12 are flattened either with a first top 58 of the mold, or by a press, via a mechanical coining process. That is, the mold top 58 is pressed against the top surfaces 14 of the balls 12 within the cavities 52 of the platen 50, which flattens the top surfaces 14 of the balls 12. If the cavities 52 also have a flat or partially flat bottom surface, then the bottom surfaces 16 of the balls 12 are flattened in the same way as the top surfaces 14. Thus, either one or both of the top and bottom surfaces 14 and 16 of the balls 12 are flattened or partially flattened.
  • a first injection molding process is performed such that the first mold compound 18 surround the balls 12. That is, the first mold compound 18 is injected into the mold and the first mold compound 18 surrounds the exposed portions of the balls 12. Injection molding is well known in the art and further description thereof is not required for a complete understanding of the invention.
  • the first top 58 of the mold is removed.
  • the balls 12 may be removed from the platen 50 or the balls 12 may remain in the platen 50 for further processing, as described below.
  • the balls 12 are shown detached or separated from the platen 50. However, in the presently preferred embodiment, the balls 12 are not yet removed from the platen 50.
  • the integrated circuit die 20 is attached to a plurality of the balls 12 at a predetermined location.
  • the die 20 has a bottom surface 22, and a top surface 26 that includes a plurality of wire bonding pads 28.
  • the bottom surface 22 of the die 20 is attached directly to the balls 12 with a die attach adhesive (not shown),.
  • the die 20 is attached at locations such that the die 20 is surrounded by a plurality of the balls 12.
  • the number of I/O's is used to determine the number of balls 12 that surround the die 20. Attaching the die 20 on the top surface 14 of a plurality of the balls 12 allows a platen into which the balls 12 are loaded to be uniform in size and have a single ball matrix pattern.
  • a single ball matrix pattern allows different size die and different package sizes to be formed without having to change the size of the platen. Further, as discussed above, the balls 12 upon which the die 20 is attached serve as a thermal path for the die 20 and provide a solderable surface that enhances board level solder joint strength.
  • the die could be soldered to the balls 12.
  • the die 20 can be attached to a heat sink 34 (e.g., a solid metal plate) with an epoxy or solder.
  • the heat sink 34 can further improve the thermal performance of the package'and increase the solderable area of the package.
  • the wire bonding pads 28 on the die 20 are electrically connected to respective ones of the balls 12 that surround the die 20. More particularly, bonding wires 30 are connected from the die wire bonding pads 28 to respective ones of the balls 12.
  • One end of the wires 30 is connected to the die bonding pads 28 and another end is connected to the balls 12 using a wire bonding process as is known in the art.
  • a wire bonding process as is known in the art.
  • an alternative to the ultrasonic force used in the traditional thermosonic wire bonding process may be used.
  • hard wire made of copper or a hard gold alloy is used to penetrate into the balls 12, which form connections by embedding the wires 30 into the balls 12.
  • tips of the wires 30 are embedded within * the balls 12. The tips are generally circular in shape and are formed by electric flame off (EFO) of the wires 30 by a wire bonding machine.
  • the die 20 the electrical connections, the wires 30 and a portion of the balls 12 are encapsulated with a second mold compound 24.
  • a second mold compound 24 is preferably a plastic material, as is known in the art for packaging integrated circuits.
  • the now packaged die 20 is removed from the mold and the platen 50, thereby uncovering the bottom surfaces of the array of balls 12, as shown in FIG. 1.
  • the exposed bottom surfaces 16 of the balls 12 may be coated or plated with a noble surface finish, (e.g., NI/Au) that is both resistant to corrosion and provides low contact resistance.
  • the exposed portions of the balls 12 may be coated via selective deposition of electrolytic Ni/Au platings.
  • FIG. 5A shows three such packages 60.
  • the packages 60 are separated by cutting along saw streets 62, preferably using a well-known saw singulation process, to form separate packaged devices 10, as shown in FIG. 5B.
  • the saw streets 62 are flanges that are formed of the first mold compound 18 during the first mold injection process.
  • the saw streets (flanges) 62 protect the balls 12 embedded in the first mold compound 18 during die attach, wire bonding and the second mold injection processes.
  • an optional electrical functional test may be performed prior to the saw singulation process. Since all of the I/O terminals of the encapsulated devices are separated throughout the packaging process, an electrical test in strip format is possible, hence improving tester utilization and making parallel testing possible without additional process or cost.
  • the packaged device has improved high-frequency electrical performance because the signal path from the die 20 to the board is shortened. Further, system reliability is improved by increasing solder joint resistance to stress failures caused by deflections of the system board. Improved RF performance and resistance to mechanical stress failures are important issues to cellular telephone handset makers. [0044]
  • the present invention provides an easy and inexpensive method of packaging an integrated circuit. Two layers of mold compound are used, with the C5 balls being embedded into the first layer of mold compound. The top surfaces of the C5 balls act as bond fingers and the bottom surfaces provide stand-off on a PCB.
  • a packaged device can include a heat slug for better thermal performance. Further, the device may be formed using a glob top encapsulation.
  • the device cost is low because neither a substrate nor terminations (external pins) are required. Since there is no metal leadframe, the saw blade used in the singulation step does not have to cut through metal, so the saw blade will have a longer life. Also, since no leadframe is required, there is no need to perform substrate trace routing.
  • the packaging process does not require any chemical etch-back, which can be expensive. The packaging process may be performed using currently available equipment. The package also has a very low profile, down to about 0.4mm. Although a LGA package is described, other package types, such as QFN (Quad Flat No lead) also can be formed using the aforedescribed method. Stacked die devices can be packaged with this method too. Land grid arrays (LGA) offer high interconnection density, e.g., 200+ I/Os is possible.

Abstract

A method of packaging an integrated circuit die (12) includes the steps of loading an array of soft conductive balls (12) into recesses formed in a platen (50) and locating the platen (50) in a first part of a mold cavity. A second part of the mold is pressed against the balls (12) to flatten a surface of the balls. A first mold compound (18) then is injected into the mold cavity such that the mold compound (18) surrounds exposed portions of the balls (12). The balls are removed from the platen and a first side of an integrated circuit die (20) is attached to the balls (12). Die bonding pads (28) on a second side of the die are electrically connected to respective ones of the balls (12) surrounding the die (20), and then the die (20), the electrical connections (30), and a top portion of the conductive balls (12) is encapsulated with a second mold compound (24).

Description

PACKAGED DEVICE AND METHOD OF FORMING SAME BACKGROUND OF THE INVENTION
[0001] The present invention relates to integrated circuit packaging, and more particularly to an improved process for fabricating a Ball Grid Array (BGA) packaged device.
[0002] An integrated circuit (IC) die is a small device formed on a semiconductor wafer, such as a silicon wafer. A leadframe is a metal frame that usually includes a paddle that supports the IC die that has been cut from the wafer. The leadframe also has lead fingers that provide external electrical connections. That is, the die is attached to the die paddle and then bonding pads of the die are connected to the lead fingers via wire bonding or flip chip bumping to provide the external electrical connections . Encapsulating the die and wire bonds or flip chip bumps with a protective material forms a package. Depending on the package type, the external electrical connections may be used as-is, such as in a Thin Small Outline Package (TSOP) , or further processed, such as by attaching spherical solder balls for a BGA. These terminal points allow the die to be electrically connected with other circuits, such as on a printed circuit board. However, it can be expensive and time-consuming to form a leadframe and package a device if steps like chemical etching and etch back are required.
[0003] Thus, it would be desirable to eliminate such etching steps, and further, to eliminate the need for the leadframe. It is desirable to have a method of decreasing the size of packaged ICs too.
BRIEF DESCRIPTION OF THE DRAWINGS [0004] The following detailed description of preferred embodiments of the invention will be better understood when read in conjunction with the appended drawings . The present invention is illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements.
[0005] FIG. 1 is an enlarged cross-sectional view of a packaged integrated circuit in accordance with a first embodiment of the present invention;
[0006] FIG. 2 is an enlarged cross-sectional view of a packaged integrated circuit in accordance with a second embodiment of the present invention;
[0007] FIG. 3 is an enlarged cross-sectional view of a packaged integrated circuit in accordance with a third embodiment of the present invention;
[0008] FIGS. 4A-4H are perspective views illustrating^ the steps for fabricating packaged semiconductor devices in accordance with the present invention;
[0009] FIGS. 5A and 5B are cross-sectional views illustrating the formation of a plurality of packaged semiconductor devices in accordance with the present invention;
DETAILED DESCRIPTION OF THE INVENTION
[0010] The detailed description set forth below in connection with the appended drawings is intended as a description of the presently preferred embodiments of the invention, and is not intended to represent the only form in which the present invention may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the invention. Further, it will be understood by those of skill in the art that the drawings have been simplified and are not drawn to scale.
[0011] The present invention provides a method of packaging an integrated circuit die, including the steps of:
[0012] loading a plurality of conductive balls into recesses formed in a platen;
[0013] transferring the platen to a cavity of a first part of a mold;
[0014] pressing a second part of the mold against the conductive balls, thereby at least partially flattening a top surface of the conductive balls;
[0015] injecting a first mold compound into the mold, wherein the first mold compound surrounds exposed portions of the conductive balls;
[0016] removing the conductive balls from the platen, wherein the conductive balls are held together by the first mold compound;
[0017] attaching a first side of an integrated circuit die to a plurality of the conductive balls, wherein the die is surrounded by others of the conductive balls;
[0018] electrically connecting die bonding pads on a second side of the die to respective ones of the conductive balls surrounding the die; and [0019] encapsulating at least the second side of the die, the electrical connections, and at least part of the conductive balls with a second mold compound.
[0020] In another embodiment, a heat sink may be located coplanar with the conductive balls and the die attached to a surface of the heat sink.
[0021] The present invention further provides a packaged integrated circuit die having a plurality of conductive balls having a top, flattened surface and a first mold compound that holds the plurality of conductive balls together. The top, flattened surfaces of the balls are generally coplanar with a top surface of the first mold compound, and bottom, opposing surfaces of the balls are exposed. An integrated circuit die having a first side is attached to a plurality of the conductive balls. The die is surrounded by others of the conductive balls. The die is electrically coupled to the others of the conductive balls. A second mold compound encapsulates at least a second side of the die opposing the die first side, and the top surfaces of the conductive balls.
[0022] Referring now to FIG. 1, an enlarged cross-sectional view of a packaged semiconductor device 10 formed in accordance with an embodiment of the present invention is shown. The packaged device 10 includes a plurality of conductive balls 12 having a top, flattened surface 14 and bottom, opposing surface 16. A first mold compound 18 holds the plurality of conductive balls 12 together. The top, flattened surfaces 14 of the balls 12 are generally coplanar with a top surface of the first mold compound 18, and the bottom, opposing surfaces 16 of the balls 12 are exposed. An integrated circuit die 20 has a first side thereof 22 attached to a plurality of the conductive balls 12. The die 20 is surrounded by others of the conductive balls 12 and the die 20 is electrically coupled to the others of the conductive balls 12. A second mold compound 24 encapsulates at least a second side 26 of the die 20 opposing the die first side 22, and the top surfaces 14 of the conductive balls 12. The second mold compound 24 is of a type known to those of skill in the art that is commonly used for packaging integrated circuits.
[0023] The conductive balls 12 preferably are C5 (Controlled Collapse Chip Carrier Connection) solder balls. The balls 12 are made with an electrically conductive material so that electrical signals can be passed therethrough. The conductive material may be a metal, such as copper or gold, or an alloy thereof, or a soft solder, such as 63/37 material (63% tin, 37% lead) or 90/10 (90% lead, 10% tin) . Alternatively, the soft balls 14 may be formed of a polymer base material with metallic surface finish. A lead free package can be achieved by using lead free metallic balls .
[0024] The bottom surfaces 16 of the balls 12 are exposed and allow the integrated circuit die 12 to be connected to a printed circuit board. The balls 12 are used to pass data, power and ground signals to/from the die 20 and a substrate or printed, circuit board (not shown) , as is known by those of skill in the art, while others of the balls 12 to which the die 20 is attached can conduct heat from the die 20 (i.e., thermal management) and enhance board level solder joint strength. That is, the balls 12 under the die 20 provide a solderable surface that enhances board level solder strength. It is noted that balls at the corners and even along the package edges also can provide connections that enhance the mechanical strength of the package. [0025] The top surfaces 16 of the balls 12 are flattened and coplanar. The top surfaces 16 may be flattened by pressing, as discussed in more detail below. The balls 12 are held together with the first mold compound 18. The first mold compound 18 is of a type known to those of skill in the art that is commonly used for packaging integrated circuits.
[0026] The integrated circuit die 20 may be any type of known- die, such as one cut from a silicon wafer, and may be any type of circuit, such as a digital signal processor, a special purpose circuit, etc. Such circuits are well known to those of skill in the art. The bottom surface 22 of the die 20 is attached to the top flattened surfaces 14 of one or more of the conductive balls 12 with a die attach material (not shown) . The die attach material may be an adhesive of a type well known in the semiconductor art for attaching dies to substrates, such as an epoxy.
[0027] The top surface 26 of the integrated circuit die 20 includes a plurality of die bonding pads 28. The die bonding pads 28 are electrically connected to ones of the conductive balls 12 that surround the die 20. In one embodiment, the die bonding pads 28 are connected to the conductive balls 12 with wires 30 via wirebonding. Known wirebonding processes, such as thermosonic wire bonding may be used to connect the wires 30 to the die bonding pads 28 and the top surface 14 of the balls 12.
[0028] As is known by those of skill in the art, various size wires are available for connecting die to substrates, with the wire size being selected based on, among other things, pad pitch. The bond wire 30 has a diameter of between about 15urn to about 55um, although other diameter bond wires may be used and the invention should not be limited to a particular bond wire diameter. For example, 63um pitch applications use 25um diameter wire, while 52um and 44um pitch applications use 20.3um diameter wire. Development is being done for a 37um pitch application using 17um diameter wire. Thus, as is known in the art, fine pitch and ultra-fine pitch wire bonding processes may be performed depending on the pad pitch. In one embodiment of the invention, insulated bond wire is used. Insulated bond wire comprises a conductive core coated with an electrically insulating material and is suitable for fine pitch and ultra- fine pitch wirebonding. The insulating material prevents the wire from shorting to other wires or other conductive structures. In general, gold and aluminum are the most commonly used elements to make the conductive core of the bonding wire. Both gold and aluminum are strong and ductile and have similar resistance in most environments. Gold wire is sometimes doped with a dopant, such as beryllium, calcium in order to stabilize it. Small-diameter aluminum wire is often doped with silicon or sometimes magnesium to improve its breaking load and elongation parameters. In addition to gold and aluminum, copper, palladium-alloy, platinum and silver bonding wire are also known. In an embodiment of the invention, insulated wires having a diameter of less than about 25 um are used. The insulative coating preferably is an organic insulative coating having a thickness of about 0.5um to about 2.0um that can be thermally decomposed during free air ball formation. Further, the wires 30 preferably have a melting temperature (Tg) of about 180° to 3500C.
[0029] The balls 12 are made of a soft material so that the wires 30 can be readily wirebonded thereto. Preferably, the wires 30 are made of a stiffer or more rigid material, such as copper or a hard gold alloy so that during wirebonding, the wires 30 penetrate into and are embedded within the balls 12. - Using a harder material for the wires 30 allows the wires 30 to penetrate into the balls 12, hence forming a connection by embedding the hard wires 30 in the softer balls 12.
[0030] Referring now to FIG. 2, another embodiment of a packaged device 32 is shown. In this embodiment, instead of attaching the die 20 to the balls 12, the die 20 is attached to a heat sink 34. The heat sink 34 preferably is coplanar with and surrounded by a plurality of the balls 12. More particularly, a first surface of the heat sink 32 to which the die is attached is coplanar with the top surface of the balls 12 and a second, opposing surface of the heat sink 34 is coplanar with the bottom surface 16 of the balls 12. Thus, the second side of the heat sink 34 is exposed. The heat sink 34 preferably has a thickness that is equal to a diameter of the balls 12 as measured from the top, flat surface 14 to the bottom surface 16. The die 20 may be attached to the heat sink 34 with a die attach adhesive or solder (not shown) . In order to provide good thermal properties, the heat sink 34 preferably is formed of a solid metal plate, such as copper slug. The heat sink 34 further improves the thermal performance and increases the solderable area of the package 32.
[0031] Referring now to FIG. 3, yet another alternative of a packaged device 36 is shown. The packaged device 36 is similar to the packaged device 32 (FIG. 2) except that a second mold compound 38 has been formed over the die 20, wires 30 and top surfaces 14 of the balls 12 as a glob top. In order to perform the glob top encapsulation process, dams or flanges 40 are formed at the sides of the package to retain the second mold compound 38. The dams 40 may be formed of the first mold compound 18. It will be appreciated that the glob top encapsulation process may be performed on a package with or without the heat sink 34. That is, although the packaged device 36 includes the heat sink 34, the heat sink 34 is not required.
[0032] Referring now to FIGS. 4A-4H, a method for packaging an IC die in accordance with an embodiment of the present invention will be described. FIGS. 4A and 4B are enlarged cross-sectional views illustrating a platen or fixture 50 into which a plurality of conductive balls 12 is loaded. The platen 50 is a block of metal having a large flat surface with a plurality of cavities or recesses 52 in which the balls 12 are loaded. The cavities 52 are laid out in a grid or array on the surface of the platen 50. FIG. 4A shows the balls 12 being loaded into the platen 50 and FIG. 4B shows the balls 12 disposed within the cavities 52. The cavities 52 are generally circular, as shown. However, the cavities 52 may have a flat or partially flattened bottom surface so that the bottoms of the balls 12 can be flattened or partially flattened, such as by pressing. The balls 12 may be loaded into the recesses 52 using known technology, such as a shaker. The recesses 52 are spaced at a pitch to match the required ball pitch for a packaged device, such as 1.27mm apart. Once the balls are loaded in the recesses 52, the entire platen 50 is transferred into a mold cavity. An alternative to using the platen 50 is to load the balls 12 into an array of holes located in the bottom of a mold cavity. The balls 12 could be placed in such holes in a number of ways, such as with a mask. FIG. 4C shows the balls 12 being placed in a platen 54 that has recesses 52 and a space 56 for a heat sink 34. In this embodiment, the heat sink 34 is placed in the space 56 prior to loading the balls 12 into the recesses 52. [0033] As previously discussed, the balls 14 are formed of a soft, conductive material that can be deformed, such as a soft metal. Example metals are solder or gold. As is known by those of skill in the art, most BGA balls are made out of 63/37 material (63% tin, 37% lead), which is very soft. Even when 90/10 (90% lead, 10% tin) material is used, the ball shape can deform. Referring now to FIGS. 4D and 4E, after the balls 12 are located in the platen 50, the top surfaces 14 of the balls 12 are flattened either with a first top 58 of the mold, or by a press, via a mechanical coining process. That is, the mold top 58 is pressed against the top surfaces 14 of the balls 12 within the cavities 52 of the platen 50, which flattens the top surfaces 14 of the balls 12. If the cavities 52 also have a flat or partially flat bottom surface, then the bottom surfaces 16 of the balls 12 are flattened in the same way as the top surfaces 14. Thus, either one or both of the top and bottom surfaces 14 and 16 of the balls 12 are flattened or partially flattened.
[0034] Referring now to FIG. 4F, after the mechanical coining process, a first injection molding process is performed such that the first mold compound 18 surround the balls 12. That is, the first mold compound 18 is injected into the mold and the first mold compound 18 surrounds the exposed portions of the balls 12. Injection molding is well known in the art and further description thereof is not required for a complete understanding of the invention.
[0035] Referring to FIG. 4G, after the first mold compound 18 solidifies, the first top 58 of the mold is removed. At this point, the balls 12 may be removed from the platen 50 or the balls 12 may remain in the platen 50 for further processing, as described below. For illustrative purposes, in FIG. 4G the balls 12 are shown detached or separated from the platen 50. However, in the presently preferred embodiment, the balls 12 are not yet removed from the platen 50.
[0036] Referring to FIG. 4H, the integrated circuit die 20 is attached to a plurality of the balls 12 at a predetermined location. The die 20 has a bottom surface 22, and a top surface 26 that includes a plurality of wire bonding pads 28. In the presently preferred embodiment, the bottom surface 22 of the die 20 is attached directly to the balls 12 with a die attach adhesive (not shown),. The die 20 is attached at locations such that the die 20 is surrounded by a plurality of the balls 12. The number of I/O's is used to determine the number of balls 12 that surround the die 20. Attaching the die 20 on the top surface 14 of a plurality of the balls 12 allows a platen into which the balls 12 are loaded to be uniform in size and have a single ball matrix pattern. A single ball matrix pattern allows different size die and different package sizes to be formed without having to change the size of the platen. Further, as discussed above, the balls 12 upon which the die 20 is attached serve as a thermal path for the die 20 and provide a solderable surface that enhances board level solder joint strength.
[0037] As previously discussed, other options for die attach exist. For example, instead of a die attach adhesive, the die could be soldered to the balls 12. Further, as shown in FIGS. 2 and 3, the die 20 can be attached to a heat sink 34 (e.g., a solid metal plate) with an epoxy or solder. The heat sink 34 can further improve the thermal performance of the package'and increase the solderable area of the package. [0038] Referring again to FIG. 4H, after the die 20 has been attached to the balls 12, as described above, the wire bonding pads 28 on the die 20 are electrically connected to respective ones of the balls 12 that surround the die 20. More particularly, bonding wires 30 are connected from the die wire bonding pads 28 to respective ones of the balls 12. One end of the wires 30 is connected to the die bonding pads 28 and another end is connected to the balls 12 using a wire bonding process as is known in the art. However, as the balls 12 are held together with the first mold compound 18, in order that the structure of the first mold compound 18 is not compromised, an alternative to the ultrasonic force used in the traditional thermosonic wire bonding process may be used. For example, instead of applying the traditional thermosonic bonding, hard wire made of copper or a hard gold alloy is used to penetrate into the balls 12, which form connections by embedding the wires 30 into the balls 12. As shown in FIG. 4H, tips of the wires 30 are embedded within * the balls 12. The tips are generally circular in shape and are formed by electric flame off (EFO) of the wires 30 by a wire bonding machine.
[0039] Referring back to FIG. 1, after the wirebonding process is performed, the die 20, the electrical connections, the wires 30 and a portion of the balls 12 are encapsulated with a second mold compound 24. Again, a known injection molding process is used. The second mold compound is preferably a plastic material, as is known in the art for packaging integrated circuits.
[0040] After the encapsulation process, the now packaged die 20 is removed from the mold and the platen 50, thereby uncovering the bottom surfaces of the array of balls 12, as shown in FIG. 1. To ensure reliable interconnection performance, the exposed bottom surfaces 16 of the balls 12 may be coated or plated with a noble surface finish, (e.g., NI/Au) that is both resistant to corrosion and provides low contact resistance. The exposed portions of the balls 12 may be coated via selective deposition of electrolytic Ni/Au platings.
[0041] Referring now to FIG. 5A, rather than forming a single package, multiple packages are formed at the same time. FIG. 5A shows three such packages 60. The packages 60 are separated by cutting along saw streets 62, preferably using a well-known saw singulation process, to form separate packaged devices 10, as shown in FIG. 5B. The saw streets 62 are flanges that are formed of the first mold compound 18 during the first mold injection process. The saw streets (flanges) 62 protect the balls 12 embedded in the first mold compound 18 during die attach, wire bonding and the second mold injection processes.
[0042] Prior to the saw singulation process, an optional electrical functional test may be performed. Since all of the I/O terminals of the encapsulated devices are separated throughout the packaging process, an electrical test in strip format is possible, hence improving tester utilization and making parallel testing possible without additional process or cost.
[0043] The packaged device has improved high-frequency electrical performance because the signal path from the die 20 to the board is shortened. Further, system reliability is improved by increasing solder joint resistance to stress failures caused by deflections of the system board. Improved RF performance and resistance to mechanical stress failures are important issues to cellular telephone handset makers. [0044] The present invention provides an easy and inexpensive method of packaging an integrated circuit. Two layers of mold compound are used, with the C5 balls being embedded into the first layer of mold compound. The top surfaces of the C5 balls act as bond fingers and the bottom surfaces provide stand-off on a PCB. A packaged device can include a heat slug for better thermal performance. Further, the device may be formed using a glob top encapsulation. The device cost is low because neither a substrate nor terminations (external pins) are required. Since there is no metal leadframe, the saw blade used in the singulation step does not have to cut through metal, so the saw blade will have a longer life. Also, since no leadframe is required, there is no need to perform substrate trace routing. The packaging process does not require any chemical etch-back, which can be expensive. The packaging process may be performed using currently available equipment. The package also has a very low profile, down to about 0.4mm. Although a LGA package is described, other package types, such as QFN (Quad Flat No lead) also can be formed using the aforedescribed method. Stacked die devices can be packaged with this method too. Land grid arrays (LGA) offer high interconnection density, e.g., 200+ I/Os is possible.
[0045] While the preferred embodiments of the invention have been illustrated and described, it will be clear that the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions and equivalents will be apparent to those skilled in the art without departing from the spirit and scope of the invention as described in the claims.

Claims

1. A method of packaging an integrated circuit die, comprising the steps of: loading a plurality of conductive balls into recesses formed in a platen; transferring the platen to a cavity of a first part of a mold; pressing a second part of the mold against the conductive balls, thereby closing the mold and at least partially flattening a top surface of the conductive balls; injecting a first mold compound into the mold, wherein the first mold compound surrounds exposed portions of the conductive balls and holds the conductive balls together; removing the second part of the mold to expose the top surface of the conductive balls; attaching a first side of an integrated circuit die to a plurality of the conductive balls, wherein the die is surrounded by others of the conductive balls; electrically connecting die bonding pads on a second side of the die to respective ones of the conductive balls surrounding the die; and encapsulating at least the second side of the die, the electrical connections, and at least part of the top surface of ■ the conductive balls with a second mold compound.
2. The method of packaging an integrated circuit die of claim 1, wherein a mask is used to transfer and place the conductive balls into a bottom cavity of the mold.
3. The method of packaging an integrated circuit die of claim 1, wherein the conductive balls comprise solder balls.
4. The method of packaging an integrated circuit die of claim 1, wherein the platen has an array of recesses for receiving the conductive balls.
5. The method of packaging an integrated circuit die of claim 4, wherein the recesses are spaced at a predetermined pitch.
6. The method of packaging an integrated circuit die of claim 5, wherein the platen includes a space for receiving a heat sink, the method further comprising the step of placing a heat sink within the heat sink receiving area.
7. The method of packaging an integrated circuit die of claim 6, wherein the heat sink has a first side that is generally coplanar with the flattened top surface of the conductive balls and wherein the die attaching step comprises attaching the first side of the die to the first side of the heat sink.
8. The method of packaging an integrated circuit die of claim 1, wherein in the die attaching step, the die is attached to the flattened, top surface of a plurality of the conductive balls.
9. The method of packaging an integrated circuit die of claim 1, wherein the electrically connecting step comprises wirebonding the die bonding pads to the respective ones of the balls with a corresponding plurality of wires .
10. The method of packaging an integrated circuit die of claim 9, wherein in the wirebonding step, the wires penetrate into the balls and are embedded therein.
11. The method of packaging an integrated circuit die of claim 10, wherein the wires are insulated wires.
12. The method of packaging an integrated circuit die of claim 10, wherein the balls are formed of a metal that is softer than the wires so that the wires are embedded in the balls.
13. The method of packaging an integrated circuit die of claim 9, wherein the wires are attached to the top, flattened surface of the balls.
14. The method of packaging an integrated circuit die of claim 1, further comprising the step of saw singulating the encapsulated die from adjacent encapsulated die.
15. The method of packaging an integrated circuit die of claim 1, wherein the conductive balls are embedded into the first mold compound with the flattened surface of the balls being substantially coplanar with a top surface of the first mold compound.
16. The method of packaging an integrated circuit die of claim 15, wherein a surface of the conductive balls opposing the flattened surface of the balls protrudes beyond a bottom surface of the first mold compound.
17. The method of packaging an integrated circuit die of claim 1, wherein the encapsulating step comprises performing a glob top encapsulation process.
18. A packaged integrated circuit die assembled in accordance with claim 1.
19. A method of packaging a plurality of integrated circuit dice, comprising the steps of : loading a plurality of conductive balls into recesses formed in a platen; transferring the platen to a cavity of a first part of a mold; pressing a second part of the mold against the conductive balls, thereby at least partially flattening a top surface of the conductive balls; injecting a first mold compound into the mold, wherein the first mold compound surrounds exposed portions of the conductive balls; attaching first sides of a plurality of integrated circuit dies on the plurality of the conductive balls at predetermined locations, wherein the dies are surrounded by others of the conductive balls; electrically connecting die bonding pads on second sides of the dies to respective ones of the conductive balls surrounding the dies; encapsulating at least the second sides of the dies, the electrical connections, and at least part of the conductive balls with a second mold compound; and singulating adjacent encapsulated dies to form individual packaged devices.
20. A packaged integrated circuit die, comprising: a plurality of conductive balls having top, flattened surfaces; a first mold compound that holds the plurality of conductive balls together, wherein the top, flattened surfaces are generally coplanar with a top surface of the first mold compound, and bottom, opposing surfaces of the balls are exposed; an integrated circuit die having a first side attached to a plurality of the conductive balls, wherein the die is surrounded by others of the conductive balls, and wherein the die is electrically connected to the others of the conductive balls; and a second mold compound encapsulating at least a second side of the die opposing the die first side, and the top surfaces of the conductive balls .
PCT/US2005/034261 2004-10-23 2005-09-27 Packaged device and method of forming same WO2006047028A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
MYPI20044381A MY136179A (en) 2004-10-23 2004-10-23 Packaged device and method of forming same
MYPI20044381 2004-10-23
US11/191,132 2005-07-27
US11/191,132 US7179682B2 (en) 2004-10-23 2005-07-27 Packaged device and method of forming same

Publications (2)

Publication Number Publication Date
WO2006047028A2 true WO2006047028A2 (en) 2006-05-04
WO2006047028A3 WO2006047028A3 (en) 2007-04-05

Family

ID=36228201

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/034261 WO2006047028A2 (en) 2004-10-23 2005-09-27 Packaged device and method of forming same

Country Status (2)

Country Link
US (1) US7285855B2 (en)
WO (1) WO2006047028A2 (en)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6930256B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
US7548430B1 (en) 2002-05-01 2009-06-16 Amkor Technology, Inc. Buildup dielectric and metallization process and semiconductor package
US9691635B1 (en) 2002-05-01 2017-06-27 Amkor Technology, Inc. Buildup dielectric layer having metallization pattern semiconductor package fabrication method
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US10811277B2 (en) 2004-03-23 2020-10-20 Amkor Technology, Inc. Encapsulated semiconductor package
US11081370B2 (en) 2004-03-23 2021-08-03 Amkor Technology Singapore Holding Pte. Ltd. Methods of manufacturing an encapsulated semiconductor device
US20080123318A1 (en) * 2006-11-08 2008-05-29 Atmel Corporation Multi-component electronic package with planarized embedded-components substrate
US7550857B1 (en) 2006-11-16 2009-06-23 Amkor Technology, Inc. Stacked redistribution layer (RDL) die assembly package
US7847398B2 (en) * 2007-08-01 2010-12-07 Amkor Technology, Inc. Semiconductor device having a stacked bump to reduce kirkendall voids and or cracks and method of manufacturing
US7960827B1 (en) 2009-04-09 2011-06-14 Amkor Technology, Inc. Thermal via heat spreader package and method
US8623753B1 (en) 2009-05-28 2014-01-07 Amkor Technology, Inc. Stackable protruding via package and method
US8222538B1 (en) 2009-06-12 2012-07-17 Amkor Technology, Inc. Stackable via package and method
US8471154B1 (en) 2009-08-06 2013-06-25 Amkor Technology, Inc. Stackable variable height via package and method
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US8536462B1 (en) 2010-01-22 2013-09-17 Amkor Technology, Inc. Flex circuit package and method
US8300423B1 (en) 2010-05-25 2012-10-30 Amkor Technology, Inc. Stackable treated via package and method
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8338229B1 (en) 2010-07-30 2012-12-25 Amkor Technology, Inc. Stackable plasma cleaned via package and method
US8717775B1 (en) 2010-08-02 2014-05-06 Amkor Technology, Inc. Fingerprint sensor package and method
US8337657B1 (en) 2010-10-27 2012-12-25 Amkor Technology, Inc. Mechanical tape separation package and method
US8482134B1 (en) 2010-11-01 2013-07-09 Amkor Technology, Inc. Stackable package and method
US9748154B1 (en) 2010-11-04 2017-08-29 Amkor Technology, Inc. Wafer level fan out semiconductor device and manufacturing method thereof
US8525318B1 (en) 2010-11-10 2013-09-03 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8557629B1 (en) 2010-12-03 2013-10-15 Amkor Technology, Inc. Semiconductor device having overlapped via apertures
US8535961B1 (en) 2010-12-09 2013-09-17 Amkor Technology, Inc. Light emitting diode (LED) package and method
US9721872B1 (en) 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
US9013011B1 (en) 2011-03-11 2015-04-21 Amkor Technology, Inc. Stacked and staggered die MEMS package and method
KR101140113B1 (en) 2011-04-26 2012-04-30 앰코 테크놀로지 코리아 주식회사 Semiconductor device
US8653674B1 (en) 2011-09-15 2014-02-18 Amkor Technology, Inc. Electronic component package fabrication method and structure
US8633598B1 (en) 2011-09-20 2014-01-21 Amkor Technology, Inc. Underfill contacting stacking balls package fabrication method and structure
US9029962B1 (en) 2011-10-12 2015-05-12 Amkor Technology, Inc. Molded cavity substrate MEMS package fabrication method and structure
US20150216051A1 (en) * 2011-12-21 2015-07-30 Lawrence Livermore National Security, Llc Method of fabricating electrical feedthroughs using extruded metal vias
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
KR101366461B1 (en) 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 Semiconductor device and manufacturing method thereof
KR101488590B1 (en) 2013-03-29 2015-01-30 앰코 테크놀로지 코리아 주식회사 Semiconductor device and manufacturing method thereof
KR101607981B1 (en) 2013-11-04 2016-03-31 앰코 테크놀로지 코리아 주식회사 Interposer and method for manufacturing the same, and semiconductor package using the same
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6148900A (en) * 1996-04-26 2000-11-21 Ngk Spark Plug Co., Ltd. Connecting board for connection between base plate and mounting board
US6551862B2 (en) * 2000-11-02 2003-04-22 Hitachi, Ltd. Semiconductor device and method of manufacturing the same
US6992380B2 (en) * 2003-08-29 2006-01-31 Texas Instruments Incorporated Package for semiconductor device having a device-supporting polymeric material covering a solder ball array area

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5695109A (en) 1995-11-22 1997-12-09 Industrial Technology Research Institute Solder paste inter-layer alignment apparatus for area-array on-board rework
US5830800A (en) * 1997-04-11 1998-11-03 Compeq Manufacturing Company Ltd. Packaging method for a ball grid array integrated circuit without utilizing a base plate
US6635957B2 (en) * 1998-06-10 2003-10-21 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
JP2000022044A (en) * 1998-07-02 2000-01-21 Mitsubishi Electric Corp Semiconductor device and its manufacture
KR100960739B1 (en) * 1999-02-26 2010-06-01 텍사스 인스트루먼츠 인코포레이티드 Thermally enhanced semiconductor ball grid array device and method of fabrication
US6661862B1 (en) * 2000-05-26 2003-12-09 Adtran, Inc. Digital delay line-based phase detector
US20020113322A1 (en) * 2000-06-12 2002-08-22 Shinichi Terashima Semiconductor device and method to produce the same
US6489571B1 (en) * 2000-10-31 2002-12-03 Lsi Logic Corporation Molded tape ball grid array package
US7056766B2 (en) * 2003-12-09 2006-06-06 Freescale Semiconductor, Inc. Method of forming land grid array packaged device
US7160755B2 (en) * 2005-04-18 2007-01-09 Freescale Semiconductor, Inc. Method of forming a substrateless semiconductor package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6148900A (en) * 1996-04-26 2000-11-21 Ngk Spark Plug Co., Ltd. Connecting board for connection between base plate and mounting board
US6551862B2 (en) * 2000-11-02 2003-04-22 Hitachi, Ltd. Semiconductor device and method of manufacturing the same
US6992380B2 (en) * 2003-08-29 2006-01-31 Texas Instruments Incorporated Package for semiconductor device having a device-supporting polymeric material covering a solder ball array area

Also Published As

Publication number Publication date
US7285855B2 (en) 2007-10-23
US20070114664A1 (en) 2007-05-24
WO2006047028A3 (en) 2007-04-05

Similar Documents

Publication Publication Date Title
US7285855B2 (en) Packaged device and method of forming same
US7205178B2 (en) Land grid array packaged device and method of forming same
US7056766B2 (en) Method of forming land grid array packaged device
US7816187B2 (en) Method for fabricating semiconductor package free of substrate
US8134225B2 (en) Quad flat no-lead chip carrier with standoff
US7985631B2 (en) Semiconductor assembly with one metal layer after base metal removal
US7927918B2 (en) Packaged products, including stacked package modules, and methods of forming same
US7423340B2 (en) Semiconductor package free of substrate and fabrication method thereof
US7939383B2 (en) Method for fabricating semiconductor package free of substrate
US20070099341A1 (en) Method of making stacked die package
WO2005067526A2 (en) Flipchip qfn package and method therefore
KR20050103234A (en) Multi-die semiconductor package
US7179682B2 (en) Packaged device and method of forming same
US7354796B2 (en) Method for fabricating semiconductor package free of substrate
US6075281A (en) Modified lead finger for wire bonding
US20050194665A1 (en) Semiconductor package free of substrate and fabrication method thereof
US20050184368A1 (en) Semiconductor package free of substrate and fabrication method thereof
KR100876876B1 (en) Chip stack package

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BW BY BZ CA CH CN CO CR CU CZ DK DM DZ EC EE EG ES FI GB GD GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV LY MD MG MK MN MW MX MZ NA NG NO NZ OM PG PH PL PT RO RU SC SD SG SK SL SM SY TJ TM TN TR TT TZ UG US UZ VC VN YU ZA ZM

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SZ TZ UG ZM ZW AM AZ BY KG MD RU TJ TM AT BE BG CH CY DE DK EE ES FI FR GB GR HU IE IS IT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 200580036220.9

Country of ref document: CN

Ref document number: 3028/DELNP/2007

Country of ref document: IN

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 05799688

Country of ref document: EP

Kind code of ref document: A2