WO2006046806A1 - Method of supplying flux to semiconductor device - Google Patents

Method of supplying flux to semiconductor device Download PDF

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Publication number
WO2006046806A1
WO2006046806A1 PCT/KR2005/003186 KR2005003186W WO2006046806A1 WO 2006046806 A1 WO2006046806 A1 WO 2006046806A1 KR 2005003186 W KR2005003186 W KR 2005003186W WO 2006046806 A1 WO2006046806 A1 WO 2006046806A1
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WO
WIPO (PCT)
Prior art keywords
flux
semiconductor device
under ball
ball metallurgy
supplying
Prior art date
Application number
PCT/KR2005/003186
Other languages
French (fr)
Inventor
Myung-Soon Park
Original Assignee
Korea Semiconductor System Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Korea Semiconductor System Co., Ltd. filed Critical Korea Semiconductor System Co., Ltd.
Publication of WO2006046806A1 publication Critical patent/WO2006046806A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/11318—Manufacturing methods by local deposition of the material of the bump connector in liquid form by dispensing droplets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Definitions

  • a dipping operation is carried out. That is, the semiconductor device having the plated parts is dipped into a flux bath so that flux is applied to the plated parts.
  • predetermined heat is applied to the plated parts through a reflow process, so that each plated part is shaped into a ball due to the flux.
  • bumps are made on the under ball metallurgy.
  • a flux cleaning process is executed. That is, a cleaning liquid is supplied to the semiconductor device to remove flux residue and impurities from the semiconductor device. Consequently, a semiconductor device having bumps at predetermined positions is obtained.

Abstract

The object of this invention is to provide a flux supplying method, which precisely supplies a proper amount of flux to each of a plurality of bumps that are made on a semiconductor device, thus preventing a large amount of waste water from being produced due to excessive flux when the semiconductor device is washed, and allowing a flux supplying operation for a small or large amount of semiconductor devices to be easily executed. According to this invention, a fluid supply unit (30) supplies a molten fluid compound, that is, flux (40) having a predetermined diameter, only to the bump (50) made on the semiconductor device (10) at a predetermined speed through metal jetting.

Description

[DESCRIPTION] [InventionTitle]
METHOD OF SUPPLYING FLUX TO SEMICONDUCTOR DEVICE
[Technical Field]
The present invention relates generally to a method of supplying flux to a semiconductor device and, more particularly, to a flux supplying method, which precisely supplies a proper amount of flux to each of a plurality of bumps that are made on a semiconductor device, thus preventing a large amount of waste water from being produced due to excessive flux when the semiconductor device is washed, and allowing a flux supplying operation for a small or large amount of semiconductor devices to be easily executed.
[Background Art]
Generally, a semiconductor device has several tens of semiconductor chips. Each of the semiconductor chips is provided with under ball metallurgy on which a bump is made to ensure a superior electrical connection, when the semiconductor chip is connected to a substrate. In order to make bumps on under ball metallurgy, a screen printing method, an electroplating method, a deposition method, etc. have been proposed.
According to the screen printing method, a passivation film is formed on an upper surface of a wafer other than under ball metallurgy so as to protect a pattern formed on the wafer. Next, a three-layered metal film comprising titanium (Ti), tungsten (W), and gold (Au), that is, an upper barrier metal is deposited on the under ball metallurgy and the passivation film through a metal deposition process. Afterwards, a photoresist is applied to the upper barrier metal such that the under ball metallurgy is not electrically connected to each other. Thereafter, part of the upper barrier metal is eliminated through a photolithography process including an exposure step, a development step, an upper-barrier-metal etching step, and a stripping step. Thereby, the upper barrier metal remains on only the under ball metallurgy. In this case, since the upper barrier metal is the three-layered metal film, the upper-barrier-metal etching step is sequentially executed three times.
After the upper barrier metal is made only on the under ball metallurgy, a screen mask is laminated on the semiconductor device, and solder paste is applied to the under ball metallurgy using a squeezer. In this case, the upper barrier metal serves as a medium which enhances the coupling force between the under ball metallurgy and the solder paste. After the solder paste has been applied to the under ball metallurgy, flux is applied to the solder paste. In the case of using solder paste containing flux, an additional flux application process is not required. The flux is a kind of solvent which serves to neatly connect the under ball metallurgy to the solder paste, and prevents the formation of oxides, when the under ball metallurgy is connected to the solder paste, thus ensuring reliable connection.
Subsequently, a reflow process is carried out. When the solder paste is heated to a predetermined temperature in the reflow process, the solder paste is shaped into a ball due to the flux. Thereby, bumps are made on the under ball metallurgy. Next, a flux cleaning process is executed to remove flux residue and impurities from the wafer. Therefore, the wafer having the bumps at predetermined positions is obtained. Meanwhile, the conventional electroplating method is executed as follows. First, a wafer having under ball metallurgy is prepared. A passivation layer is formed on an upper surface of the wafer other than the under ball metallurgy. Next, an upper barrier metal is deposited on the under ball metallurgy and the passivation layer through a metal deposition process. Subsequently, a photoresist is applied to an upper surface of the upper barrier metal, and parts of the photoresist disposed on the under ball metallurgy are eliminated through an exposure operation and a development operation, so that parts of the upper barrier metal disposed on the under ball metallurgy are exposed to the outside. At this time, photoresist residue remaining on the upper barrier metal is eliminated through an etching operation. Thereafter, a plated part is formed in an empty space above the under ball metallurgy through an electrolytic plating operation. Solder, Au, Ni, and others are used as a material for the plated part. After the plated part has been formed as such, surplus photoresist is stripped and eliminated. Thereafter, the upper barrier metal is etched so that parts of the upper barrier metal other than parts provided under the plated parts are eliminated. In this case, since the upper barrier metal is a three-layered metal film, the etching process is sequentially performed three times.
Thereafter, a dipping operation is carried out. That is, the semiconductor device having the plated parts is dipped into a flux bath so that flux is applied to the plated parts. Next, predetermined heat is applied to the plated parts through a reflow process, so that each plated part is shaped into a ball due to the flux. Thereby, bumps are made on the under ball metallurgy. Afterwards, a flux cleaning process is executed. That is, a cleaning liquid is supplied to the semiconductor device to remove flux residue and impurities from the semiconductor device. Consequently, a semiconductor device having bumps at predetermined positions is obtained.
[Disclosure]
[Technical Problem] However, the conventional flux supplying method is problematic in that flux is applied to an upper surface of a semiconductor device, so that a large amount of waste water may be produced during the flux washing process,* due to the excessive use of flux, thus causing water pollution. Further, high treatment costs are required to treat waste water, and the flux is unnecessarily wasted.
[Technical Solution]
Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and an object of the present invention is to provide a flux supplying method, which precisely supplies a proper amount of flux to each of a plurality of bumps that are made on a semiconductor device, thus preventing a large amount of waste water from being produced due to excessive flux when the semiconductor device is washed, and allowing a flux supplying operation for a small or large amount of semiconductor devices to be easily executed.
In order to accomplish the above object, the present invention provides a method of supplying flux to a bump made on under ball metallurgy of a semiconductor device to enhance electrical connection, wherein a fluid supply unit supplies a molten fluid compound, that is, flux having a predetermined diameter, only to the bump made on the under ball metallurgy of the semiconductor device at a predetermined speed through metal jetting.
[Advantageous Effects] [Description of Drawings]
.The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
FIGS. 1 and 2 are views to illustrate a flux supply process which supplies flux to a bump of a semiconductor device, according to the present invention.
[Best Mode]
[Mode for Invention]
Hereinafter, the preferred embodiment of the present invention will be described with reference to the accompanying drawings.
FIG. 1 is a view to illustrate a wafer positioning operation, according to the present invention, and FIG. 2 is a view to illustrate a flux supplying operation according to the present invention, in which flux is supplied to a bump of the semiconductor device.
Referring to FIGS. 1 and 2, the flux supplying method according to the present invention is executed as follows. That is, a fluid supplying unit 30 supplies a molten fluid compound, that is, flux 40 having a predetermined diameter, only to bumps 50 made on a semiconductor device 10, at a predetermined speed through metal jetting.
In a detailed description, a predetermined amount of flux 40, which is the molten fluid compound of a predetermined size, is jetted onto a predetermined position on the semiconductor device 10 at a predetermined speed through metal jetting using the fluid supplying unit 30, so that the flux 40 is supplied only to the bumps 50 which are made on the under ball metallurgy 20 of the semiconductor device 10. The semiconductor device 10 is moved such that preset position coordinates thereof are sequentially precisely located under the fluid supplying unit 30. Thus, the molten flux 40 supplied from the fluid supplying unit 30 accurately falls onto each of the bumps 50 of the under ball metallurgy 20.
When the flux 40 has been supplied to each of the bumps 50 in this way, a reflow step is executed.
In the reflow step, the bump 50 provided on the under ball metallurgy 20 is heated to a predetermined temperature. The heated bump 50 is shaped into a ball due to surface tension, so that a desired bump 50 is obtained.
[industrial Applicability]
As described above, the present invention provides a flux supplying method, which precisely supplies a proper amount of flux to each of a plurality of bumps that are made on a semiconductor device, thus preventing a large amount of waste water from being produced due to excessive flux when the semiconductor device is washed, and allowing a flux supplying operation for a small or large amount of semiconductor devices to be easily executed.

Claims

[CLAIMS] [Claim l]
A method of supplying flux to a bump made on under ball metallurgy of a semiconductor device to enhance electrical connection, wherein a fluid supply unit supplies a molten fluid compound, that is, flux having a predetermined diameter, only to the bump made on the under ball metallurgy of the semiconductor device at a predetermined speed through metal jetting.
PCT/KR2005/003186 2004-10-29 2005-09-26 Method of supplying flux to semiconductor device WO2006046806A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2004-0087184 2004-10-29
KR1020040087184A KR100560990B1 (en) 2004-10-29 2004-10-29 A flux supply method of semiconductor element

Publications (1)

Publication Number Publication Date
WO2006046806A1 true WO2006046806A1 (en) 2006-05-04

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101019385B1 (en) 2008-11-06 2011-03-07 고려대학교 산학협력단 Method for self-arranging of solder balls for packaging and soldering using the same
KR100923430B1 (en) * 2009-05-04 2009-10-27 주식회사 고려반도체시스템 Method of processing board for manufacturing semiconductor element

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5810988A (en) * 1994-09-19 1998-09-22 Board Of Regents, University Of Texas System Apparatus and method for generation of microspheres of metals and other materials
KR19990048003A (en) * 1997-12-08 1999-07-05 윤종용 Metal bump manufacturing method
US6224180B1 (en) * 1997-02-21 2001-05-01 Gerald Pham-Van-Diep High speed jet soldering system
US6264090B1 (en) * 1995-09-25 2001-07-24 Speedline Technologies, Inc. High speed jet soldering system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5810988A (en) * 1994-09-19 1998-09-22 Board Of Regents, University Of Texas System Apparatus and method for generation of microspheres of metals and other materials
US6264090B1 (en) * 1995-09-25 2001-07-24 Speedline Technologies, Inc. High speed jet soldering system
US6224180B1 (en) * 1997-02-21 2001-05-01 Gerald Pham-Van-Diep High speed jet soldering system
KR19990048003A (en) * 1997-12-08 1999-07-05 윤종용 Metal bump manufacturing method

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