WO2006035390A1

WO2006035390A1 - Liquid crystal display device having deep trench isolated cmos pixel transistors

Info

Publication number: WO2006035390A1
Application number: PCT/IB2005/053146
Authority: WO
Inventors: Lucian Remus Albu; Peter Johannes Michiel Janssen; Stefan Hausser
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2004-09-30
Filing date: 2005-09-22
Publication date: 2006-04-06

Abstract

A liquid crystal display (LCD) device employs a CMOS transfer switch (428). The CMOS transistors (510, 511) are electrically isolated from adjacent transistors (510, 511) by a deep trench (530) formed in the semiconductor substrate (520) in the field oxide region (570). The CMOS transistors (510, 511) can operate at a lower voltage than a comparable NMOS transfer switch (128). Also, pixel density of the device employing the CMOS transfer switch (428) is increased compared to a comparable device employing the NMOS transfer switches (128).

Description

LIQUID CRYSTAL DISPLAY DEVICE HAVING DEEP TRENCH ISOLATED CMOS PIXEL TRANSISTORS

This invention pertains to the field of liquid crystal display (LCD) devices, and in particular, to reflective liquid crystal display devices such as reflective liquid crystal on silicon (LCOS) devices. Liquid crystal display (LCD) devices, including reflective liquid crystal on silicon

(LCOS) devices, are increasingly popular.

FIG. 1 shows a partial schematic diagram of an LCD device 10 including a plurality of liquid crystal (LC) pixel cells 105. The device 10 includes a plurality of row (gate) lines 180, a plurality of column lines 190, and a plurality of (LC) pixel cells 105, including a counter electrode 1 15. Each LC pixel cell 105 comprises a transfer switch 128, a pixel capacitor 121 , a pixel electrode 125, and an LC material layer 130 disposed between the pixel electrode 125 and the counter electrode 1 15.

Typically, the LCD device 10 employs an NMOS transistor for the transfer switch 128. Beneficially, the LCD device 10 is a reflective liquid crystal on silicon (LCOS) device. FIG. 2 shows a cross-sectional view of a pixel 105 of a reflective LCOS device 20, which may be the LCD device 10. The device 20 includes a pixel substrate 100, a transparent substrate 1 10 having a transparent counter electrode 1 15 disposed thereon, and the liquid crystal (LC) material layer 130 disposed between the pixel substrate 100 and the transparent substrate 1 10. Beneficially, an alignment layer 135 (not shown) is further disposed between the liquid crystal material layer 130 and the pixel substrate 100. The pixel substrate 100 includes a semiconductor substrate 120, the plurality of reflective pixel electrodes 125 being disposed on the semiconductor substrate 120 and defining the plurality of pixel cells 105, a light shield layer 123 between the semiconductor substrate 120 and the plurality of reflective electrodes 125, and one or more intermetal dielectric layers, including at least one dielectric later 127 between the light shield layer 123 and the reflective pixel electrodes 125. In this case, the pixel electrode 125 is a reflective (mirror metal) pixel electrode. Also, beneficially the transfer switch 128 is a medium voltage NMOS device fabricated in the semiconductor substrate. As used herein, "medium voltage transistors" refers to transistors which are designed to operate at a maximum voltage of between ±3.5 V and ±20 V for dual-supply operation, or at a maximum voltage of between +7 V to +40V for single-supply operation.

FIG. 3 shows a cross-sectional view of a portion of the pixel substrate 100 including N-channel metal oxide semiconductor (NMOS) transistors 310, which may comprise the transfer switches 128 in FIGs. 1 and 2. In FIG. 3, two adjacent NMOS transistors 310 having channel regions 315 are disposed in adjacent P-well regions 305 of the semiconductor substrate 120. Each of the transistors 310 comprises a source 312, a drain 314, and a gate electrode 316 extending between the source 312 and drain 314 and disposed on an oxide layer 318 on the semiconductor substrate 120. The transistors 310 are separated and isolated from each other by a field oxide region 370, typically formed by local oxidation of silicon (LOCOS) and therefore also sometimes referred to as a LOCOS oxide film 370.

The field oxide region 370 separates and isolates the transistors 310 from each other. Therefore the field oxide region 370 must be designed such that when the transistors 310 are at their maximum operating voltages, the depletion regions of the transistors 310 do not "touch" each other. For a medium voltage NMOS transistor 310 with a maximum operating voltage range of 15 volts (and a breakdown voltage of 30 volts), the depletion region extends laterally and vertically into the semiconductor substrate 120 about 2.75 μm from the drain 1 14. Accordingly, in that case, the field oxide region 370 must have a width of at least 5.5 μm. So the distance between the drains 314 of the adjacent transistors 310 is necessarily greater than 5.5 μm.

However, the use of a single bulk NMOS (or PMOS) transistor as the pixel transfer switch in an LCD device has certain limitations and drawbacks.

First, as noted above, because of the requirement that the field oxide region have a sufficient width to isolate the space charge regions of the adjacent transistors, transistor fabrication densities within the semiconductor substrate are limited. Accordingly, pixel device density is also relatively low. Second, using only one type of MOS transistor as the transfer switch forces the gate voltage to be at values larger than the maximum drain/source maximum values. If: VCOL_M_AX represents the maximum voltage (~15V) applied to the source; Vb_g_MAX represents the back gate bias voltage of a bulk silicon MOS technology (~5.5V); and VDDD represents the (maximum) voltage applied to the gate of the transistor, then:

1 ) VDDD = V_COL_MAX + V_bg__MAX = V_COL_MAX + 5.5V ~ 20.5V

So it can be seen that the switching transistors require a relatively high maximum voltage rating.

Accordingly, it would be desirable to provide a liquid crystal display device with increases pixel density. It would also be desirable to provide a liquid crystal display device capable of employing switching transistors having a lower maximum voltage rating.. In one aspect of the invention, a liquid crystal display device comprises: a transparent substrate having a transparent first electrode disposed thereon; a semiconductor substrate including a plurality of second electrodes disposed thereon confronting the first electrode, and defining a plurality of pixel cells; liquid crystal material disposed between the first and second electrodes in each of the pixel cells; a plurality of CMOS transistor pairs, each CMOS transistor pair being connected to a corresponding one of the second electrodes and each comprising first and second MOS transistors, each transistor having a channel region in the semiconductor substrate; at least one field oxide region on the semiconductor substrate extending between and separating the first MOS transistor of a first one of the CMOS transistor pairs from the first MOS transistor of a second one of the CMOS transistor pairs; a trench extending from the field oxide region down to a depth greater than a depth of space charge region of the first MOS transistors; and a dielectric material disposed in the trench.

Beneficially, the trench surrounds and isolates each of the first MOS transistors In another aspect of the invention, a liquid crystal display device comprises: a plurality of complementary row line pairs extending in a first direction; a plurality of column lines extending in a second direction; and a plurality of pixel cells disposed at intersections of the row and column lines, each said pixel cell comprising: a pixel capacitor; an NMOS transistor having a first terminal connected to a first one of the column lines, a second terminal connected to the pixel capacitor, and a control terminal connected to a first row line of a first one of the complementary row line pairs; and a PMOS transistor having a first terminal connected to the first column line, a second terminal connected to the pixel capacitor, and a control terminal connected to a second row line of the first complementary row line pair.

FlG. 1 shows a partial schematic diagram of an LCD device including a plurality of liquid crystal (LC) pixel cells;

FlG. 2 shows a cross-sectional view of a pixel of a reflective LCOS device; FIG. 3 shows a cross-sectional view of a portion of a pixel substrate;

FIG. 4 shows a partial schematic diagram of an LCD device including a plurality of liquid crystal (LC) pixel cells having CMOS transfer switches;

FIG. 5 shows a cross-sectional view of a portion of a pixel substrate having CMOS transfer switches; FIG. 6 shows a top view of a portion (four lOμm x lOμm pixels) of a pixel substrate of an LCD device;

FIG. 7 shows a top view of a portion (four lOμm x lOμm pixels) of a pixel substrate of an LCD device having CMOS transfer switches.

FIG. 4 shows a partial schematic diagram of an LCD device 40 including a plurality of liquid crystal (LC) pixel cells 405. The device 40 includes a plurality of complementary row (gate) line pairs 480/485, a plurality of column lines 190, and a plurality of (LC) pixel cells 405, including a counter electrode 115. Each LC pixel cell 405 comprises a CMOS transfer switch 428, a pixel capacitor 121, a pixel electrode 125, and an LC material layer 130 disposed between the pixel electrode 125 and the counter electrode 1 15.

Beneficially, the LCD device 40 is a reflective liquid crystal on silicon (LCOS) device, as described above.

Beneficially, the LCD device ^'40 employs a CMOS transistor pair (one NMOS transistor 510 and one PMOS transistor 51 1 ) for the transfer switch 428.

Each CMOS transistor pair includes: an NMOS transistor having a first terminal (e.g., a drain) connected to one of the column lines 190, a second terminal (e.g., source) connected to the pixel capacitor 121 and the pixel electrode 125, and a control terminal (e.g., gate) connected to a first row line 480 of a first one of the complementary row line pairs; and a PMOS transistor having a first terminal (e.g., a drain) connected to the first column line 190, a second terminal (e.g., source) connected to the pixel capacitor 121 and the pixel electrode 125, and a control terminal connected to a second row line 485 of the first complementary row line pair.

With the CMOS transfer gate 428, if VCOL_M_AX represents the maximum voltage (~15V) applied to the source; V_bg M_AX represents the back gate bias voltage of a CMOS device (~0V); and VDDD represents the (maximum) voltage applied to the gate of the transistor, then:

1 ) V_DDD = VcOL_MAX + Vbg MAX ~ V_COL_MAX + OV ~ 15 V

So it can be seen that from the "voltage rating" perspective, the CMOS transfer gate 428 is preferable to the NMOS transfer gate 128 of FIG. 1. However, typical silicon bulk CMOS medium voltage transistor structures, such as the arrangement shown in FIG. 3, could not lead to a space-efficient implementation of a CMOS transfer gate within the pixel. Accordingly, desired pixel densities would not be possible with such silicon bulk CMOS medium voltage transistors such as those shown in FIG. 3. Accordingly, FIG. 5 shows a cross-sectional view of a portion of a pixel substrate

500 for an LCD device 40 that has an increased pixel density. The pixel substrate 500 includes two adjacent N-channel metal oxide semiconductor (NMOS) transistors 510 having channel regions 515 formed in adjacent P-well regions 505 of an N-type semiconductor substrate 520. Each of the transistors 510 comprises a source 512, a drain 514, and a gate electrode 516 extending between the source 512 and drain 514 and disposed on an oxide layer 518 on the semiconductor substrate 520. The transistors 528 are separated and isolated from each other by a deep trench 530 in the semiconductor substrate 520. A field oxide region 570, typically formed by local oxidation of silicon (LOCOS) and therefore also sometimes referred to as a LOCOS oxide film 570, is on the top portion of the trench 530.

Beneficially, each of these NMOS transistors 510 is associated with and connected to a corresponding p-channel MOS device 51 1 (see FIG. 5). Beneficially, the transistors 510 are "medium voltage transistors," which as used herein refers to transistors which are designed to operate over voltage ranges from ±3.5 V to ±20V for dual-supply operation, and from +7V to +40V for single-supply operation. Beneficially, the trench 530 is filled with a dielectric material, such as a thermal oxide (e.g., Siθ₂) for surface state control. Even more beneficially, the trench is filled with a thermal oxide, Tetraethoxysilane (TEOS) on the thermal oxide, and a lightly-doped polysilicon material in the central core of the trench.

The trench 530 separates and isolates the NMOS transistors 510 from each other. Namely, the trench 530 prevents the depletion regions of the transistors 510 from "touching" each other. Beneficially, the trench 530 surrounds and isolates each of the wells 505 and/or the NMOS transistors 510.

Beneficially, the trench 530 extends down from the field oxide region 570 into the semiconductor substrate 520 to a depth that is greater than a depth of both of the depletion regions of the transistors 510. For a medium voltage NMOS transistor 510 with a maximum operating voltage range of 15 volts (and a breakdown voltage of 30 volts), the depletion region extends vertically about 2.75 μm from the drain 214 into the semiconductor substrate 520. Accordingly, in that case, beneficially the trench 530 has a depth from the top of the semiconductor substrate 520 that is about 2.75 μm or greater. Even more beneficially, the bottom of the trench 530 extends down below the bottoms of the N-well regions 505 into the doped semiconductor substrate 420.

On the other hand, by virtue of the trench 530, the width of the field oxide region 570 can be reduced compared to the field oxide region 370 of the pixel substrate 100 of FIG. 3 which does not have the trench 530. Therefore, the distance between the adjacent transistors 510 of FIG. 5 can also be reduced compared to the distance between the adjacent transistors 310 of FIG. 3. For example, in the case where the medium voltage transistors 310 and 510 are 15 volt devices, whereas the minimum width of the field oxide layer 370 of FIG. 3 must be about 5.5 μm, the width of the field oxide layer 570 of FIG. 5 can be less than 2.0 μm, indeed in this case only about 1.4 μm.

Although FIG. 5 only shows the two NMOS transistors 510, deep trench isolation is also employed for the PMOS transistors 51 1 of the CMOS transistor pair. Also, although FIG. 5 shows the two NMOS transistors formed in two P-WeIIs of an N-type semiconductor substrate, the conductivity types of the wells, substrate, etc. can be changed or reversed. For example, the device could include two NMOS transistors formed in two P-wells in an N-rype semiconductor substrate

Accordingly, all other things being equal, the pixel substrate 500 can have a much greater transistor density than the pixel substrate 100 of FIGs. 1 and 3. Indeed, the transistor density is sufficiently increased such that a pixel 405 including the CMOS switching gate 428 can occupy less surface area than the pixel 105 of FIG. 1 having the NMOS transistor 310 as the switching gate 128. To that end, FIG. 6 shows a top view of a portion (four l Oμm x lOμm pixels) of the pixel substrate 100 of the LCD device 10 of FIG. 1 having the NMOS transistor 310 as the transfer switch 128, while FIG. 7 shows a top view of a portion (four lOμm x lOμm pixels) of the pixel substrate 500 of the LCD device 40 of FIG. 4 having the CMOS transfer switch 428. The four l Oμm x l Oμm pixels of FlG. 7 with the CMOS transfer switch 428 occupy less area than the four l Oμm x lOμm pixels of FIG. 6 with the NMOS transfer switch 128. Furthermore, the area available for the pixel capacitance is greater in FIG. 7 than in FIG. 6. Finally, as noted above, the CMOS transistors 510, 51 1 can operate at a lower voltage than the NMOS transistor 310.

While embodiments are disclosed herein, many variations are possible which remain within the concept and scope of the invention. Such variations would become clear to one of ordinary skill in the art after inspection of the specification, drawings and claims herein. The invention therefore is not to be restricted except within the spirit and scope of the appended claims.

Claims

CLAIMS:

1. A liquid crystal display device, comprising: a transparent substrate (1 10) having a transparent first electrode (1 15) disposed thereon; a semiconductor substrate (520) including a plurality of second electrodes (125) disposed thereon confronting the first electrode ( 1 15), and defining a plurality of pixel cells (405); liquid crystal material (130) disposed between the first and second electrodes (1 15, 125) in each of the pixel cells (405); a plurality of CMOS transistor pairs (428), each CMOS transistor pair (428) being connected to a corresponding one of the second electrodes (125) and each comprising first and second MOS transistors (510, 51 1 ), each transistor (510, 51 1 ) having a channel region (515) in the semiconductor substrate (520); at least one field oxide region (570) on the semiconductor substrate (520) extending between and separating the first MOS transistor (510) of a first one of the CMOS transistor pairs (528) from the first MOS transistor (510) of a second one of the CMOS transistor pairs (528); a trench (530) extending from the field oxide region (570) down to a depth greater than a depth of space charge region of the first MOS transistors (510); and a dielectric material disposed in the trench (530).

2. The device of claim 1 , wherein the first and second MOS transistors (510) are medium voltage transistors.

3. The device of claim 1 , wherein the second electrodes ( 125) are reflective electrodes, and further comprising a light shield (123) disposed between the CMOS transistor pairs (528) and the transparent substrate (1 10).

4. The device of claim 1 , wherein the dielectric material is a thermal oxide.

5. The device of claim 4, further comprising a Tetraethoxysilane (TEOS) material and a doped polysilicon material in the trench (530).

6. The device of claim 1, the first MOS transistors (510) each operate about 15 volts, and wherein a width of the field oxidation region is less than 5 μm.

7. The device of claim 6, wherein a width of the field oxide region (570) is less than 2 μm.

8. The device of claim 1 , further comprising first and second well regions (505) formed in the semiconductor substrate (520), wherein the semiconductor substrate (520) has a first conductivity type, the first and second well regions (505) have a second conductivity type, the first MOS transistor (510) of the first CMOS transistor pair (528) is formed in the first well region (505), and the first MOS transistor (510) of the second CMOS transistor pair (528) is formed in the second well region (505).

9. The device of claim 8, wherein the trench (530) surrounds and isolates each of the first and second well regions (505).

10. The device of claim 1, wherein the trench (530) surrounds and isolates each of the first MOS transistors (510).

1 1. The device of claim 1 , wherein the first and second MOS transistors (510, 51 1) of the first CMOS transistor pair (528) each have first and second terminals and a gate, said device further comprising: a row line (480) connected to the gate of a first MOS transistor (510); a complementary row line (485) connected to the gate of the second MOS transistor (51 1 ); and a column line ( 190) connected to the first terminals of the first and second MOS transistors (510, 51 1), wherein the second terminals of the first and second MOS transistors (510, 51 1 ) are each connected to the corresponding second electrode (125).

12. A liquid crystal display device, comprising: a plurality of complementary row line pairs (480, 485) extending in a first direction; a plurality of column lines (190) extending in a second direction; and a plurality of pixel cells (405) disposed at intersections of the row and column lines (480, 485, 490), each said pixel cell (405) comprising: a pixel capacitor (121 ); an NMOS transistor (510) having a first terminal connected to a first one of the column lines (190), a second terminal connected to the pixel capacitor ( 121 ), and a control terminal connected to a first row line (180) of a first one of the complementary row line pairs (480, 485); and a PMOS transistor (51 1) having a first terminal connected to the first column line (190), a second terminal connected to the pixel capacitor (121), and a control terminal connected to a second row line (485) of the first complementary row line pair (480, 485).

13. The device of claim 12, wherein the NMOS and PMOS transistors (510, 51 1 ) are medium voltage transistors.

14. The device of claim 12, wherein the device includes a semiconductor substrate (520), and further comprising: at least one first field oxide region (570) on the semiconductor substrate (520) extending between and separating the NMOS transistor (510) of a first pixel cell (405) from the NMOS transistor (510) of a second pixel cell (405); a trench (530) extending from the first field oxide region (570) down to a depth greater than a depth of space charge region of the NMOS transistors (510); and a dielectric material disposed in the trench (530).

15. The device of claim 14, wherein the dielectric material is a thermal oxide.

16. The device of claim 15, further comprising a Tetraethoxysilane (TEOS) material and a doped polysilicon material in the trench (530).

17. The device of claim 14, wherein NMOS transistors (510) each operate at about 15 volts, and wherein a width of the first field oxidation region is less than 5 μm.

18. The device of claim 14, further comprising: at least one second field oxide region (570) on the semiconductor substrate (520) extending between and separating the PMOS transistor (51 1) of a third pixel cell (405) from the PMOS transistor (51 1) of a fourth pixel cell (405); a second trench (530) extending from the second field oxide region (570) down to a depth greater than a depth of space charge region of the PMOS transistors (51 1); and a dielectric material disposed in the second trench (530).

19. The device of claim 12, further comprising: at least one field oxide region (530) on the semiconductor substrate (520) extending between and separating the PMOS transistor (51 1) of a first pixel cell (405) from the PMOS transistor (51 1) of a second pixel cell (405); a trench (530) extending from the field oxide region (570) down to a depth greater than a depth of space charge region of the PMOS transistors (51 1); and a dielectric material disposed in the trench (530).

20. The device of claim 12, wherein each pixel cell (405) further comprises a reflective pixel electrode (125) connected to the pixel capacitor (121), the NMOS transistor (510), and the PMOS transistor (51 1).