WO2006017339A3 - Programmable processor system with two types of sub-processors to execute multimedia applications - Google Patents

Programmable processor system with two types of sub-processors to execute multimedia applications Download PDF

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Publication number
WO2006017339A3
WO2006017339A3 PCT/US2005/024867 US2005024867W WO2006017339A3 WO 2006017339 A3 WO2006017339 A3 WO 2006017339A3 US 2005024867 W US2005024867 W US 2005024867W WO 2006017339 A3 WO2006017339 A3 WO 2006017339A3
Authority
WO
WIPO (PCT)
Prior art keywords
processor
sub
type sub
processors
types
Prior art date
Application number
PCT/US2005/024867
Other languages
French (fr)
Other versions
WO2006017339A2 (en
Inventor
Ramchandran Amit
Reid Hauser John Jr
Original Assignee
3Plus1 Technology Inc
Ramchandran Amit
Reid Hauser John Jr
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 3Plus1 Technology Inc, Ramchandran Amit, Reid Hauser John Jr filed Critical 3Plus1 Technology Inc
Priority to CA002572954A priority Critical patent/CA2572954A1/en
Priority to EP05771043A priority patent/EP1779256A4/en
Priority to JP2007521614A priority patent/JP2008507039A/en
Publication of WO2006017339A2 publication Critical patent/WO2006017339A2/en
Publication of WO2006017339A3 publication Critical patent/WO2006017339A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7864—Architectures of general purpose stored program computers comprising a single central processing unit with memory on more than one IC chip
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units

Abstract

One embodiment of the present invention includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor (74, 76) capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor (78, 80) capable of processing N bits in parallel, N being an integer value wherein and smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type-sub­processor and shared memory coupled to the at least one W-type sub-processor and the at least one N-type sub-processor (312), wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.
PCT/US2005/024867 2004-07-13 2005-07-12 Programmable processor system with two types of sub-processors to execute multimedia applications WO2006017339A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CA002572954A CA2572954A1 (en) 2004-07-13 2005-07-12 Programmable processor system with two types of sub-processors to execute multimedia applications
EP05771043A EP1779256A4 (en) 2004-07-13 2005-07-12 Programmable processor architecture
JP2007521614A JP2008507039A (en) 2004-07-13 2005-07-12 Programmable processor architecture

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US58769104P 2004-07-13 2004-07-13
US60/587,691 2004-07-13
US59841704P 2004-08-02 2004-08-02
US60/598,417 2004-08-02

Publications (2)

Publication Number Publication Date
WO2006017339A2 WO2006017339A2 (en) 2006-02-16
WO2006017339A3 true WO2006017339A3 (en) 2006-04-06

Family

ID=35839807

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/024867 WO2006017339A2 (en) 2004-07-13 2005-07-12 Programmable processor system with two types of sub-processors to execute multimedia applications

Country Status (5)

Country Link
EP (1) EP1779256A4 (en)
JP (1) JP2008507039A (en)
KR (1) KR20070055487A (en)
CA (1) CA2572954A1 (en)
WO (1) WO2006017339A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7856246B2 (en) 2007-03-21 2010-12-21 Nokia Corporation Multi-cell data processor
GB2474901B (en) * 2009-10-30 2015-01-07 Advanced Risc Mach Ltd Apparatus and method for performing multiply-accumulate operations
CN109284131B (en) * 2013-05-24 2023-05-30 相干逻辑公司 Memory-network processor with programmable optimization
JP6102528B2 (en) 2013-06-03 2017-03-29 富士通株式会社 Signal processing apparatus and signal processing method
KR102235803B1 (en) * 2017-03-31 2021-04-06 삼성전자주식회사 Semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5878085A (en) * 1997-08-15 1999-03-02 Sicom, Inc. Trellis coded modulation communications using pilot bits to resolve phase ambiguities
US5909559A (en) * 1997-04-04 1999-06-01 Texas Instruments Incorporated Bus bridge device including data bus of first width for a first processor, memory controller, arbiter circuit and second processor having a different second data width
US6166748A (en) * 1995-11-22 2000-12-26 Nintendo Co., Ltd. Interface for a high performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing
US20040078411A1 (en) * 2002-10-22 2004-04-22 Joshua Porten Galois field arithmetic unit for use within a processor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9509989D0 (en) * 1995-05-17 1995-07-12 Sgs Thomson Microelectronics Manipulation of data
AU9026498A (en) * 1997-08-22 1999-03-16 Jens Korsgaard Fluid swivel for oil production vessels and tanker vessels
JP2991694B1 (en) * 1998-06-12 1999-12-20 日本放送協会 Digital transmitter and receiver
US6643332B1 (en) * 1999-07-09 2003-11-04 Lsi Logic Corporation Method and apparatus for multi-level coding of digital signals
US6539467B1 (en) * 1999-11-15 2003-03-25 Texas Instruments Incorporated Microprocessor with non-aligned memory access

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6166748A (en) * 1995-11-22 2000-12-26 Nintendo Co., Ltd. Interface for a high performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing
US5909559A (en) * 1997-04-04 1999-06-01 Texas Instruments Incorporated Bus bridge device including data bus of first width for a first processor, memory controller, arbiter circuit and second processor having a different second data width
US5878085A (en) * 1997-08-15 1999-03-02 Sicom, Inc. Trellis coded modulation communications using pilot bits to resolve phase ambiguities
US20040078411A1 (en) * 2002-10-22 2004-04-22 Joshua Porten Galois field arithmetic unit for use within a processor

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
HEINRICH J.: "MIPS R4000 Microprocessor User's Manual.", 1994, pages: 1 - 21, XP002928551 *
See also references of EP1779256A4 *

Also Published As

Publication number Publication date
CA2572954A1 (en) 2006-02-16
JP2008507039A (en) 2008-03-06
EP1779256A4 (en) 2007-11-28
WO2006017339A2 (en) 2006-02-16
KR20070055487A (en) 2007-05-30
EP1779256A2 (en) 2007-05-02

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