WO2006008746A2

WO2006008746A2 - Integrated active pixel sensor and method of its fabrication

Info

Publication number: WO2006008746A2
Application number: PCT/IL2005/000779
Authority: WO
Inventors: Amir Sa'ar; Joseph Shappir
Original assignee: Yissum Research Development Company Of The Hebrew University Of Jerusalem
Priority date: 2004-07-22
Filing date: 2005-07-21
Publication date: 2006-01-26
Also published as: WO2006008746A3

Abstract

An active pixel sensor and a method of its manufacture are provided. The sensor comprises a silicon substrate patterned to form a photodetctor arrangement therein, and a silicon-on-insulator (SOI) layer structure on the substrate, the silicon layer of the SOI layer structure carrying an electronics circuit vertically integrated with said photodetector arrangement for processing output thereof.

Description

INTEGRATED ACTIVE PIXEL SENSOR AND METHOD OF ITS FABRICATION

FIELD OF THE INVENTION

This invention is generally in the field of integrated electronic devices and relates to complementary metal-oxide-semiconductor (CMOS) image sensors.

BACKGROUND OF THE INVENTION The CMOS imager technology presents a new generation of imagers with advance features that make them an alternative technology to charge-coupled device (CCD) based imagers. CMOS based active pixel sensors (APS) capable of achieving nearly the same performance as CCDs in terms of quantum efficiency and noise have been developed. One of the advantages of using CMOS technology instead of CCDs is associated with the fact that CCDs typically require high power for operation and are not well suited for integration of additional signal and image processing operations. For comparison, on-chip CMOS sensors consume two orders of magnitude less power and are well suited for a further integration with on-chip, image-processing operations. In addition, CMOS sensors can be read out randomly (that is, pixels can be accessed in any order) and only the interesting parts of the picture may be read out. Finally, CMOS sensors are realized by the leading microelectronics processing technology with outstanding advantages in speed, power reliability, and cost. However, CMOS imagers often require the use of "on pixel" electronics to perform smart signal processing though negatively affecting such parameters as filling factor, pixel area, etc. For example, the dynamic range, defined as a ratio in brightness between the darkest and the brightest parts of the image, generally achieves smaller values in CMOS technology than in CCD technology, but could be increased with the help of "on pixel" smart signal processing possible with the CMOS technology. The "on pixel" smart signal processing may for example include incorporation of electronic filters that allows for achieving real-time automatic scaling of each pixel, and/or the use of median filters (MED), e.g., to remove the so-called "salt and pepper" noise. Typically, MED are digitally calculated off-chip using special digital signal processing. On-pixel median calculations can provide an improvement in system complexity, power mass and cost, and may be performed with real time throughput.

Some imaging applications require higher radiation hardness than that of bulk CMOS. In the case of CMOS very large scale integration (VLSI) technology, higher radiation hardness may be achieved by using silicon-on- insulator (SOI) substrates instead of bulk silicon wafers. Generally, there are two known approaches in the field of SOI CMOS VLSI consisting of using thick film or thin film SOI. In the first case (thick SOI film), the SOI layer thickness is in the range of few microns and the same circuit design and layout as in bulk silicon can be utilized. This approach is therefore easy to implement without heavy investments in process development and circuit design. On the other hand, the most important benefit of this approach is in improved radiation hardness with no additional improvements in speed, latch up immunity, etc.

In the case of thin SOI layer, the source/drain n⁺ and p⁺ junctions can penetrate to the bottom of the SOI layer. As a result, the effective junction area is significantly smaller. The resulting major reduction in junction capacitance results in a much faster circuit. Different implementations of the CMOS image sensors have been developed. One of the most promising of them, the SOI active pixel sensor with the photosites implemented in the substrate, was disclosed in International Publication WO 00/21280. There, active pixel sensors for a high quality imager are fabricated using a SOI process by integrating photodetectors on the SOI substrate and forming pixel read-out transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistors in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnection among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read via the transistors formed on the silicon islands.

The placing of photosites into the SOI substrate is advantageous over conventional bulk CMOS sensors in a number of factors. In particular, high collection and absorption efficiencies, large dynamic range, and low noise can be achieved for the pixels. The pixels can exhibit very little cross-talk and can be formed closely to one another. Additionally, the pixels can exhibit radiation hardness. Also, gains in power consumption and speed can be achieved due to common advantages of the SOI electronics over bulk electronics.

SUMMARY OF THE INVENTION

There is a need in the art to improve the performance (in particular the fill factor) of a CMOS imager, by providing a novel active pixel sensor, in which photodetector and CMOS electronics are integrated vertically thus making the entire pixel area available for smart signal processing, and which can be implemented in a single wafer structure.

It should be noted that the term "single wafer structure" used herein signifies that the wafer structure is formed on the single substrate without any hybridization between two separate wafers to bond photodetector and CMOS electronics carrying substrates.

According to one broad aspect of the invention, there is provided an active pixel sensor comprising: a silicon substrate patterned to form a photodetector arrangement therein; a silicon-on-insulator (SOI) layer structure on said substrate, the silicon layer of said SOI layer structure carrying an electronics circuit vertically integrated with said photodetector arrangement for processing output thereof.

As indicated above, preferably, the sensor includes a single wafer structure formed by the substrate and the SOI.

The sensor further includes an upper electrically insulating layer on top of the SOI layer structure.

The photodetector arrangement is in the form of an array of spaced-apart doped regions of the silicon substrate, defining the array of photosensitive regions, spaced by electrically insulating regions.

The electronic circuit includes transistors and preferably also capacitors.

The electronic circuit includes a plurality of differently doped regions in the silicon layer of the SOI layer structure and lithography patterned electrically conductive regions in the upper electrically insulating layer on top of the SOI layer structure, defining a transistor arrangement (active regions of transistors).

The SOI layer structure and the upper layer are patterned to form vertical interconnects between the photosensitive regions and the respective elements of the electronic circuit. The capacitor arrangement of the electronic circuit is defined by lithography patterned electrically conductive regions in the upper electrically insulating layer on top of the SOI layer structure. The silicon substrate may have a thickness allowing illumination therethrough of the photodetector arrangement. The thickness may for example be of about 20 micrometers.

The substrate thickness may be selected to enable diffusion of current carriers, generated in the substrate in response to the illumination, to the photodetector arrangement.

The sensor may also include a lowermost electrically insulating layer carrying the substrate thereon. This lowermost electrically insulating layer may be transparent for certain wavelength range allowing illumination therethrough (and through the thin substrate) of the photodetector arrangement.

The sensor of the invention may be configured by patterning a single wafer structure, which is formed by the unpatterned silicon substrate and the SOI layer structure on said unpatterned substrate. This single wafer structure may be formed by bonding between first and second wafer structures, where the first wafer structure is formed by an SOI carried on top of a first silicon substrate and covered by a first electrically insulating layer, and the second wafer structure is formed by a second silicon substrate covered by a second electrically insulating layer. The first and second wafers are bonded at the first and second electrically insulating layers, thereby forming the SOI layer structure including the second silicon substrate on the electrically insulating layer resulting from the boding.

According to another broad aspect of the invention, there is provided an active pixel sensor comprising: a silicon substrate patterned to define a photodetector arrangement formed by an array of doped regions defining the array of photosensitive elements spaced by electrically insulating regions; a silicon-on-insulator (SOI) layer structure on said substrate, the silicon layer of said SOI layer structure carrying an electronics circuit configured such that each element of the electronic circuit is vertically integrated with the respective photosensitive element for processing output thereof; an upper electrically insulating layer patterned with horizontally oriented electrically conductive regions defining gate electrodes of the transistors; and vertical interconnects between the photosensitive regions and the respective elements of the electronic circuit.

According to yet another broad aspect of the invention, there is provided a method of fabricating an active pixel sensor with an electronics circuit vertically integrated with a photodetector arrangement, the method comprising: providing a silicon-on-insulator (SOI) layer structure on a p-type silicon substrate; processing said SOI layer structure by applying thereto or therethrough an ion implantation or material diffusion, and by applying material removal processes, to thereby define elements of said electronics circuit and elements of said photodetector arrangement vertically integrated with each other in a single wafer structure.

According to some embodiments of the invention, the method consists of the following: providing a wafer structure formed by the SOI layer structure on the ρ-type silicon substrate; applying said processing to the substrate through the SOI layer structure to define a photodetector arrangement layer therein; forming an upper insulator layer by oxidizing the silicon layer of said SOI; applying patterning procedures to the upper insulator layer, and the silicon layer and the buried oxide layer of said SOI layer structure, to form elements of the electronic circuit vertically aligned with the photodetector arrangement; patterning the upper layer, the SOI layer structure and the substrate to define an array of photodiodes of the photodetector arrangement such that each photodiode is vertically aligned with its corresponding element of the electronic circuit.

The processing to define the photodetector layer includes applying ion implantation to the substrate through the SOI layer structure. The patterning procedures include patterning the silicon layer of the SOI layer structure by applying ion implantation thereto to form transistor elements, and patterning the SOI layer structure and the upper layer by the material removal to form transistor and capacitor element, and interconnects between the electronics and the photodetector arrangement.

The method may further include at least partial removal of the substrate layer to enable backside illumination therethrough of the photodetector arrangement. Also, a lower insulator layer may be formed interfacing the substrate layer. This lower insulator layer is transparent to the illumination.

According to some other embodiments of the invention, the method consists of the following: providing first and second wafer structures, the first wafer structure being formed by an SOI carried on top of a first silicon substrate and covered by a first electrically insulating layer, the silicon layer of the SOI presenting the photodetector arrangement layer, and the second wafer structure being formed by a second silicon substrate covered by a second electrically insulating layer, bonding the first and second wafer structures at the first and second electrically insulating layers, thereby forming said SOI layer structure including the second silicon substrate on the electrically insulating layer resulting from said boding; applying the material removal to partially remove the second silicon substrate; oxidizing an upper surface of the second silicon substrate to thereby enable formation of an upper electrically insulating layer; patterning said SOI layer structure, to form elements of the electronic circuit vertically aligned with the photodetector arrangement; patterning the upper electrically insulating layer, the SOI layer structure and the first substrate below the SOI layer structure to define an array of photodiodes of the photodetector arrangement such that each photodiode is vertically aligned with its corresponding element of the electronic circuit.

In this embodiment, the first substrate layer may be then at least partially removed to enable backside illumination of the photodetector arrangement.

BRIEF DESCRIPTION OF THE DRAWINGS In order to understand the invention and to see how it may be carried out in practice, preferred embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

Fig. IA is a schematic illustration of an example of an integrated structure of an active pixel sensor device of the present invention; Fig. IB illustrates an electric scheme of the device of Fig. IA;

Fig. 2 illustrates a test photodiode structure obtained through ion implantation;

Figs. 3 A to 3H show a method of fabrication of the structure of Fig. 2; Fig. 4 illustrates a test photodiode structure obtained through material diffusion;

Figs. 5 A and 5B show the measurement results for the structures of Figs. 2 and 4;

Fig. 6 is a schematic illustration of another example of an integrated structure of an active pixel sensor device of the present invention; and

Figs. 7A to 7D exemplify a method of fabricating the structure of Fig. 6.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Referring to Fig. IA, there is partially illustrated example of an active pixel sensor, generally designated 10, configured according to the invention. The sensor device 10 includes a silicon p-type substrate 12 patterned to form a photodetector arrangement 14 therein; and a silicon-on-insulator (SOI) layer structure 16 (silicon layer 16A on a buried oxide layer 16B) on the substrate 12.

The silicon layer 16A is processed to form an SOI CMOS electronics circuit, generally at 18, vertically integrated with the photodetector arrangement 14 for processing output thereof.

In the present example, of Fig. IA, the substrate 12 layer thickness is considered to be too large to enable the backside illumination. Accordingly, the photodetector arrangement (its pixel regions) is illuminated from the top electronics side. It should be noted that it is possible to thin down the substrate to the range of about 20 micrometers to enable efficient back side illumination.

The sensor device 10 is prepared as a single wafer structure formed by the substrate 12 and the SOI 16. The device 10 also includes an upper electrically insulating layer (e.g., silicon oxide) 20 on top of the SOI 16. The insulator layer 20 is prepared as two-layer structure: layer 2OA serving as the gate insulator and a capacitor spacer (e.g., obtained by oxidation of silicon layer 16A); and top layer 2OB.

The photodetector arrangement 14 is in the form of an array of spaced- apart doped regions of the silicon substrate, defining the array of photosensitive regions, spaced by electrically insulating regions 22. In Fig. IA, one such region (image pixel) 14A is shown in full, and two adjacent pixels 14B and 14C are partially shown. This region 14 is formed as n+Si layer doped in the p-type Si substrate 12. Regions 14A-14C are spaced from each other by electrically insulating regions (e.g., silicon oxide) 22. To this end, the SOI structure 16 and the substrate 12 (including its π+-doped layer 14) are appropriately patterned.

The electronic circuit 18 (its transistor part) is formed as a plurality of differently doped regions 24A and 24B in the silicon layer 16A so as to define an active area of the transistor. The top layer 20 and SOI structure 16 are patterned to form vertical interconnects, generally at 26, between the pixel region 14A and the respective element of the electronic circuit 18. Also, the interconnect 26 preferably has a horizontally elongated portion 26A above the silicon layer 16A being spaced therefrom by the oxide layer material 2OA to thereby form together a capacitor which serves to store the photo generated electronic charge. The upper layer 20 is then further patterned to enable metal contacts 28A and 28B to the silicon layer 16 A.

Fig. IB shows in a self-explanatory manner the electrical scheme of the device 10. Here, contact 28A is grounded.

The so-obtained structure consists of two main parts: (1) buried n⁺-p Si photodiode (formed by layers 12 and 14) below the BOX layer 16B, the photodiode being utilized for sensing the light and generating the photo-current; and (2) top silicon (SOI) electronics 18 that consists of integration capacitor (for accumulating the charges) and on-pixel smart electronics (for signal processing). In Fig. IA, only one CMOS transistor is shown for the sake of simplicity. Both parts (photodiode and electronics) are vertically integrated. Thus, the present invention provides the active pixel sensor in which the photodetector arrangement 14 and the CMOS electronics 18 are integrated vertically thus making the entire pixel area 14A available for smart signal processing. This sensor is advantageously implemented in the single wafer structure thus preventing the need to bond two silicon dies together with tens of thousands electrical connections.

The starting material for the device fabrication is an SOI wafer formed by the/Mype substrate layer 12 (before doping, i.e., before forming layer 14, as well as before defining the pixel isolating oxide 22), buried oxide (BOX) 16B and silicon 16 A on top thereof. Regions 22 are defined by lithography followed by Reactive Ion Etching (RIE) of the SOI layer structure 16 and substrate 12 (including its layer 14), and filled with silicon oxide, thus forming insulating spacers between adjacent pixels. As indicated above, the oxide layer 2OA is fabricated by oxidation of a part of top silicon 16A (e.g., thermal oxidation of IOOA of the top Si layer 16A). Doping (n+ doping) is applied to the layer 14 (thus forming p-n transition layer 12-14 for photodiodes 12-14B, 12-14A, 12- 14C), and n+ and ^-doping is applied to layer 16A (thus forming the transistor active regions 24A and 24B). Regions 22 may be defined before the creation of regions 24A and 24B or after that. The formation of layer 14 can use an ion (e.g. phosphor) implantation technique. This may for example be a two-stage implantation, aimed at reducing the damage to the top SOI layer 16A and allowing better damage repair by thermal annealing.

Further fabrication steps relate to the^r definition of the transistors and other elements of the electronic circuit, and are performed by standard SOI CMOS process. An additional lithographic step is used either prior to oxidation or later on, to define the interconnect 26 followed by the RIE etching applied to layers 16A and 16B. Then, polycrystalline silicon is deposited and patterned to form the vertical interconnect 26 as well as the top electrode of the storage capacitor 26A. Finally, metallic contacts 28A and 28B are fabricated by oxide etch of the respective regions of the top layer 20, metal deposition (e.g., Al), and excessive metal etch.

The inventor has prepared test structures of two types for of photodiodes (photodetector arrangement), shown in Figs. 2 and 4, respectively: three test structures of the type 100 of Fig. 2 distinguishing from each other by the P- implantation parameters (showing that ion implantation through the SOI structure can effectively be utilized to fabricate the photodetector arrangement) and one test structure type 200 of Fig. 4 fabricated using P diffusion rather than implantation. The fabrication of the structure type 100 will now be described with reference to Figs. 3A-3H: The starting material for the device fabrication was an SOI wafer: a 14-22 Ω cmp-type SOI wafer with 2050A top Si layer 16A, 2000A buried oxide (BOX) layer 16B and a 625 micron thick substrate 12 (commercially available from SOITEC, fabricated by the Unibond process). As shown in Fig. 3A, the oxide layer 2OA is fabricated by oxidation of a part of top silicon 16A (e.g., thermal oxidation of IOOA of the top Si layer 16A). Then (Fig. 3B), n+ doping is applied to the layer 12, to form layer 14 by ion (e.g. phosphor) implantation technique. Here, three different parameter sets were used for fabrication of three samples of this type, namely, P-implantation range 4650 A and dose 3x10¹⁴Cm^"2; range 4650A and dose IxIO¹⁴Cm^"2; and for double implantation sample - range 4650A and dose IxIO¹⁴Cm^"2, and 1030A; dose 2xl0¹⁵cm ²,

In a further step (Fig. 3C), a material removal (patterning) is applied to a region of the SOI structure to define the electric contact to the n+-layer 14 of the photodiode (about 75 micron diameter). Then (Fig. 3D), polysilicon deposition and subsequent P diffusion is applied. The photodiode is defined by further patterning (Fig. 3E) to form a diode mesa structure using RIE (mesa diameter of 200 micron). Then, second oxidation and boron implantation are applied to form layer 2OB and define p+ regions 30 (Fig. 3F). Then, oxide etching followed by Al deposition is applied to form contacts 32 to enable measurement of the photodiode characteristics in the experimental samples (Figs. 3G and 3H). The resulting photodiode structure, after selective Al-layer removal, is shown in Fig. 2.

The structure 200 of Fig. 4 is obtained starting from the SOI wafer and carrying out P diffusion, after etching away the tqp silicon layer and the box layer.

The following Table and Figs. 5A-5B illustrate the measured photodiodes' characteristics. This includes I-V measurements in the dark (Fig. 5A) and under constant white light top illumination of 5 mW/cm² (Fig. 5B). The dark resistance of the diodes was calculated as well as the responsivity. Also, the breakdown voltage of diodes was measured. The area of all diodes is 3-10^"4 cm² (200 μm in diameter mesas). In Figs. 5A and 5B, four graphs Gi-G₄ are shown, corresponding to respectively, reference diffusion, deep implant 10¹⁴cm^"2, deep implant 3xl0¹⁴cm^"2, and double implant - deep implant 10¹⁴cm^'2 and shallow 2x10¹⁵. Table 1 summarized the measurement results.

Table 1

It is shown that for the diode with the lowest dose implantation the leakage current is lower than those with the high-dose implantation; the dark resistance is higher for this diode (low-dose) than those of the high-dose implantation. The responsivity of the low-dose diode is higher than that of the high-dose diodes. The best responsivity (0.7 AAV) was achieved for the reference diode that did not experience ion implantation. The measured responsivity is very close to reported values of commercial Si-diodes. It is thus clear that the ion implantation process might degrade the performances of the diodes. The larger the dose of the implantation the worse is the diode performances. The best performances were achieved for the reference diode that did not experience ion implantation. This effect is due to the larger damage to the silicon induced by the implanted ions. Hence, an improved process for the sensor manufacture would be that eliminating the ion implantation stage using modified SOI wafers.

In order to estimate of SOI imager performances, let us consider the expected performances of the diode fabricated with the lowest dose (IxIO¹⁴ cm²). The resistance measured for this diode, with diode area of ~3.1xlO^"4 cm² (200μm diam.) is 3xlO^πΩ. Hence, assuming a pixel area of lόxlO^"8 cm² (4x4 μm²), the expected resistance is R=6xlO¹⁴Ω.

Assuming operating backward voltage of, V=-3 Volt, a dark current is

z_D=V/R=5xl0^"15 Amp.

For an integration time t of 30 msec, the amount of dark charges would be Q_D=f_β-Z=1.5xl0^'16 C.

Therefore, the average number of electrons accumulated in the integration capacitor due to dark current is N_D =Qo/e = 10³.

This means that the electronic noise associated with fluctuations in the average number of electrons would be N_noise ≡

= 30 electrons. In order to estimate the dynamic range of the SOI diode, let us assume that only 1/4 of the pixel area (lμm²) is utilized for the integration capacitor and that the thickness of the capacitor oxide layer is about 5θA. Hence, the capacity of this capacitor is C=2xlO^"13 F. Therefore, for operation voltage of -3 V, the maximum number of electrons that can be accumulated is N_max=C-Y/e ≡ 5x10⁶ electrons.

These results mean that the dynamic range of the SOI-based imager of the present invention can be extended to 13 bits. These results could be further improved by processing techniques to further extend the dynamic range of the device.

The vertically integrated SOI imager structure could be improved by eliminating two restricting factors that limit the performances of the device. These include the following: (a) a need of using the backside illumination approach (backside illumination is necessary when the entire pixel area is to be used for electronics), thus requiring removal of the backside Si substrate at the end of the process (otherwise most of the visible light will be absorbed in the substrate); and

(b) elimination of a need for ion implantation of phosphorous to generate the n⁺ side of the diode, aimed at improving the photodiode performances;

Both problems can be solved by using a modified SOI wafer. Such a structure utilizing the backside illumination approach is exemplified in Fig. 6. An active pixel sensor 300 of Fig. 6 is generally similar to that of Fig. IA, except for the thickness of a substrate layer 112 (12 in Fig. IA), and presence of a newly introduced silicon oxide layer 50. Layer 112 is thinner than layer 12 so that to allow for a backside illumination to penetrate deep enough into the substrate to generate photocarriers within the diffusion distance from layer 14. Ideally, the thickness of layer 112 is chosen to maximize the photocurrent in photodiode 112- 14. Generally, there are two possible techniques to fabricate the sensor 300.

The first technique utilizes etching away the backside Si substrate (12 in Fig. IA) using standard Chemical Mechanical Planarization (CMP) and etching techniques, carried out at the end of the fabrication process as described above with reference to Fig. IA. It should be noted that the processed wafer can be bonded to another substrate (from top), before the substrate removal, for a mechanical support. The performances of the photodiode depend on the thickness of the residual Si substrate layer 112 that should be appropriately thin (e.g., about 20 micrometers) to avoid absorption of the light during backside illumination.

The second technique takes advantage of the SOI fabrication technology to form double buried oxide layers (BOX layers). The role of the second, bottom BOX layer 50 is for two important aspects: forming a natural stop-etch layer; and the backside of the thinned wafer will be terminated by thermal oxide that has extremely low surface recombination velocity, and hence much lower dark current. According to this approach, the same processing procedure as described above is used to define the vertically integrated CMOS imager (i.e., starting from an SOI and carrying out ion implantation/diffusion and material removal). Next, standard dry etching techniques are used to selectively etch the silicon layer but not the oxide layer (for example, ICP for deep trenches) to totally remove the backside substrate. This allows for the formation of high quality and flat interfaces, without surface defects and recombination. Such a structure shown in Fig. 6 is ideal for backside illumination.

The second problem associated with the ion implantation can be solved by making the n⁺ Si layer of the buried p-n photodiode as an integral part of the starting (modified) SOI wafer and by fabricating it by using either diffusion or epitaxy. As a result, there is no damage to the Si crystal during the fabrication process and the performances of the photodiode are improved by at least a factor of 5-10.

An example of a process of fabrication of a starting SOI wafer that obeys the above requirements will now be described with reference to Figs. 7A-7D. For the sake of simplicity, the process is presented here schematically.

Fig. 7A shows a structure profile 60 obtained as follows: A starting wafer of this process is the standard p-type SOI wafer structure 60 formed by a p-type Si layer 112 on oxide layer (BOX) 50. This SOI structure is located on top of a p- type substrate 62. The, phosphorous (P) diffusion of the p-type SOI wafer 112 is carried out to form the upper n⁺ Si layer 14 of the diode. Alternatively, this layer can epitaxially be grown during the fabrication of the SOI wafer using the standard ELTRAN process. Then, oxidation of a thin top layer 16B is performed.

In a separate process, the second wafer 70 (Fig. 7B) is prepared using a p- type Si substrate 72 with porous silicon (PS) sacrificial layer 74 and a top oxide 16B for wafer bonding.

Wafer bonding and separation is carried out according to the standard ELTRAN process between wafers 60 and 70 (Fig. 7C). The wafer at the end of the process (Fig. 7D) includes a buried p-n junction 80 (similar to that of 12-14 in Fig. IA or 2) and a second, bottom BOX 50 as required. Thus, the present invention provides the novel technique for vertical integration of CMOS sensors and CMOS electronics using SOI wafers. The SOI CMOS sensor is formed by a buried p-n photodiode (below the BOX) and a top SOI layer available for CMOS electronics. The vertically integrated SOI CMOS sensor is ideal for backside illumination with all pixel area being available for electronic design. Such a sensor could also be configured for operating with front side illumination, where the light has to pass through the top thin silicon layer and the poly silicon gate level. These layers are equivalent to the double poly silicon layers of conventional CCD imagers. The SOI CMOS sensor of the present invention can be fabricated by the SOI ELTRAN process to form a buried p-n junction and a second BOX layer for substrate removal.

Those skilled in the art will readily appreciate that various modifications and changes can be applied to the embodiments of the invention as hereinbefore . exemplified without departing from the scope as defined in and by the appended claims.

Claims

CLAIMS:

1. An active pixel sensor comprising: a silicon substrate patterned to form a photodetector arrangement therein; a silicon-on-insulator (SOI) layer structure on said substrate, the silicon layer of said SOI layer structure carrying an electronics circuit vertically integrated with said photodetector arrangement for processing output thereof.

2. The sensor of Claim 1, comprising a single wafer structure formed by said substrate and said SOL

3. The sensor of Claim 1 or 2, comprising an upper electrically insulating layer on top of the SOI.

4. The sensor of any one of preceding Claims, wherein said photodetector arrangement is in the form of an array of spaced-apart doped regions of the silicon substrate, defining the array of photosensitive regions, spaced by electrically insulating regions.

5. The sensor of Claims 3 and 4, wherein the electronic circuit comprises a plurality of differently doped regions in the silicon layer of said SOI and lithography patterned electrically conductive regions in the upper electrically insulating layer on top of the SOI^ defining a transistor arrangement.

6. The sensor of Claim 5, wherein the SOI layer structure and said upper layer are patterned to form vertical interconnects between the photosensitive regions and the respective elements of the electronic circuit.

7. The sensor of Claims 6, wherein the electronic circuit comprises lithography patterned electrically conductive regions in the upper electrically insulating layer on top of the SOI layer structure, defining a capacitor arrangement.

8. The sensor of any one of preceding Claims, wherein the silicon substrate has a thickness allowing illumination therethrough of the photodetector arrangement.

9. The sensor of Claim 8, wherein the silicon substrate has the thickness of about 20 micrometers.

10. The sensor of Claim 8 or 9, wherein the substrate thickness is selected to enable diffusion of current carriers, generated in the substrate in response to the illumination, to the photodetector arrangement.

11. The sensor of any one of Claims 8 to 10, comprising a lowermost electrically insulating layer carrying said substrate thereon and being transparent for certain wavelength range allowing illumination therethrough of the photodetector arrangement.

12. The sensor of any one of preceding claims, being configured by patterning a single wafer structure, which is formed by the unpatterned silicon substrate and the SOI layer structure on said unpatterned substrate.

13. The sensor of Claim 12, wherein said single wafer structure is formed by bonding between first and second wafer structures, the first wafer structure being formed by an SOI carried on top of a first silicon substrate and covered by a first electrically insulating layer, and the second wafer structure being formed by a second silicon substrate covered by a second electrically insulating layer, the first and second wafers being bonded at the first and second electrically insulating layers, thereby forming said SOI layer structure including the second silicon substrate on the electrically insulating layer, resulting from said boding.

14. An active pixel sensor comprising: (a) a silicon substrate patterned to define a photodetector arrangement formed by an array of doped regions defining the array of photosensitive elements spaced by electrically insulating regions;

(b) a silicon-on-insulator (SOI) layer structure on said substrate, the silicon layer of said SOI layer structure carrying elements of an electronics circuit configured such that each element of the electronic circuit is vertically integrated with the respective photosensitive element for processing output thereof;

(c) an upper electrically insulating layer patterned with electrically conductive regions defining gate electrodes of the transistors; (d) vertical interconnects between the photosensitive regions and the respective elements of the electronic circuit.

15. A method of fabricating an active pixel sensor with an electronics circuit vertically integrated with a photodetector arrangement, the method comprising: providing a silicon-on-insulator (SOI) layer structure on a p-type silicon substrate; processing said SOI layer structure by applying thereto or therethrough an ion implantation or material diffusion, and by applying material removal processes, to thereby define elements of said electronics circuit and elements of said photodetector arrangement vertically integrated with each other in a single wafer structure.

16. The method of Claim 15 comprising: providing a wafer structure formed by the SOI layer structure on the p- type silicon substrate; applying said processing to the substrate through the SOI layer structure to define a photodetector arrangement layer therein; forming an upper insulator layer by oxidizing the silicon layer of said

SOI; applying patterning procedures to the upper insulator layer, and the silicon layer and the buried oxide layer of said SOI layer structure, to form elements of the electronic circuit vertically aligned with the photodetector arrangement; patterning the upper layer, the SOI layer structure and the substrate to define an array of photodiodes of the photodetector arrangement such that each photodiode is vertically aligned with its corresponding element of the electronic circuit.

17. The method of Claim 16, wherein said processing to define the photodetector layer comprises applying ion implantation to the substrate through the SOI layer structure.

18. The method of Claim 16 or 17, wherein said patterning procedures comprise patterning the silicon layer of the SOI layer structure by applying ion implantatioii thereto to form transistor elements, and patterning the SOI layer structure and the upper layer by the material removal to form transistor and capacitor element, and interconnects between the electronics and the photodetector arrangement.

19. The method of Claim 15, comprising: providing first and second wafer structures, the first wafer structure being formed by an SOI carried on top of a first silicon substrate and covered by a first electrically insulating layer, the silicon layer of said SOI presenting the photodetector arrangement layer, and the second wafer structure being formed by a second silicon substrate covered by a second electrically insulating layer, bonding the first and second wafer structures at the first and second electrically insulating layers, thereby forming said SOI layer structure including the second silicon substrate on the electrically insulating layer resulting from said boding; applying the material removal to partially remove the second silicon substrate; oxidizing an upper surface of the second silicon substrate to thereby enable formation of an upper electrically insulating layer; patterning said SOI layer structure, to form elements of the electronic circuit vertically aligned with the photodetector arrangement; patterning the upper electrically insulating layer, the SOI layer structure and the first substrate below the SOI layer structure to define an array of photodiodes of the photodetector arrangement such that each photodiode is vertically aligned with its corresponding element of the electronic circuit.

20. The method of any one of Claims 15 to 18, comprising at least partially removing the substrate layer to thereby enable backside illumination therethrough of the photodetector arrangement.

21. The method of Claim 20, comprising forming a lower insulator layer interfacing said substrate layer, said lower insulator layer being transparent to said illumination.

22. The method of Claim 19, comprising at least partially removing the first substrate layer to thereby enable backside illumination therethrough of the photodetector arrangement.