WO2006002615A2 - Elektrisches mehrschichtbauelement mit zuverlässigem lötkontakt - Google Patents
Elektrisches mehrschichtbauelement mit zuverlässigem lötkontakt Download PDFInfo
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- WO2006002615A2 WO2006002615A2 PCT/DE2005/001155 DE2005001155W WO2006002615A2 WO 2006002615 A2 WO2006002615 A2 WO 2006002615A2 DE 2005001155 W DE2005001155 W DE 2005001155W WO 2006002615 A2 WO2006002615 A2 WO 2006002615A2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C1/00—Details
- H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C1/00—Details
- H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
- H01C1/144—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors the terminals or tapping points being welded or soldered
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
- H01C7/18—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material comprising a plurality of layers stacked between terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09827—Tapered, e.g. tapered hole, via or groove
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09845—Stepped hole, via, edge, bump or conductor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49149—Assembling terminal to base by metal fusion bonding
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- the invention relates to an electrical multilayer component whose basic body is constructed from dielectric layers, between which metallization planes formed as component structures are arranged.
- such multilayer components can be used, for example, as capacitors, varistors or temperature-dependent resistors (thermistors).
- a multilayer varistor in which, in order to reduce the resistance, non-overlapping internal electrodes are arranged in the interior of the base body.
- the internal electrodes are contacted on the two end faces of the component by large-area contact layers, which allow an SMD mounting of the component.
- the disadvantage of such a conventional component is that parasitic capacitances and inductances are built up on account of the large-area contact layers, which makes precise adjustment of the electrical characteristics of the component difficult.
- due to the large contact layers such a component requires a corresponding amount of space when mounted on, for example, printed circuit boards.
- modules in this construction in which several of these components are integrated, are particularly large and thus have a particularly low integration density.
- multi-layer devices which can be mounted by means of flip-chip mounting on a PCB circuit board.
- solderable contacts on the underside which enable soldering onto the PCB by means of bumps. Since such a component is usually fastened by means of a multiplicity of bumps and the material of the multilayer components differs from that of the PCB, high mechanical stresses can occur, in particular during temperature changes, which load the solder joints and in particular the associated metallizations. Bumps can therefore come loose from the solder contacts, the solder contacts can detach from the multilayer component, or the plated-through holes which are connected to the solder contacts and establish the connection to the internal component structures can be pulled out of the lowermost dielectric layer by the bumps.
- the invention proposes to design in the base body of the multilayer component at least the plated-through holes which are in contact with the solder contacts applied on the underside of the base body in such a way that their cross-section widens, at least in some sections, upwards, ie in a pioneering manner from the soldering contact.
- a plated-through hole and a soldering contact connected thereto will be obtained, which, due to the through-hole widening upwards, secure a secure hold in the base body. sitting.
- the plated-through hole which consists of a corresponding hole in the dielectric layer and the metallization arranged therein, is secured in this way against pulling out of the base body. The tearing off of the soldering contact by forces acting on the soldering contact after soldering on eg a circuit board is made more difficult.
- the main body itself comprises a plurality of ceramic dielectric layers stacked on top of one another, between which structured metallization levels are provided to component structures.
- the internal electrical connection between different metallization levels and between the component structures and the solder contacts is made via plated-through contacts, which can each extend through one or more of the dielectric layers.
- all plated-through holes can be designed in the manner according to the invention, but at least those which are connected to the soldering contacts on the underside of the base body.
- the dielectric layers may advantageously comprise an electroceramic.
- the ceramic material may thus comprise a varistor ceramic based on ZnO-Bi or ZnO-Pr.
- the ceramic material may further comprise a capacitor ceramic selected from so-called NPO ceramics, eg (Sm, Pa) NiCdO3. These ceramics have temperature-dependent ⁇ r values and are non-ferroelectric ceramics.
- ferroelectric ceramics with high dielectric constants as well as doped BaTiO 3 and so-called barrier layer ceramics can also be used. These dielectric ceramics are published in the book "Keramik” by H. Schaumburg (ed.), BG Teubner-Verlag Stuttgart 1994 pages 351 to 352 and 363, with full reference to these pages.
- the ceramic material can be selected from thermistor ceramics, NTC ceramics, for example nickel manganese spinels and perovskites.
- dielectric non-ceramic materials for example glasses.
- all the dielectric layers are either a varistor, thermistor or capacitor ceramic, so that no dielectric layers are present in the main body that do not have one of these electrical properties.
- This embodiment is characterized in that a maximum contact area with the dielectric layer (s) is available in the area of the through-hole or its bore through which the plated-through hole passes.
- a via has a maximum contact area both with the solder contact and with the component structure, which is connected to the solder contact via the through-connection.
- the plated-through contacts are concave in cross-section on the sides. In this case, the center section of the via with the smallest diameter or the smallest cross-sectional area can be obtained by rounding off the edges of the dielectric layer / dielectric layers bordering the via.
- the plated-through holes are formed such that they have a cross section which corresponds to a double cone in which the two tips collide or penetrate one another.
- the solder contacts are provided at least in the area which corresponds to the sectional area of the through-hole leading to the underside of the base body with this underside. In the case of highly miniaturized components or in the case of small base bodies and small diameters of the plated-through holes, this area alone may be sufficient for producing a soldering contact. The area is also sufficient if the diameter of the bumps which are connected to the soldering contact is approximately equal to the diameter of the respective through-connection on the underside. This particularly concerns components in which a large number of bumps are required in order to produce the necessary electrical connections of the component, the diameters of the bumps then being e.g. in the range 30 - 100 microns.
- the soldering contact requires a larger area and is applied on the underside of the base body in such a way that it partially overlaps or comes to rest on the lowest ceramic dielectric layer.
- it is in part, to equip the partial layer of the solder contact which is in direct contact with the ceramic dielectric layer with a glass component which ensures better adhesion to the ceramic dielectric layer.
- this layer then comprises at least one metal or a metal alloy.
- Such a solder contact is preferably applied in the form of a printable paste and is baked, for example.
- the solder contacts comprise a layer whose material is selected from tin (Sn), tin lead alloy (SnPb), tin-silver copper alloy (SnAgCu), tin-silver copper bismuth alloy (SnAgCuBi), tin zinc alloy (SnZn) and tin-silver alloy (SnAg).
- the soldering contact may also comprise further layers selected from this spectrum.
- a diffusion barrier layer is provided in the solder contact. This prevents it when soldering the Bau ⁇ elements, so when applying or soldering the bump on the soldering contact to an alloy formation with components of the metallization within the via, which may change their properties inadmissible or even a separation of the electrical connection could result
- this is advantageous when using lead-free solders, since the material of these solders tends to form alloys with the silver and palladium, which are preferably used in the plated-through holes.
- the diffusion barrier layer for preventing alloying formation is advantageously selected from nickel, tin and gold.
- the diffusion barrier layer can be close to the plated-through hole or even further away from the plated-through hole removed layer region of the solder contact can be arranged.
- the soldering contact can consist solely of the diffusion barrier layer then produced directly and exclusively via the plated-through hole.
- the soldering contact advantageously has an oxidation protection layer with which, for example, the oxidation of the directly underlying layer of the soldering contact, e.g. a nickel layer used as a diffusion barrier layer can be prevented.
- an oxidation protective layer can be selected, for example, from gold, tin and an organic layer. While a gold-containing oxidation protection layer permanently protects the solder contact, the tin layer can also be alloyed during soldering, but this is not disturbing. By contrast, the organic oxidation layer is oxidatively destroyed or evaporated during the soldering process. After oxidation, no oxidation protection layer is required, since oxidation can still take place superficially and can no longer interrupt the current path or can no longer lead to a substantial increase in the corresponding resistance. Even a soldering capacity that is impaired by this is irrelevant.
- a passivation for the ceramic dielectric layers is provided on the base body.
- glass layers are well suited for this purpose, which has both a good adhesion, mechanical stability and the necessary tightness against moisture and thus also ensures adequate protection of the ceramic, in particular against attack by acidic or basic metal deposition baths.
- the passivation is as electrical insulation required when a galvanic is used to produce the solder contacts.
- organic layers for lower demands on the passivation it is also possible to use other and, for example, organic layers as a passivation.
- the passivation can be vapor-deposited, printed, sputtered, spin-coated, dropped or otherwise applied.
- the soldering contact Since the soldering contact must remain free of the passivation, it is generated after the passivation.
- openings in the passivation are left open or produced subsequently.
- a contact surface is produced before the passivation on the vias, which has a sufficient area.
- the openings in the passivation, via which the solder contact then makes contact with the contact surface and thus with the plated-through holes, can then be arranged over an arbitrary surface area of the contact surface. It is therefore not necessary according to the invention to arrange the openings with high accuracy exactly over the plated-through holes, which increases process reliability.
- the metallizations for the plated-through holes may be selected from silver (Ag), palladium (Pd), platinum (Pt), silver palladium (AgPd), silver platinum (AgPt), silver palladium platinum (AgPdPt), nickel (Ni), copper ( Cu) or gold (Au). These materials can be introduced into the corresponding holes / holes for the vias already at the stage of the green sheets and sintered together with them.
- the Selection of the corresponding material for the plated-through holes is dependent on the ceramic material and in particular on the sintering temperature required for the ceramic material.
- the plated-through holes can be made of silver. Higher-internal ceramics such as, for example, HTCC ceramics require more temperature-resistant materials and, in particular, platinum.
- the soldering contact seated on the underside of the main body can have as a bottom layer directly connected to the ceramic dielectric layer an adhesion promoter layer which is selected from nickel, copper, chromium or silver. These materials show particularly good adhesion on the ceramic and therefore increase the adhesion of the entire solder contact even during operation of the component.
- a component according to the invention can be designed for different functions and is defined by selecting the ceramic and by structuring the corresponding metallization planes.
- the component can be designed as a multilayer varistor, as a ceramic multilayer capacitor, as a multi-layer thermistor or as a multilayer component comprising a ferrite ceramic.
- a ceramic multilayer capacitor is characterized by a dielectric having a high dielectric constant and by a multilayer electrode structure realized in the metallization planes, wherein two types of overlapping electrodes are mutually arranged one above the other so that a desired and in particular maximum overlap area between the different ones Types of electrodes results.
- the dielectric constant is for a ceramic multilayer capacitor still the Tempe ⁇ ratur relevant, wherein an inventive designed as a multilayer capacitor base body Dielektri ⁇ cums harshen comprises, which may be selected from the temperature classes COG, X7R, Z5U and Y5V.
- the component can also contain ceramic layers from other temperature classes.
- An inventive component designed as a ceramic multilayer varistor preferably has ke ⁇ ramic layers of bismuth-doped zinc oxide (ZnO-Bi) or praseodymium-doped zinc oxide (ZnO-Pr) in the main body.
- ZnO-Bi bismuth-doped zinc oxide
- ZnO-Pr praseodymium-doped zinc oxide
- the ceramic base body can also comprise an LTCC or HTCC ceramic. If individual layers of this ceramic are selected from the materials suitable for capacitors, varistors or thermistors, component functions as a two-layer or multi-layer component of the capacitor, thermistor, varistor or ferrite component type can also be realized in the LTCC ceramic.
- the ceramic base body can also be the substrate of a module, wherein a plurality of active or passive components are arranged on the upper side of the main body and electrically connected to component structures arranged in the interior of the base body, wherein the component structures in the Inner are formed as further passive components and / or interconnection structures.
- the module or the module substrate can also be soldered onto PCB printed circuit boards with the aid of solder contacts arranged on the underside, wherein the advantages of the soldering contact and via configuration according to the invention also prove themselves in this case and the Module to an improved durability and thus help life longer.
- Figure 1 shows a detail in schematic cross section of an inventive component
- FIGS. 2 to 5 show various embodiments of through holes according to the invention with reference to schematic cross sections
- FIG. 6 shows the structure of a solder contact in schematic cross section
- FIGS. 7 to 9 show various exemplary embodiments of electrical components in a schematic cross section
- FIG. 10 shows a detail of a component soldered to a printed circuit board in a schematic cross section
- FIG. 11 shows a detail of a component with a passivation
- FIG. 12 shows a detail of a component with additional contact area under the passivation and solder contact
- FIG. 13 shows a detail of a component with additional contact area under the passivation and not centered solder contact
- Figure 14 shows a detail of a component with a
- FIG. 1 shows a detail of a multi-layer component according to the invention in schematic cross-section. Shown are two dielectric layers DS1, DS2, between which a metallization plane is arranged, of which only one conductor section LA is shown in the figure. Not illustrated are further dielectric layers and further metallization levels, which are structured to form component structures, in a given arbitrary number, which continue the illustrated base body by way of "upward".
- a solder contact LK is arranged on the underside US of the base body, which is connected via a plated-through hole DK1 to a metallization level, in this case to the conductor section LA.
- the Englishkntunkie tion DKl has at least in sections, here over the entire height of the lowermost dielectric layer DS1, have a cross section which widens upwards.
- the further available plated-through holes which connect further metallization planes or the component structures arranged therein, only one further through-contact DK2 is shown here.
- the further fürmorie ⁇ tion can be formed as shown in a known manner with vertical side walls, but can also like the According to the invention, the bottom-most through-contacting DKL, which leads to the soldering contact LK, is designed with a cross section which widens upwards. Otherwise, the through-contacts, which are also referred to as vias, are the manufacturing methods and material selections known for conventional plated-through holes. The production of the through-hole formed according to the invention will be discussed later.
- FIG. 2 shows a further embodiment of a through-connection DK1 according to the invention in a dielectric layer DS in a schematic cross-section.
- This through-hole has its smallest cross-section in a middle section and has concave outer edges.
- the through-hole dielectric layer DS has rounded edges in cross-section.
- FIG. 3 shows a further possible shaping of plated through holes DK1 according to the invention through a dielectric layer DS.
- a middle section as seen with respect to the height of the dielectric layer h ⁇ s, has the smallest cross-section. From this middle section, the cross section increases in a linearly increasing manner, in both directions - in the direction of the solder contact LK and in the opposite direction. In this case, a cross section is obtained, which has the shape of a colliding with the tips of a double cone.
- Vias formed in accordance with the invention can be produced with appropriately shaped, for example, rotating tools in the intended form in a ceramic green sheet as holes and then metallized in a manner known per se or filled with a metallic mass. It is also possible to produce the through-connection with a material that is not directed vertically against the green sheet and ablates the material.
- An elegant method of making via holes consists in a controlled controlled production of the multilayer main body.
- a suitable temperature control at a suitable pressure and a suitable metallization within the plated-through connection, it is possible to constrict the through contact during pressing and the subsequent sintering in the middle, resulting in the desired cross-sectional shape.
- FIG. 4 shows, in a further embodiment, a through-connection according to the invention, which is guided through two directly adjacent dielectric partial layers TS2, TS3.
- the through-connection through the individual partial layers differs with respect to the cross-sectional area or the diameter.
- the lower plated-through hole DK12 through the dielectric sub-layer TS2 has a smaller diameter than the upper through-hole DK13 through the second dielectric sub-layer TS3.
- a through-connection according to the invention can also be guided by three (or more) dielectric partial layers TS1 to TS3, the through-connection DK12 having the smallest diameter through the middle dielectric partial layer TS2.
- the plated-through holes DK13 through the third partial layer TS3 and the plated-through hole DKI1 through the first partial layer TS1 have a larger diameter than the through-hole DK12.
- the embodiments according to FIGS. 4 and 5 have the advantage that they can be produced easily with conventional apparatuses and methods for the production of multilayer components, since the partial plated-through holes DK 11, DK 12 are each covered by the partial layers TS Way with vertical side walls can be performed.
- FIG. 6 shows by way of a schematic cross section the possible structure of a solder contact LK according to the invention.
- the soldering contact is located on the underside of the lowermost dielectric layer DS and is preferably arranged centered to the plated-through hole DK1.
- An adhesion-promoting layer HVS is provided directly above the via-contacting and furthermore on the ceramic, which layer has, for example, a glass content or which comprises nickel, copper, chromium or silver in order to improve the adhesion of one of the metals.
- This adhesion-promoting layer HVS is reinforced with a reinforcing layer VS, which provides the actual metallic base of the soldering contact.
- a further layer arranged above it is a diffusion barrier layer DSS, which in turn is covered by an oxidation protection layer OSS.
- DSS diffusion barrier layer
- OSS oxidation protection layer
- the lowermost adhesion-promoting layer HVS of the solder contact LK can be printed or sputtered on
- the layers applied above or above can be applied by galvanic reinforcement of the adhesion-promoting layer or likewise by sputtering.
- the galvanic reinforcement of the adhesion-promoting layer HVS is self-adjusting, since a metal deposition takes place only on the already existing metallic layer, the production is defined by sputtering, for example by means of a mask.
- FIG. 7 shows further details of a possible configuration of the component structures in the interior of the main body GK.
- Dar ⁇ is a ceramic multilayer capacitor having ei ⁇ NEN first stack of electrode layers ESL.
- electrode layers ES2 of a second stack are arranged in such a way that the maximum possible overlapping area results.
- At least one electrode layer ES of each electrode stack is connected via a plated-through hole DKI1, DK12 to its own soldering contact LK1, LK2 on the underside of the base body GK.
- the electrode layers ES belonging to an electrode stack can likewise be connected to one another by through contacts DK21, DK22, which are arranged in the figure, for example, offset from the plated-through holes DK1.
- the plated-through holes for connecting the electrode layers ES of a stack and the plated-through hole for connecting the stack to the corresponding soldering contact LK may be centered or arranged concentrically one above the other.
- the plated-through hole DK 12 is guided in FIG. 7, for example, by two dielectric layers, wherein the cross-sectional shape of the plated-through holes through the individual layers may have the design according to the invention per se, as illustrated, for example, for the through-hole DKI 1 in FIG.
- FIG. 8 shows an embodiment of a component according to the invention as a varistor, in which likewise two stacks of electrode layers ES1, ES2 are provided in the main body GK, the electrode layers of different stacks, however, not overlapping. A region B between the stacks therefore has no electrodes.
- a multilayer component such as a capacitor or a thermistor with an electrode arrangement according to FIG. In this case, the distance between the electrode stacks and the ceramic material determines the component resistance or the capacitance.
- FIG. 9 shows in cross section a further embodiment of a multilayer component according to the invention in which electrodes E1 to E14 which do not overlap one another overlap with a single electrode E20 of larger area.
- Each of the electrode layers Ell to E14 is connected via its own through-connection DKI1 to DK14 with its own solder contact LKI1 to LK14.
- the electrode layers E20 are connected via a plated-through hole DK20 to a solder contact LK20.
- the plated-through hole may be guided over more than one dielectric layer depending on the position of the electrode layer to be contacted.
- the plated-through holes according to the invention are shown in a straight line in FIGS. 7 to 9, but in reality have cross-sectional shapes according to the invention with cross-section pointing away from solder contact.
- a component according to the invention is not limited to this number. It is possible, for example, to connect component structures or electrode layers ES, conductor track sections LA or other parts of the metallization planes parallel over a plurality of plated-through holes DK with optionally a plurality of solder contacts, in order to reduce the corresponding connection resistance or around the Sheet resistance of electrode layers, Porterbahnab ⁇ cut or component structures in the interior of Grundkör ⁇ Pers GK to bridge. It is also possible to produce more than two-pole components which have a plurality of terminals of different polarity, or to which a corresponding number of signals with different potential can be applied. This is the case in particular in the case of components which have complex interconnection structures in the interior or which have a plurality of stacks of electrode layers which can be addressed individually via the corresponding plated-through holes and solder contacts or can be electrically interconnected via these elements.
- Figure 11 shows a detail of a component with a passivation P, which is applied here over the solder contact LK. An opening in the passivation releases the surface area of the solder contact to which the bump is applied.
- FIG. 12 shows a further modification of the component described in FIG. Under the passivation, an additional contact surface KF is arranged.
- the solder contact LK above the passivation P is in the opening OE with the Kon ⁇ contact surface and thus in contact with the via contact.
- FIG. 13 shows a detail of a further modification of the component described in FIG. 12, with the difference that here the solder contact LK is not centered over the plated-through hole DK.
- the passivation is e.g. a glass layer.
- Figure 14 shows a detail of a device with a passivation P.
- An opening OE in the passivation leaves the Area of the via freely, which can then be used directly as a surface for the solder contact.
- FIG. 10 shows a detail of the connection of a multi-layer component according to the invention by means of a solder ball or a bump BU with a printed circuit board PCB on the basis of a single solder joint.
- the solder joint between the solder contact LK on the underside of the base body GK and a solder pad LP on the top side of the printed circuit board PCB is connected via the bump BU.
- the bump wetted in the soldered state, the entire surface of the corresponding LötWallete LK or solder pads LP, so that the surface of these contacts or pads for given volume of the bump determines the height of the bump and thus the distance in which the body GK or the Multi-layer component is mounted over the PCB PCB.
- soldering shown in Figure 10 is also referred to as a flip-chip arrangement.
- a multiplicity of bumps BU can connect the electrical and mechanical connection of all solder contacts LK on the underside of the component to the corresponding pads on the surface of the conductor plate.
- the circuit board can be designed as a ball grid array or land grid array.
- the invention encompasses any configurations of component structures that can be realized in metallization levels between dielectric layers.
- Such component structures may comprise passive components which are interconnected or complex interconnection structures which comprise passive components realized in the basic body, such as resistors, capacitances, inductances.
- the main body or the dielectric layers preferably the same ceramic materials are used. However, it is also possible to realize different dielectric layers within the main body. Parts of the dielectric layers can therefore also consist of non-ceramic materials, for example of plastics.
- the ceramic is adapted to the material of the printed circuit board PCB with regard to its thermal expansion coefficient, which additionally reduces the thermal stresses of the entire component.
- thermal expansion coefficient there is a difference in the thermal expansion coefficient of only 5.6 ppm between a ZnO-comprising dielectric layer and a printed circuit board made of FR4 material.
- Such a selected combination of materials with differences between 5 and 7 ppm is substantially improved in durability compared to known material combinations which have differences in the thermal expansion coefficient of 9 to 11.
- a component according to the invention is also not limited to the number of dielectric layers or the metallization levels arranged therebetween with component structures and can be realized, for example, from two dielectric layers. Also not shown is the embodiment in which the main body exclusively serves as a carrier substrate for a module whose components are arranged or realized on and in the module substrate. LIST OF REFERENCE NUMBERS
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/630,524 US20070271782A1 (en) | 2004-07-01 | 2005-06-30 | Electrical Multilayer Component with Solder Contact |
JP2007518446A JP4838795B2 (ja) | 2004-07-01 | 2005-06-30 | 高信頼性のはんだ付けコンタクトを備えた電気的な多層構成素子 |
EP05782178.7A EP1761936B1 (de) | 2004-07-01 | 2005-06-30 | Elektrisches mehrschichtbauelement mit zuverlässigem lötkontakt |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004031878.6 | 2004-07-01 | ||
DE102004031878A DE102004031878B3 (de) | 2004-07-01 | 2004-07-01 | Elektrisches Mehrschichtbauelement mit zuverlässigem Lötkontakt |
Publications (2)
Publication Number | Publication Date |
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WO2006002615A2 true WO2006002615A2 (de) | 2006-01-12 |
WO2006002615A3 WO2006002615A3 (de) | 2006-06-01 |
Family
ID=34980845
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2005/001155 WO2006002615A2 (de) | 2004-07-01 | 2005-06-30 | Elektrisches mehrschichtbauelement mit zuverlässigem lötkontakt |
Country Status (5)
Country | Link |
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US (1) | US20070271782A1 (de) |
EP (1) | EP1761936B1 (de) |
JP (1) | JP4838795B2 (de) |
DE (1) | DE102004031878B3 (de) |
WO (1) | WO2006002615A2 (de) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2012028659A3 (de) * | 2010-09-03 | 2012-07-26 | Epcos Ag | Keramisches bauelement und verfahren zur herstellung eines keramischen bauelements |
US8717120B2 (en) | 2008-04-16 | 2014-05-06 | Epcos Ag | Multi-layered component |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102004032706A1 (de) * | 2004-07-06 | 2006-02-02 | Epcos Ag | Verfahren zur Herstellung eines elektrischen Bauelements und das Bauelement |
DE102004058410B4 (de) * | 2004-12-03 | 2021-02-18 | Tdk Electronics Ag | Vielschichtbauelement mit ESD-Schutzelementen |
JP5078500B2 (ja) * | 2006-08-30 | 2012-11-21 | 三洋電機株式会社 | 素子搭載用基板、半導体モジュールおよび携帯機器 |
DE102007044604A1 (de) * | 2007-09-19 | 2009-04-09 | Epcos Ag | Elektrisches Vielschichtbauelement |
DE102008009817A1 (de) * | 2008-02-19 | 2009-08-27 | Epcos Ag | Verbundwerkstoff zur Temperaturmessung, Temperatursensor aufweisend den Verbundwerkstoff und Verfahren zur Herstellung des Verbundwerkstoffs und des Temperatursensors |
DE102008035102A1 (de) * | 2008-07-28 | 2010-02-11 | Epcos Ag | Vielschichtbauelement |
CH708584A1 (de) | 2013-09-16 | 2015-03-31 | Micro Motor Ag | Anordnung elektrischer Bauteile und elektrischer Antriebsmotor mit einer Bauteileanordnung |
DE102016100352A1 (de) * | 2016-01-11 | 2017-07-13 | Epcos Ag | Bauelementträger mit ESD Schutzfunktion und Verfahren zur Herstellung |
CN112424887B (zh) | 2018-07-18 | 2022-11-22 | 京瓷Avx元器件公司 | 变阻器钝化层及其制造方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6187418B1 (en) * | 1999-07-19 | 2001-02-13 | International Business Machines Corporation | Multilayer ceramic substrate with anchored pad |
US6203926B1 (en) * | 1992-12-29 | 2001-03-20 | International Business Machines Corporation | Corrosion-free multi-layer conductor |
US6225569B1 (en) * | 1996-11-15 | 2001-05-01 | Ngk Spark Plug Co., Ltd. | Wiring substrate and method of manufacturing the same |
US6351369B1 (en) * | 1999-11-19 | 2002-02-26 | Murata Manufacturing Co., Ltd | Multi-layer capacitor, wiring substrate, decoupling circuit, and high-frequency circuit |
US20020046880A1 (en) * | 1997-06-03 | 2002-04-25 | Kabushiki Kaisha Toshiba | Hybrid wiring board, semiconductor apparatus, flexible substrate, and fabrication method of hybrid wiring board |
Family Cites Families (97)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3612963A (en) * | 1970-03-11 | 1971-10-12 | Union Carbide Corp | Multilayer ceramic capacitor and process |
US4954875A (en) * | 1986-07-17 | 1990-09-04 | Laser Dynamics, Inc. | Semiconductor wafer array with electrically conductive compliant material |
US4935844A (en) * | 1987-01-13 | 1990-06-19 | Ian Burn | Low dielectric constant compositions |
US4803450A (en) * | 1987-12-14 | 1989-02-07 | General Electric Company | Multilayer circuit board fabricated from silicon |
US5065284A (en) * | 1988-08-01 | 1991-11-12 | Rogers Corporation | Multilayer printed wiring board |
JPH035028U (de) * | 1989-05-26 | 1991-01-18 | ||
US5063177A (en) * | 1990-10-04 | 1991-11-05 | Comsat | Method of packaging microwave semiconductor components and integrated circuits |
US5166097A (en) * | 1990-11-26 | 1992-11-24 | The Boeing Company | Silicon wafers containing conductive feedthroughs |
US5229647A (en) * | 1991-03-27 | 1993-07-20 | Micron Technology, Inc. | High density data storage using stacked wafers |
JPH0715855B2 (ja) * | 1991-08-26 | 1995-02-22 | 株式会社東芝 | セラミックコンデンサ |
US5290970A (en) * | 1992-09-18 | 1994-03-01 | Unisys Corporation | Multilayer printed circuit board rework method and rework pin |
US5369390A (en) * | 1993-03-23 | 1994-11-29 | Industrial Technology Research Institute | Multilayer ZnO varistor |
US5454161A (en) * | 1993-04-29 | 1995-10-03 | Fujitsu Limited | Through hole interconnect substrate fabrication process |
JP3005028U (ja) * | 1994-06-07 | 1994-12-06 | 富士電気化学株式会社 | 積層チップ部品 |
US5904499A (en) * | 1994-12-22 | 1999-05-18 | Pace; Benedict G | Package for power semiconductor chips |
JPH097877A (ja) * | 1995-04-18 | 1997-01-10 | Rohm Co Ltd | 多層セラミックチップ型コンデンサ及びその製造方法 |
US6224690B1 (en) * | 1995-12-22 | 2001-05-01 | International Business Machines Corporation | Flip-Chip interconnections using lead-free solders |
US6631558B2 (en) * | 1996-06-05 | 2003-10-14 | Laservia Corporation | Blind via laser drilling system |
US6209480B1 (en) * | 1996-07-10 | 2001-04-03 | Mehrdad M. Moslehi | Hermetically-sealed inductively-coupled plasma source structure and method of use |
US5905000A (en) * | 1996-09-03 | 1999-05-18 | Nanomaterials Research Corporation | Nanostructured ion conducting solid electrolytes |
JP3838457B2 (ja) * | 1997-05-30 | 2006-10-25 | Tdk株式会社 | セラミックス複合積層部品 |
TW345665B (en) * | 1997-06-23 | 1998-11-21 | Nat Science Council | Zinc oxide varistor and multilayer chip varistor with low temperature sintering properties |
US5969425A (en) * | 1997-09-05 | 1999-10-19 | Advanced Micro Devices, Inc. | Borderless vias with CVD barrier layer |
US5919329A (en) * | 1997-10-14 | 1999-07-06 | Gore Enterprise Holdings, Inc. | Method for assembling an integrated circuit chip package having at least one semiconductor device |
US5998292A (en) * | 1997-11-12 | 1999-12-07 | International Business Machines Corporation | Method for making three dimensional circuit integration |
US5949030A (en) * | 1997-11-14 | 1999-09-07 | International Business Machines Corporation | Vias and method for making the same in organic board and chip carriers |
US6542352B1 (en) * | 1997-12-09 | 2003-04-01 | Daniel Devoe | Ceramic chip capacitor of conventional volume and external form having increased capacitance from use of closely spaced interior conductive planes reliably connecting to positionally tolerant exterior pads through multiple redundant vias |
US6366443B1 (en) * | 1997-12-09 | 2002-04-02 | Daniel Devoe | Ceramic chip capacitor of conventional volume and external form having increased capacitance from use of closely-spaced interior conductive planes reliably connecting to positionally-tolerant exterior pads through multiple redundant vias |
US6114240A (en) * | 1997-12-18 | 2000-09-05 | Micron Technology, Inc. | Method for fabricating semiconductor components using focused laser beam |
US6072690A (en) * | 1998-01-15 | 2000-06-06 | International Business Machines Corporation | High k dielectric capacitor with low k sheathed signal vias |
US6054914A (en) * | 1998-07-06 | 2000-04-25 | Midcom, Inc. | Multi-layer transformer having electrical connection in a magnetic core |
JP2002524867A (ja) * | 1998-09-02 | 2002-08-06 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 薄膜キャパシタ |
US7106400B1 (en) * | 1998-09-28 | 2006-09-12 | Sharp Kabushiki Kaisha | Method of making LCD with asperities in insulation layer under reflective electrode |
FR2785448B1 (fr) * | 1998-10-30 | 2001-01-26 | Alstom Technology | Procede de fabrication d'une electrode de commande de grille pour transistor igbt |
SG78324A1 (en) * | 1998-12-17 | 2001-02-20 | Eriston Technologies Pte Ltd | Bumpless flip chip assembly with strips-in-via and plating |
JP3792445B2 (ja) * | 1999-03-30 | 2006-07-05 | 日本特殊陶業株式会社 | コンデンサ付属配線基板 |
DE19931056B4 (de) * | 1999-07-06 | 2005-05-19 | Epcos Ag | Vielschichtvaristor niedriger Kapazität |
JP3809053B2 (ja) * | 2000-01-20 | 2006-08-16 | 新光電気工業株式会社 | 電子部品パッケージ |
US6690123B1 (en) * | 2000-02-08 | 2004-02-10 | Sarnoff Corporation | Electron gun with resistor and capacitor |
US6871396B2 (en) * | 2000-02-09 | 2005-03-29 | Matsushita Electric Industrial Co., Ltd. | Transfer material for wiring substrate |
US6548224B1 (en) * | 2000-03-07 | 2003-04-15 | Kulicke & Soffa Holdings, Inc. | Wiring substrate features having controlled sidewall profiles |
KR100509058B1 (ko) * | 2000-04-11 | 2005-08-18 | 엘지전자 주식회사 | 인쇄회로기판의 제조방법 |
US6395663B1 (en) * | 2000-06-16 | 2002-05-28 | National Science Council | Low temperature sintered BI2O3-ZNO-NB2O5 ceramics and method for its formation |
CN1196392C (zh) * | 2000-07-31 | 2005-04-06 | 日本特殊陶业株式会社 | 布线基板及其制造方法 |
US6408511B1 (en) * | 2000-08-21 | 2002-06-25 | National Semiconductor, Inc. | Method of creating an enhanced BGA attachment in a low-temperature co-fired ceramic (LTCC) substrate |
JP2002075995A (ja) * | 2000-08-24 | 2002-03-15 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
EP1184637A1 (de) * | 2000-08-28 | 2002-03-06 | Mino Yogyo Co., Ltd. | Brenntraggestelle und Verfahren zu deren Herstellung |
US6388204B1 (en) * | 2000-08-29 | 2002-05-14 | International Business Machines Corporation | Composite laminate circuit structure and methods of interconnecting the same |
JP2002075784A (ja) * | 2000-08-31 | 2002-03-15 | Kyocera Corp | 薄膜コンデンサ、その製造方法及びその実装構造 |
DE10054812A1 (de) * | 2000-11-04 | 2002-05-08 | Philips Corp Intellectual Pty | Keramikkondensator mit CZT-Dielektrikum |
JP2002260959A (ja) * | 2001-03-01 | 2002-09-13 | Nec Corp | 積層コンデンサとその製造方法およびこのコンデンサを用いた半導体装置、電子回路基板 |
JP2002290030A (ja) * | 2001-03-23 | 2002-10-04 | Ngk Spark Plug Co Ltd | 配線基板 |
JP4999234B2 (ja) * | 2001-04-02 | 2012-08-15 | ルネサスエレクトロニクス株式会社 | フォトマスク及びそれを用いた半導体装置の製造方法 |
US7049929B1 (en) * | 2001-05-01 | 2006-05-23 | Tessera, Inc. | Resistor process |
JP2002338353A (ja) * | 2001-05-17 | 2002-11-27 | Aiomu Technology:Kk | 誘電体磁器組成物 |
US6744135B2 (en) * | 2001-05-22 | 2004-06-01 | Hitachi, Ltd. | Electronic apparatus |
JP2002373957A (ja) * | 2001-06-14 | 2002-12-26 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP4053257B2 (ja) * | 2001-06-14 | 2008-02-27 | 新光電気工業株式会社 | 半導体装置の製造方法 |
DE10155594A1 (de) * | 2001-11-13 | 2003-05-22 | Philips Corp Intellectual Pty | Verfrahren zum Herstellen eines aus mehreren Schichten bestehenden mikroelektronischen Substrats |
JP2003212668A (ja) * | 2002-01-28 | 2003-07-30 | Sanyo Electric Co Ltd | セラミック積層体およびその製造方法 |
US6622907B2 (en) * | 2002-02-19 | 2003-09-23 | International Business Machines Corporation | Sacrificial seed layer process for forming C4 solder bumps |
WO2003071843A1 (fr) * | 2002-02-22 | 2003-08-28 | Fujikura Ltd. | Tableau de connexions multicouche, base pour tableau de connexions multicouche, tableau de connexions imprime et son procede de production |
JP4187184B2 (ja) * | 2002-02-28 | 2008-11-26 | Tdk株式会社 | 電子部品 |
US6693356B2 (en) * | 2002-03-27 | 2004-02-17 | Texas Instruments Incorporated | Copper transition layer for improving copper interconnection reliability |
JP2003318058A (ja) * | 2002-04-25 | 2003-11-07 | Kyocera Corp | 積層コンデンサ |
KR100466073B1 (ko) * | 2002-05-24 | 2005-01-13 | 삼성전기주식회사 | 균일성 및 절연저항성이 증대된 유전체 조성물, 그제조방법 및 이를 이용한 적층 세라믹 콘덴서 |
JP2003347148A (ja) * | 2002-05-27 | 2003-12-05 | Murata Mfg Co Ltd | 導電性ペースト及び積層セラミック電子部品 |
US6759309B2 (en) * | 2002-05-28 | 2004-07-06 | Applied Materials, Inc. | Micromachined structures including glass vias with internal conductive layers anodically bonded to silicon-containing substrates |
WO2004001837A2 (en) * | 2002-06-25 | 2003-12-31 | Unitive International Limited | Methods of forming electronic structures including conductive shunt layers and related structures |
JP4043873B2 (ja) * | 2002-07-11 | 2008-02-06 | 大日本印刷株式会社 | 多層配線基板の製造方法 |
JP2004055781A (ja) * | 2002-07-19 | 2004-02-19 | Sony Corp | 半導体装置の製造方法 |
US7714432B2 (en) * | 2002-07-26 | 2010-05-11 | Intel Corporation | Ceramic/organic hybrid substrate |
US6730623B2 (en) * | 2002-09-27 | 2004-05-04 | Motorola, Inc. | Cofireable dielectric composition |
JP4143961B2 (ja) * | 2002-10-01 | 2008-09-03 | 日立金属株式会社 | 積層電子部品 |
US7005390B2 (en) * | 2002-10-09 | 2006-02-28 | Intel Corporation | Replenishment of surface carbon and surface passivation of low-k porous silicon-based dielectric materials |
JP4457630B2 (ja) * | 2002-10-17 | 2010-04-28 | 株式会社村田製作所 | 誘電体セラミックおよび積層セラミックコンデンサ |
KR100467834B1 (ko) * | 2002-12-23 | 2005-01-25 | 삼성전기주식회사 | 커패시터 내장형 인쇄회로기판 및 그 제조 방법 |
US7238609B2 (en) * | 2003-02-26 | 2007-07-03 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating semiconductor device |
US8368150B2 (en) * | 2003-03-17 | 2013-02-05 | Megica Corporation | High performance IC chip having discrete decoupling capacitors attached to its IC surface |
US7327554B2 (en) * | 2003-03-19 | 2008-02-05 | Ngk Spark Plug Co., Ltd. | Assembly of semiconductor device, interposer and substrate |
US6841883B1 (en) * | 2003-03-31 | 2005-01-11 | Micron Technology, Inc. | Multi-dice chip scale semiconductor components and wafer level methods of fabrication |
US6759318B1 (en) * | 2003-04-15 | 2004-07-06 | Kinsus Interconnect Technology Corp. | Translation pad flip chip (TPFC) method for improving micro bump pitch IC substrate structure and manufacturing process |
KR20040093402A (ko) * | 2003-04-22 | 2004-11-05 | 제이에스알 가부시끼가이샤 | 연마 패드 및 반도체 웨이퍼의 연마 방법 |
TWI317548B (en) * | 2003-05-27 | 2009-11-21 | Megica Corp | Chip structure and method for fabricating the same |
JP4377617B2 (ja) * | 2003-06-20 | 2009-12-02 | 日本特殊陶業株式会社 | コンデンサ、コンデンサ付き半導体素子、コンデンサ付き配線基板、および、半導体素子とコンデンサと配線基板とを備える電子ユニット |
WO2005001166A1 (ja) * | 2003-06-27 | 2005-01-06 | Kyocera Corporation | 金属メッキ膜の形成方法、電子部品の製造方法及びメッキ膜形成装置 |
EP1515364B1 (de) * | 2003-09-15 | 2016-04-13 | Nuvotronics, LLC | Gehäuse und Verfahren zu seiner Herstellung und zu seiner Prüfung |
US7183654B2 (en) * | 2003-09-30 | 2007-02-27 | Intel Corporation | Providing a via with an increased via contact area |
JP2005136335A (ja) * | 2003-10-31 | 2005-05-26 | Toshiba Corp | 半導体装置およびその製造方法 |
US7332805B2 (en) * | 2004-01-06 | 2008-02-19 | International Business Machines Corporation | Electronic package with improved current carrying capability and method of forming the same |
US6987316B2 (en) * | 2004-01-14 | 2006-01-17 | International Business Machines Corporation | Multilayer ceramic substrate with single via anchored pad and method of forming |
US7068138B2 (en) * | 2004-01-29 | 2006-06-27 | International Business Machines Corporation | High Q factor integrated circuit inductor |
US7027289B2 (en) * | 2004-03-25 | 2006-04-11 | Intel Corporation | Extended thin film capacitor (TFC) |
JP4574288B2 (ja) * | 2004-04-09 | 2010-11-04 | 大日本印刷株式会社 | リジッド−フレキシブル基板の製造方法 |
US7155821B1 (en) * | 2004-06-30 | 2007-01-02 | Emc Corporation | Techniques for manufacturing a circuit board having a countersunk via |
US7365007B2 (en) * | 2004-06-30 | 2008-04-29 | Intel Corporation | Interconnects with direct metalization and conductive polymer |
US7109068B2 (en) * | 2004-08-31 | 2006-09-19 | Micron Technology, Inc. | Through-substrate interconnect fabrication methods |
-
2004
- 2004-07-01 DE DE102004031878A patent/DE102004031878B3/de active Active
-
2005
- 2005-06-30 WO PCT/DE2005/001155 patent/WO2006002615A2/de active Application Filing
- 2005-06-30 EP EP05782178.7A patent/EP1761936B1/de active Active
- 2005-06-30 US US11/630,524 patent/US20070271782A1/en not_active Abandoned
- 2005-06-30 JP JP2007518446A patent/JP4838795B2/ja active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6203926B1 (en) * | 1992-12-29 | 2001-03-20 | International Business Machines Corporation | Corrosion-free multi-layer conductor |
US6225569B1 (en) * | 1996-11-15 | 2001-05-01 | Ngk Spark Plug Co., Ltd. | Wiring substrate and method of manufacturing the same |
US20020046880A1 (en) * | 1997-06-03 | 2002-04-25 | Kabushiki Kaisha Toshiba | Hybrid wiring board, semiconductor apparatus, flexible substrate, and fabrication method of hybrid wiring board |
US6187418B1 (en) * | 1999-07-19 | 2001-02-13 | International Business Machines Corporation | Multilayer ceramic substrate with anchored pad |
US6351369B1 (en) * | 1999-11-19 | 2002-02-26 | Murata Manufacturing Co., Ltd | Multi-layer capacitor, wiring substrate, decoupling circuit, and high-frequency circuit |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8717120B2 (en) | 2008-04-16 | 2014-05-06 | Epcos Ag | Multi-layered component |
WO2012028659A3 (de) * | 2010-09-03 | 2012-07-26 | Epcos Ag | Keramisches bauelement und verfahren zur herstellung eines keramischen bauelements |
Also Published As
Publication number | Publication date |
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JP2008504700A (ja) | 2008-02-14 |
JP4838795B2 (ja) | 2011-12-14 |
EP1761936B1 (de) | 2017-05-10 |
US20070271782A1 (en) | 2007-11-29 |
DE102004031878B3 (de) | 2005-10-06 |
WO2006002615A3 (de) | 2006-06-01 |
EP1761936A2 (de) | 2007-03-14 |
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