WO2005109666A3 - System and method for generating a jittered test signal - Google Patents

System and method for generating a jittered test signal Download PDF

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Publication number
WO2005109666A3
WO2005109666A3 PCT/US2005/015054 US2005015054W WO2005109666A3 WO 2005109666 A3 WO2005109666 A3 WO 2005109666A3 US 2005015054 W US2005015054 W US 2005015054W WO 2005109666 A3 WO2005109666 A3 WO 2005109666A3
Authority
WO
WIPO (PCT)
Prior art keywords
speed
signal
jittered
jitter
full
Prior art date
Application number
PCT/US2005/015054
Other languages
French (fr)
Other versions
WO2005109666A2 (en
Inventor
Mohamed M Hafed
Geoffrey D Duerden
Gordon W Roberts
Original Assignee
Dft Microsystems Inc
Mohamed M Hafed
Geoffrey D Duerden
Gordon W Roberts
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dft Microsystems Inc, Mohamed M Hafed, Geoffrey D Duerden, Gordon W Roberts filed Critical Dft Microsystems Inc
Priority to CA002564351A priority Critical patent/CA2564351A1/en
Priority to EP05744211A priority patent/EP1747617A4/en
Priority to CN2005800210865A priority patent/CN1985459B/en
Publication of WO2005109666A2 publication Critical patent/WO2005109666A2/en
Publication of WO2005109666A3 publication Critical patent/WO2005109666A3/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B3/00Line transmission systems
    • H04B3/02Details
    • H04B3/46Monitoring; Testing
    • H04B3/462Testing group delay or phase shift, e.g. timing jitter
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31708Analysis of signal quality
    • G01R31/31709Jitter measurements; Jitter generators
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31725Timing aspects, e.g. clock distribution, skew, propagation delay
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequences
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/31917Stimuli generation or application of test patterns to the device under test [DUT]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Nonlinear Science (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

A multi-speed jittered signal generator (216,400) that generates a full-speed jittered signal (404) by scaling a low-speed jittered signal (420) using a frequency scaler (428). The low-speed jittered signal is created by injecting a modulation signal (416) into a reference signal (412) using a jitter injector (432). Injecting jitter into a low-speed reference signal allows the full-speed jittered signal to be of higher quality than conventional jitter signals created by injecting jitter information into a full-speed reference signal. The multi-speed jittered signal generator may be used as part of a testing system (208) for testing various circuitry, such as high-speed serializer/deserializer circuitry (220).
PCT/US2005/015054 2004-05-03 2005-05-02 System and method for generating a jittered test signal WO2005109666A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CA002564351A CA2564351A1 (en) 2004-05-03 2005-05-02 System and method for generating a jittered test signal
EP05744211A EP1747617A4 (en) 2004-05-03 2005-05-02 System and method for generating a jittered test signal
CN2005800210865A CN1985459B (en) 2004-05-03 2005-05-02 System and method for generating a jittered test signal

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US56810204P 2004-05-03 2004-05-03
US60/568,102 2004-05-03
US11/114,572 US7315574B2 (en) 2004-05-03 2005-04-26 System and method for generating a jittered test signal
US11/114,572 2005-04-26

Publications (2)

Publication Number Publication Date
WO2005109666A2 WO2005109666A2 (en) 2005-11-17
WO2005109666A3 true WO2005109666A3 (en) 2006-12-14

Family

ID=35320924

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/015054 WO2005109666A2 (en) 2004-05-03 2005-05-02 System and method for generating a jittered test signal

Country Status (6)

Country Link
US (1) US7315574B2 (en)
EP (1) EP1747617A4 (en)
CN (1) CN1985459B (en)
CA (1) CA2564351A1 (en)
TW (1) TWI307460B (en)
WO (1) WO2005109666A2 (en)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1610137B1 (en) * 2004-06-24 2009-05-20 Verigy (Singapore) Pte. Ltd. Per-pin clock synthesis
US8327204B2 (en) * 2005-10-27 2012-12-04 Dft Microsystems, Inc. High-speed transceiver tester incorporating jitter injection
US7596173B2 (en) * 2005-10-28 2009-09-29 Advantest Corporation Test apparatus, clock generator and electronic device
US7809052B2 (en) * 2006-07-27 2010-10-05 Cypress Semiconductor Corporation Test circuit, system, and method for testing one or more circuit components arranged upon a common printed circuit board
US7835479B2 (en) * 2006-10-16 2010-11-16 Advantest Corporation Jitter injection apparatus, jitter injection method, testing apparatus, and communication chip
US20080133175A1 (en) * 2006-12-03 2008-06-05 Lobuono Mark Anthony Test interface for software-based sequence of event recording systems
US7536621B2 (en) * 2006-12-08 2009-05-19 Teradyne, Inc. Quantized data-dependent jitter injection using discrete samples
US7466140B2 (en) * 2006-12-25 2008-12-16 Advantest Corporation Signal generation circuit, jitter injection circuit, semiconductor chip and test apparatus
JPWO2008133238A1 (en) * 2007-04-24 2010-07-29 株式会社アドバンテスト Test apparatus and test method
KR101505193B1 (en) * 2007-06-18 2015-03-23 삼성전자주식회사 Symbol Transmission Method and Apparatus for used in Orthogonal Frequency Division Multiplex Access Systems
CN102006160B (en) * 2007-12-24 2013-09-11 瑞昱半导体股份有限公司 Jitter generator for generating jittering clock signals
US7917319B2 (en) 2008-02-06 2011-03-29 Dft Microsystems Inc. Systems and methods for testing and diagnosing delay faults and for parametric testing in digital circuits
US8228972B2 (en) 2008-06-04 2012-07-24 Stmicroelectronics, Inc. SERDES with jitter-based built-in self test (BIST) for adapting FIR filter coefficients
US8014465B2 (en) * 2008-06-10 2011-09-06 Advantest Corporation Digital modulator, digital modulating method, digital transceiver system, and testing apparatus
TWI405079B (en) * 2009-08-11 2013-08-11 Wistron Corp Output test method, system and platform for electrical device
US8310383B2 (en) * 2009-12-30 2012-11-13 Jds Uniphase Corporation Generating a jittered digital signal using a serializer device
US9222972B1 (en) * 2010-09-17 2015-12-29 Altera Corporation On-die jitter generator
US9172498B2 (en) 2012-03-28 2015-10-27 Futurewei Technologies, Inc. Controlled noise injection in transmitter for noise margin testing
CN102645628B (en) * 2012-04-19 2014-01-22 北京航空航天大学 Fixed-high and fixed-low fault injecting circuit and method for online test of digital circuit board
US8811458B2 (en) * 2012-10-04 2014-08-19 Qualcomm Incorporated Digitally controlled jitter injection for built in self-testing (BIST)
CN104954044A (en) * 2014-03-28 2015-09-30 北京大学 Jitter tolerance testing method and circuit for high-speed serial IO interface based on BIST
DE102015212243A1 (en) * 2015-06-30 2017-01-05 TRUMPF Hüttinger GmbH + Co. KG Device for generating a plurality of clock or high-frequency signals
US11131706B2 (en) * 2015-12-08 2021-09-28 International Business Machines Corporation Degradation monitoring of semiconductor chips
US10571501B2 (en) * 2016-03-16 2020-02-25 Intel Corporation Technologies for verifying a de-embedder for interconnect measurement
US10693589B2 (en) 2018-06-18 2020-06-23 Huawei Technologies Co., Ltd. Serdes with jitter injection self stress mechanism
US10805064B1 (en) 2019-04-23 2020-10-13 Ciena Corporation Built-in jitter loading and state of polarization generation to characterize optical transceivers
US11528102B1 (en) 2021-08-18 2022-12-13 International Business Machines Corporation Built-in-self-test and characterization of a high speed serial link receiver
US11662381B2 (en) 2021-08-18 2023-05-30 International Business Machines Corporation Self-contained built-in self-test circuit with phase-shifting abilities for high-speed receivers

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5903605A (en) * 1995-03-30 1999-05-11 Intel Corporation Jitter detection method and apparatus
US6185510B1 (en) * 1997-03-27 2001-02-06 Nec Corporation PLL jitter measuring method and integrated circuit therewith
US6522122B2 (en) * 2000-01-31 2003-02-18 Advantest Corporation Jitter measuring device and method
WO2003073680A2 (en) * 2002-02-26 2003-09-04 Advantest Corporation Jitter measuring apparatus and method

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0345390A1 (en) * 1988-06-08 1989-12-13 Hewlett-Packard Limited Improvement in or Relating to Jitter Circuits
US5835501A (en) 1996-03-04 1998-11-10 Pmc-Sierra Ltd. Built-in test scheme for a jitter tolerance test of a clock and data recovery unit
JPH1138100A (en) * 1997-07-18 1999-02-12 Advantest Corp Semiconductor test device
EP1001533B1 (en) * 1998-11-14 2001-09-26 Agilent Technologies Inc. a Delaware Corporation Timing generator
US6868504B1 (en) * 2000-08-31 2005-03-15 Micron Technology, Inc. Interleaved delay line for phase locked and delay locked loops
US6594595B2 (en) 2001-04-03 2003-07-15 Advantest Corporation Apparatus for and method of measuring cross-correlation coefficient between signals
US7184469B2 (en) * 2003-02-06 2007-02-27 Verigy Pte. Ltd. Systems and methods for injection of test jitter in data bit-streams
JP4323873B2 (en) * 2003-06-13 2009-09-02 富士通株式会社 I / O interface circuit
US7158899B2 (en) * 2003-09-25 2007-01-02 Logicvision, Inc. Circuit and method for measuring jitter of high speed signals
US7295604B2 (en) * 2003-11-24 2007-11-13 International Business Machines Corporation Method for determining jitter of a signal in a serial link and high speed serial link
US7236555B2 (en) * 2004-01-23 2007-06-26 Sunrise Telecom Incorporated Method and apparatus for measuring jitter
US7242209B2 (en) * 2004-05-03 2007-07-10 Dft Microsystems, Inc. System and method for testing integrated circuits

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5903605A (en) * 1995-03-30 1999-05-11 Intel Corporation Jitter detection method and apparatus
US6185510B1 (en) * 1997-03-27 2001-02-06 Nec Corporation PLL jitter measuring method and integrated circuit therewith
US6522122B2 (en) * 2000-01-31 2003-02-18 Advantest Corporation Jitter measuring device and method
WO2003073680A2 (en) * 2002-02-26 2003-09-04 Advantest Corporation Jitter measuring apparatus and method

Also Published As

Publication number Publication date
TWI307460B (en) 2009-03-11
WO2005109666A2 (en) 2005-11-17
EP1747617A4 (en) 2009-05-13
CN1985459A (en) 2007-06-20
US7315574B2 (en) 2008-01-01
US20050271131A1 (en) 2005-12-08
CN1985459B (en) 2010-08-11
EP1747617A2 (en) 2007-01-31
TW200606615A (en) 2006-02-16
CA2564351A1 (en) 2005-11-17

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