WO2005109650A1 - Analog-to-digital converter with range error detection - Google Patents

Analog-to-digital converter with range error detection Download PDF

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Publication number
WO2005109650A1
WO2005109650A1 PCT/US2005/011385 US2005011385W WO2005109650A1 WO 2005109650 A1 WO2005109650 A1 WO 2005109650A1 US 2005011385 W US2005011385 W US 2005011385W WO 2005109650 A1 WO2005109650 A1 WO 2005109650A1
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WO
WIPO (PCT)
Prior art keywords
analog
sequence
outputs
digital
circuit
Prior art date
Application number
PCT/US2005/011385
Other languages
French (fr)
Inventor
Jonathon Michael Jongsma
Garrie David Huisenga
Original Assignee
Rosemount Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rosemount Inc. filed Critical Rosemount Inc.
Priority to JP2007509488A priority Critical patent/JP4703643B2/en
Priority to CN2005800124658A priority patent/CN1947341B/en
Priority to EP05732479A priority patent/EP1743426B1/en
Priority to DE602005015206T priority patent/DE602005015206D1/en
Publication of WO2005109650A1 publication Critical patent/WO2005109650A1/en

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10Calibration or testing
    • H03M1/1071Measuring or testing
    • H03M1/1076Detection or location of converter hardware failure, e.g. power supply failure, open or short circuit
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/1205Multiplexed conversion systems
    • H03M1/122Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages
    • H03M1/1225Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages using time-division multiplexing
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/124Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/129Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling ; Out-of-range indication

Definitions

  • A/D converters have input pins for receiving multiple analog inputs, and provide digital outputs that represent the analog inputs.
  • the digital outputs are fed into a microcontroller which uses the digital outputs to generate a microcontroller output that is a function of the analog inputs.
  • the A/D converter and microcontroller are part of an industrial process control transmitter and the microcontroller output represents a process variable that is compensated for temperature, power supply voltages, etc., all of which are analog inputs.
  • Various types of malfunctions can occur in the circuitry.
  • a circuit comprises a multiplexer.
  • the multiplexer has a select input and a sequence of analog outputs that are selected from a plurality of analog inputs.
  • the circuit also comprises a reference source that provides a first reference.
  • the circuit comprises an analog-to-digital converter.
  • the analog-to-digital converter receives the sequence of analog outputs and the first reference.
  • the analog-to-digital converter provides a sequence of digital outputs.
  • the circuit comprises a control circuit.
  • the control circuit actuates the select input to select the sequence of the analog outputs.
  • the control circuit compares the sequence of digital outputs to a stored sequence of normal ranges that correspond with the digital outputs to provide an error output when at least one of the digital outputs is not in its normal range .
  • FIG. 1 illustrates a PRIOR ART analog-to-digital converter system.
  • FIG. 2A illustrates a first embodiment of a circuit with a dynamically changing input range.
  • FIG. 2B illustrates a first simplified flow chart of a method of error checking in the circuit illustrated in FIG. 2A.
  • FIG. 3A illustrates a second embodiment of a circuit with a dynamically changing input range.
  • FIG. 3B illustrates a second ' simplified flow chart of a method of error checking in the circuit illustrated in FIG. 3A.
  • FIG. 4A illustrates a third embodiment of a circuit with a dynamically changing input range.
  • FIG. 4B illustrates a third simplified flow chart of a method of error checking in the circuit illustrated in FIGS. 4A, 5.
  • FIG. 4A illustrates a third embodiment of a circuit with a dynamically changing input range.
  • FIG. 5 illustrates a fourth embodiment of a circuit with. a dynamically changing input range.
  • FIG. 6 illustrates an embodiment of a reference circuit .
  • FIG. 7 illustrates a block diagram of a transmitter circuit in which circuits and methods such as described above in FIGS. 2-6 can be used.
  • FIGS. 8A, 8B, 8C illustrate circuits that can be used in analog systems to provide scaling, inversion or level shifting of an analog input. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • a circuit includes a multiplexer (MUX) , an analog-to- digital converter (A/D) and a processor (typically a microcontroller (uC) ) .
  • MUX multiplexer
  • A/D analog-to- digital converter
  • uC microcontroller
  • the processor provides digital output that represents analog inputs.
  • the processor compares a sequence of digital outputs from the analog-to- digital converter to a sequence of stored normal ranges that correspond with the digital outputs.
  • the processor provides an error output when one of the digital outputs is outside its normal range.
  • the arrangement provide detection of shorted analog input pins on the multiplexer, stuck bits at the analog-to- digital convert output and other malfunctions. The arrangement is especially useful in process control applications where Safety Instrumented Systems (SIS) standards are in use.
  • FIG. 1 illustrates a PRIOR ART analog-to-digital converter system 100.
  • An analog system 102 provides continuously variable (analog) voltages Al, A2 , A3, ... , AN to a multiplexer 104.
  • Each of the analog voltages Al , A2 , A3, -.., AN has a normal voltage range indicated by vertical ranges of rectangles 1, 2, 3, ..., N at 106.
  • the analog voltages Al , A2 , A3, ... , AN can represent a process variable, a temperature, a voltage, a calibration pot setting and other analog variables.
  • the analog voltages Al As part of the design process for the analog system 102, the analog voltages Al ,
  • A2 , A3, ... , AN are scaled so that each analog voltage has a normal range of voltages that is within the input range of an analog-to-digital converter (A/D) 108.
  • the input range of the A/D 108 ranges between zero (common) and a reference input 110 of the A/D 108.
  • a reference 112 is selected which provides the desired input range (0 to +REF) to accommodate the normal ranges of all of the analog voltages Al, A2 , A3, ..., AN.
  • a digital output 114 of the A/D is coupled to a microcontroller 116.
  • the microcontroller 116 provides a digital output (M) 118 that couples to the Multiplexer (MUX) 104.
  • the multiplexer 104 receives the digital output 118 and selects one output AM to connect to the multiplexer output 120.
  • the multiplexer output 120 couples to an analog input 122 of the A/D 108.
  • the microcontroller 116 increments or steps the digital output M and obtains digital representations at output 114 for each of the relevant analog inputs Al , A2 , A3, ..., AN.
  • the microcontroller 116 calculates desired outputs 124 as a function of the digitized analog inputs Al, A2 , A3, ... AN.
  • the outputs 124 will represent process variables that are compensated for temperature, power supply voltages, calibration settings and the like that are obtained from the analog system 102.
  • Adjacent input pins on the multiplexer 104 are close together and subject to accidental or intermittent short circuiting by a short 130 during assembly or use of the multiplexer 104 on a printed wiring board.
  • analog voltages Al , A2 , A3, ..., AN tend to have voltage ranges that are crowded together and are overlapping.
  • the voltage at the two shorted together pins is typically in both of the voltage ranges for the shorted pins, and there is no "out of range” reading to identify the fact that there is a short circuit .
  • Analog voltages that are only slightly different than correct voltages may be converted by the A/D 108 and there will be no indication of the short circuit.
  • the digital output 114 of the A/D 108 is a digital word 132 that includes a number of bits ranging from a least significant bit (LSB) to a most significant bit (MSB) .
  • the number of bits generally corresponds to the output resolution of the A/D.
  • Each bit is generated by one or more switches internal to the A/D 108. These internal switches are subject to failure, and when a switch fails, typically one bit 134 of the digital word 132 becomes stuck at either a high (1) level or a low (0) level.
  • FIG. 2A illustrates a first embodiment of an circuit 200 with a dynamically changing input range and an error output 219.
  • the circuit 200 is typically used to process analog variables in an industrial process variable transmitter such as the transmitter illustrated in FIG. 7, but can be used in a wide variety of other applications using multiplexed analog-to-digital conversion.
  • the circuit 200 receives a plurality of analog inputs Al, A2 , A3, ... AN from an analog system 202.
  • Each analog input has a normal operating range (RANGE 1, RANGE 2, RANGE 3, ... RANGE N) associated with it.
  • the analog system 202 has been specially configured so that each analog input has a normal operating range that is different from the normal operating range of the other remaining analog inputs.
  • the normal operating ranges of the analog inputs are non-overlapping.
  • the analog inputs are conditioned by a combination of scaling, inversion or level shifting to provide a unique normal operating range for each analog input A. Examples of conditioning circuits are described below in connection with FIGS. 8A, 8B, 8C.
  • the circuit 200 includes a multiplexer (MUX) 204 that receives the analog inputs Al , A2 , A3, ... AN.
  • the multiplexer 204 has a select input 218 that selects one of the analog inputs Al , A2 , A3, ... AN to connect to a multiplexer output (AM) to provide a sequence of analog outputs 220.
  • the multiplexer select input 218 is a multibit word and is simply counted up (or down) to sample the analog inputs in numerical order.
  • the multiplexer 204 preferably comprises an integrated circuit analog multiplexer, for example, Analog Devices AD7501 available from Analog Devices, Inc. of Norwood, Massachusetts.
  • the circuit 200 also includes a reference source 212 that provides a first reference voltage to a reference input 210 of an analog-to-digital converter 208. In one preferred arrangement, a separate
  • reference such as a Zener diode or active reference
  • the reference source is simply a lead in circuit 200 that connects to a shared reference (such as a Zener diode or active reference) that is part of the analog system 202.
  • a reference source that is part of a commercial A/D circuit 208 is used.
  • the analog-to-digital converter (A/D) 208 receives the sequence of analog outputs (AM) 220.
  • the A/D 208 has a reference input 210 that receives the first reference voltage from reference 212.
  • the A/D 208 converts the sequence of analog inputs (AM) 220 to a corresponding sequence of digital outputs (DM) 214.
  • the multiplexer 204 presents the sequence of analog outputs (AM) 220 in a numerical sequence, and the sequence of digital outputs (DM) is also presented in a numerical sequence.
  • the individual digital outputs DM can be presented in either a serial or a parallel format, depending on the type of A/D converter that is used. In one preferred embodiment, an Analog Devices AD571 A/D converter is used, for example.
  • a digital output (for each serial or parallel digital output in the sequence) , includes a number of bits ranging from a least significant bit (LSB) to a most significant bit (MSB) as illustrated.
  • the circuit 200 includes a control circuit 216.
  • the control circuit 216 actuates the select input 218 with a numerical sequence that selects the sequence of the analog outputs to be read by the control circuit 216.
  • the control circuit 216 compares the sequence of digital outputs 214 to a stored sequence of normal ranges 217 that correspond with the digital outputs ' 214 to provide or actuate an error output 219 when at least one of the digital outputs 214 is not in its stored normal range 217.
  • the control circuit 216 preferably comprises a microcontroller, for example, a National Semiconductor COP8SGE728M8.
  • the error checking (normal range checking) runs in the background on the control circuit 216.
  • the control circuit also provides a real time output 221 that represents some useful parameter of the analog system 202.
  • the parameter of interest is a compensated pressure, temperature, or flow that is displayed or used for process control .
  • the arrangement illustrated in FIG. 2A provides for checking errors due to short circuits between analog inputs Al , A2 , A3, ... AN which all have unique, non-overlapping normal ranges.
  • the resulting voltage can only be in a single one of the normal ranges and cannot lie in two different ranges because the ranges are non-overlapping. This results in at least one, and sometimes both of the shorted analog inputs being detected as outside of normal range.
  • Short-circuiting of two of the plurality of analog inputs causes at least one of the digital outputs to exceed its corresponding normal range.
  • FIG. 2A also provides for checking errors due to one of the output bits of the A/D 208 being stuck.
  • a bit is considered stuck when the bit remains at one logic state (0 or 1) continuously, or in other words is shorted to one of the power supply rails.
  • the effect of the stuck bit is different percentage for each output in the sequence, and there is a high probability that the control circuit 216 will detect that one of the digital outputs is out of its corresponding stored normal range.
  • the sequence of digital outputs comprises digital words with a series of bits, and sticking of one of the bits causes at least one of the digital outputs to exceed its corresponding normal range.
  • FIG. 2B illustrates a simplified flow chart example of background error checking in the system illustrated in FIG.
  • Program flow starts at START 250 and proceeds to compare the current output DM (i.e., the output D when the select input is M) to the stored normal range data for range M at decision block 252. If the output DM is in the normal range, then program flow continues along lines 254, 256 to function block 258. At function block 258, the background program waits for the select input M to change to the next number. If the output DM is not in the normal range at decision block 252, then program flow continues along line 260 to function block 262 which actuates the error output 219 (FIG. 2A) and then continues along lines 264, 256 to the function block 258. When the select input M changes, then program flow starts again and continues along lines 266 back to the decision block 252.
  • FIG. 3A illustrates a second embodiment of a circuit 300 with a dynamically changing input range and an error output 219.
  • Reference numbers used in FIG. 3A that are the same as reference numbers used in FIG. 2A designate the same or similar features.
  • the circuit 300 receives a plurality of analog inputs Al, A2 , A3, ... AN from an analog system 302. Each analog input has a normal operating range (RANGE 1, RANGE 2, RANGE 3, ... RANGE N) associated with it.
  • the analog system 302 has been specially configured so that odd-numbered analog inputs (Al, A3 , ... ) are in an odd normal operating range, and even-numbered analog inputs (A2 , A4 , ...) are in an even normal operating range.
  • the odd and even operating ranges of the analog inputs are non-overlapping and each of the two operating ranges extends over about one half of the input range of the A/D 208.
  • the analog inputs are conditioned by a combination of scaling, inversion or level shifting so that alternately numbered analog inputs are in alternating normal operating ranges.
  • FIG. 3B illustrates an example of a simplified flow chart of background error checking useful in the system illustrated in FIG. 3A.
  • Program flow begins at START 301 and continues along line 303 to decision block 304.
  • the current select input number "M” is tested to find out if it is even. If the input number "M” is even, then program flow continues along line 306 to decision block 308. If the number "M” is not even, then program flow continues along line 310 to decision block 312.
  • the A/D output DM is tested to find out if DM is in the even stored normal range. If DM is in the even stored normal range, then program flow continues along line 314 and 316 to action block 318. Action block 318 provides a wait until the value of M is updated, and then program flow continues along lines 320, 303 to start the process over for the next value of M.
  • Action block 324 reports an error (actuates output 219 in FIG. 3A) , and then program flow continues along lines 326, 316 to action block 318. If DM is in the odd range at decision block 312, then program flow continues along lines 328, 316 to action block 318. If Dm is not in the odd range at decision block 312, then program flow continues along line 330 to action block 324.
  • the arrangements illustrated in FIGS. 3A-3B provide for error checking using only two stored normal ranges.
  • FIG. 4A illustrates a third embodiment of a circuit 400 with a dynamically changing input range and an error output 219. Reference numbers used in
  • Circuit 400 in FIG. 4A comprises a first switch
  • a reference source 213 generates a first reference 402 and also generates a second reference 404 that is different than the first reference 402.
  • a control circuit 216 controls the first switch 406 to couple the first reference 402 to the analog- to-digital converter 208 when an odd-numbered analog input (Al , A3, ...) is selected.
  • the control circuit 216 controls the first switch 406 to couple the second reference 404 to the analog-to-digital converter when an even-numbered analog input (A2 , A4 , ... ) is selected.
  • the switching provided by the first switch 406 shifts the range of the output of the A/D converter 208.
  • the output DM of the A/D converter is a digital word that is scaled to a product of voltage at the analog output AM divided by voltage at the reference input 210 times the count span of the A/D converter. Accordingly, data 215 in the control circuit 216 is stored shifted normal range data.
  • the arrangement in FIG. 4A provides enhanced A/D converter resolution for the lower range while still providing the error detection between adjacent pins of the analog inputs.
  • the circuit 400 of FIG. 4A is similar to the circuit 300 of FIG. 3.
  • FIG. 4B illustrates a simplified flow chart of error checking in the system illustrated in FIG. 4A. Reference numbers used in FIG. 4B that are the same as reference numbers used in FIG. 3B identify the same or similar features. In FIG.
  • FIG. 4B illustrates a fourth embodiment of a circuit 500 with a dynamically changing input range and an error output 219. Reference numbers used in FIG. 5 that are the same as reference numbers used in FIG. 4A identify the same or similar features.
  • a circuit 500 comprises a second switch 502.
  • the A/D converter 208 is provided with differential analog inputs +IN and -IN.
  • the second switch 502 is coupled to the -IN differential input and the analog input AM is coupled to +IN differential input.
  • the control circuit 216 controls the second switch 502 to connect a selected one of the second reference 404 and a common conductor 504 (zero volts) to the -IN differential input.
  • the switches 406 and 502 are operated in synchronization so that both the upper and lower limits of the range of the A/D converter 208 can be shifted. This arrangement allows enhanced error detection while retaining high A/D converter resolution. An odd range input value will produce a maximum count A/D output value DM if input into an even range switch configuration.
  • FIG. 6 illustrates an embodiment of a reference switching circuit 600 that provides a selectable level of reference voltage 602 to a reference input on an A/D converter. Selection of the level is controlled by a control line 604 from a control circuit such as a microcontroller. The control line 604 activates a switch 606 to short out a resistor 608. Resistor 608 is in a resistive voltage divider 614 along with resistors 610, 612. The resistive voltage divider 614 provides a reference voltage on line 616 to a buffer circuit 618.
  • the reference switching circuit 600 can be used in place of the reference 213 and the switch 406 in FIG. 4A, for example.
  • the reference switching circuit 600 is controlled to generate the first reference at a first level when an odd-numbered analog input is selected, and controlled to generate the first reference at a second level when an even-numbered analog input is selected.
  • FIG. 7 is a block diagram showing one example of a transmitter circuit 700 in which circuits and software such as described above in FIGS. 2-6 can be used.
  • feature module electronics 750 is shown coupled to two wire process control loop 718 through a shunt regulator 699 and a loop feedback resistor 701.
  • a series of cascaded voltage regulators 702, 704, 706 couple power from the loop 718 to the feature module electronics 750 and also to sensor module electronics 752.
  • Loop override circuitry 762 serves as an error output and is partially implemented in microcontroller 738 which couples to a digital to analog (D/A) converter 722 and a multiplexed converter circuit 764 that includes an analog-to- digital (A/D) converter, multiplexer and reference as described above in connection with FIGS. 2-5.
  • the multiplexed converter circuit 764 is configured to measure the sense voltage on resistor 701 (sensing loop current) and also senses regulated power supply voltages at nodes 703, 705, 707. The.
  • multiplexed converter circuit 764 also measures a voltage at node 709 which is representative of power supply current from voltage regulator 704.
  • the microcontroller 738 is configured to control the current I through loop 718, and any digital data modulated onto that current, using D/A 722 and shunt regulator 699.
  • the multiplexed converter circuit 764 provides outputs 765 (comparable to outputs 214 in FIGS. 2-5) that represents the various analog voltages that are sensed.
  • the multiplexed converter circuit 764 can also be connected to other voltages or components within transmitter 700.
  • the microcontroller 738 includes a memory 740 which stores normal range data (comparable to data 215, 217 in FIGS 2-5) used to detect errors such as shorted pins or a stuck output bit as described above in connection with FIGS. 2-5. Upon the detection of a short circuit or stuck bit, the microcontroller 738 transmits an alarm signal on line 761 to activate loop override circuitry 762. The current I flowing through loop 718 is then set to a fixed current level. In some embodiments, circuitry within the device can be disconnected or shut off in order to provide enough power to other circuitry to provide a desired output. One technique to provide a loop override is to disconnect the device, or otherwise take the device offline from the process control loop.
  • FIG. 7 also illustrates an optional watch dog circuit 750 coupled to microcontroller 738.
  • the watch dog circuit 750 when used, must be periodically triggered by microcontroller 738. If microcontroller 738 stops triggering watch dog circuit 750, it can be assumed that a failure has occurred. Examples include, but are not limited to, improper program flow, microprocessor or memory failure, clock errors, etc.
  • FIGS. 8A, 8B, 8C illustrate circuits that can be used in analog systems to provide scaling, inversion or level shifting of an analog input.
  • FIG. 8A illustrates a conditioning circuit in which an analog voltage 800 from an analog system is amplified by an amplifier 802 to provide a scaled output 804 which can be coupled to an input of an A/D converter.
  • FIG. 8A illustrates a conditioning circuit in which an analog voltage 800 from an analog system is amplified by an amplifier 802 to provide a scaled output 804 which can be coupled to an input of an A/D converter.
  • FIG. 8B illustrates a conditioning circuit in which an analog voltage 810 from an analog system is scaled down by a factor controlled by a resistive voltage divider to provide a scaled down output 814 that can be coupled to an input of an A/D converter.
  • FIG. 8C illustrates a conditioning circuit in which an analog voltage 820 is coupled to an inverting input 821 of an amplifier 822 via a resistor.
  • a reference voltage 824 is also coupled to the inverting input 821 via a resistor.
  • the arrangement shown in FIG. 8C provides scaling, inversion and level shifting by the selection of resistor values and reference voltage 824 to provide an output 826 that can be coupled to an input of an A/D converter.

Abstract

A circuit (200) includes a multiplexer (204), an analog-to-digital converter (208), and a processor (216) that compares a sequence (DM) of digital outputs from the analog-to-digital converter to a sequence (217) of normal ranges that correspond with the digital outputs in order to provide an error output (219) when one of the digital outputs is outside its normal range.

Description

ANALOG-TO-DIGITAL CONVERTER WITH RANGE ERROR DETECTION BACKGROUND OF THE INVENTION Multiplexed analog-to-digital (A/D) converters have input pins for receiving multiple analog inputs, and provide digital outputs that represent the analog inputs. The digital outputs are fed into a microcontroller which uses the digital outputs to generate a microcontroller output that is a function of the analog inputs. Typically, the A/D converter and microcontroller are part of an industrial process control transmitter and the microcontroller output represents a process variable that is compensated for temperature, power supply voltages, etc., all of which are analog inputs. Various types of malfunctions can occur in the circuitry. One malfunction that can occur is a short between adjacent, input pins of the multiplexer. Another malfunction that can occur is an A/D converter failure that results in one of the digital output bits becoming stuck at either a high level (1) or a low level (0) . When A/D converter systems are used in Safety Instrumented Systems (SIS) , there is a need to identify when such malfunctions occur and provide an error or diagnostic output. A high degree of confidence is needed in the reliability of the A/D converter. A diagnostic output from the microcontroller is needed so that a process control system supported by the A/D converter system is alerted to malfunctions. SUMMARY OF THE INVENTION A circuit comprises a multiplexer. The multiplexer has a select input and a sequence of analog outputs that are selected from a plurality of analog inputs. The circuit also comprises a reference source that provides a first reference. The circuit comprises an analog-to-digital converter. The analog-to-digital converter receives the sequence of analog outputs and the first reference. The analog-to-digital converter provides a sequence of digital outputs. The circuit comprises a control circuit. The control circuit actuates the select input to select the sequence of the analog outputs. The control circuit compares the sequence of digital outputs to a stored sequence of normal ranges that correspond with the digital outputs to provide an error output when at least one of the digital outputs is not in its normal range . BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a PRIOR ART analog-to-digital converter system. FIG. 2A illustrates a first embodiment of a circuit with a dynamically changing input range. FIG. 2B illustrates a first simplified flow chart of a method of error checking in the circuit illustrated in FIG. 2A. FIG. 3A illustrates a second embodiment of a circuit with a dynamically changing input range. FIG. 3B illustrates a second 'simplified flow chart of a method of error checking in the circuit illustrated in FIG. 3A. FIG. 4A illustrates a third embodiment of a circuit with a dynamically changing input range. FIG. 4B illustrates a third simplified flow chart of a method of error checking in the circuit illustrated in FIGS. 4A, 5. FIG. 5 illustrates a fourth embodiment of a circuit with. a dynamically changing input range. FIG. 6 illustrates an embodiment of a reference circuit . FIG. 7 illustrates a block diagram of a transmitter circuit in which circuits and methods such as described above in FIGS. 2-6 can be used. FIGS. 8A, 8B, 8C illustrate circuits that can be used in analog systems to provide scaling, inversion or level shifting of an analog input. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the embodiments illustrated in FIGS. 2-8, a circuit includes a multiplexer (MUX) , an analog-to- digital converter (A/D) and a processor (typically a microcontroller (uC) ) . The processor provides digital output that represents analog inputs. In order to detect malfunctions, the processor compares a sequence of digital outputs from the analog-to- digital converter to a sequence of stored normal ranges that correspond with the digital outputs. The processor provides an error output when one of the digital outputs is outside its normal range. The arrangement provide detection of shorted analog input pins on the multiplexer, stuck bits at the analog-to- digital convert output and other malfunctions. The arrangement is especially useful in process control applications where Safety Instrumented Systems (SIS) standards are in use. FIG. 1 illustrates a PRIOR ART analog-to-digital converter system 100. An analog system 102 provides continuously variable (analog) voltages Al, A2 , A3, ... , AN to a multiplexer 104. Each of the analog voltages Al , A2 , A3, -.., AN has a normal voltage range indicated by vertical ranges of rectangles 1, 2, 3, ..., N at 106. The analog voltages Al , A2 , A3, ... , AN can represent a process variable, a temperature, a voltage, a calibration pot setting and other analog variables. As part of the design process for the analog system 102, the analog voltages Al ,
A2 , A3, ... , AN are scaled so that each analog voltage has a normal range of voltages that is within the input range of an analog-to-digital converter (A/D) 108. The input range of the A/D 108 ranges between zero (common) and a reference input 110 of the A/D 108. As part of the design process for the converter system 100, a reference 112 is selected which provides the desired input range (0 to +REF) to accommodate the normal ranges of all of the analog voltages Al, A2 , A3, ..., AN. Various engineering tradeoffs are made in the design process in an effort to select scaling for each analog input and a reference voltage so that the input range maximum is near the upper limit (+REF) in order to provide high resolution at a digital output 114 of the A/D 108. As a result of these engineering tradeoffs, the ranges of the analog voltage at 106 tend to be all near the upper limit (+REF) and vertically overlapping one another on a voltage scale as illustrated. A digital output 114 of the A/D is coupled to a microcontroller 116. The microcontroller 116 provides a digital output (M) 118 that couples to the Multiplexer (MUX) 104. The multiplexer 104 receives the digital output 118 and selects one output AM to connect to the multiplexer output 120. The multiplexer output 120 couples to an analog input 122 of the A/D 108. The microcontroller 116 increments or steps the digital output M and obtains digital representations at output 114 for each of the relevant analog inputs Al , A2 , A3, ..., AN. The microcontroller 116 calculates desired outputs 124 as a function of the digitized analog inputs Al, A2 , A3, ... AN. Typically, the outputs 124 will represent process variables that are compensated for temperature, power supply voltages, calibration settings and the like that are obtained from the analog system 102. Adjacent input pins on the multiplexer 104 are close together and subject to accidental or intermittent short circuiting by a short 130 during assembly or use of the multiplexer 104 on a printed wiring board. As explained above, analog voltages Al , A2 , A3, ..., AN tend to have voltage ranges that are crowded together and are overlapping. When two adjacent pins are shorted together, the voltage at the two shorted together pins is typically in both of the voltage ranges for the shorted pins, and there is no "out of range" reading to identify the fact that there is a short circuit . Analog voltages that are only slightly different than correct voltages may be converted by the A/D 108 and there will be no indication of the short circuit. One or more of the output 124 will provide inaccurate data, and this inaccurate data can cause a process control system to malfunction without adequate warning. The digital output 114 of the A/D 108 is a digital word 132 that includes a number of bits ranging from a least significant bit (LSB) to a most significant bit (MSB) . The number of bits generally corresponds to the output resolution of the A/D. Each bit is generated by one or more switches internal to the A/D 108. These internal switches are subject to failure, and when a switch fails, typically one bit 134 of the digital word 132 becomes stuck at either a high (1) level or a low (0) level. This malfunction or failure can go unnoticed, particularly when the bit is nearer the least significant bit (LSB) because the analog inputs tend to be in overlapping ranges and will be approximately equally affected by the stuck bit. The outputs 124 provide inaccurate data, and this inaccurate data can cause a process control system to malfunction without adequate warning. The problems with the A/D system 100 are overcome as described below in connection with examples illustrated in FIGS. 2-8. FIG. 2A illustrates a first embodiment of an circuit 200 with a dynamically changing input range and an error output 219. The circuit 200 is typically used to process analog variables in an industrial process variable transmitter such as the transmitter illustrated in FIG. 7, but can be used in a wide variety of other applications using multiplexed analog-to-digital conversion. The circuit 200 receives a plurality of analog inputs Al, A2 , A3, ... AN from an analog system 202. Each analog input has a normal operating range (RANGE 1, RANGE 2, RANGE 3, ... RANGE N) associated with it. The analog system 202 has been specially configured so that each analog input has a normal operating range that is different from the normal operating range of the other remaining analog inputs. In a preferred embodiment, the normal operating ranges of the analog inputs are non-overlapping. In a typical analog system 202, the analog inputs are conditioned by a combination of scaling, inversion or level shifting to provide a unique normal operating range for each analog input A. Examples of conditioning circuits are described below in connection with FIGS. 8A, 8B, 8C. The circuit 200 includes a multiplexer (MUX) 204 that receives the analog inputs Al , A2 , A3, ... AN. The multiplexer 204 has a select input 218 that selects one of the analog inputs Al , A2 , A3, ... AN to connect to a multiplexer output (AM) to provide a sequence of analog outputs 220. In a preferred arrangement, the multiplexer select input 218 is a multibit word and is simply counted up (or down) to sample the analog inputs in numerical order. The multiplexer 204 preferably comprises an integrated circuit analog multiplexer, for example, Analog Devices AD7501 available from Analog Devices, Inc. of Norwood, Massachusetts. The circuit 200 also includes a reference source 212 that provides a first reference voltage to a reference input 210 of an analog-to-digital converter 208. In one preferred arrangement, a separate
• reference (such as a Zener diode or active reference) is provided in circuit 200. In another preferred embodiment, the reference source is simply a lead in circuit 200 that connects to a shared reference (such as a Zener diode or active reference) that is part of the analog system 202. In yet another preferred arrangement, a reference source that is part of a commercial A/D circuit 208 is used. The analog-to-digital converter (A/D) 208 receives the sequence of analog outputs (AM) 220. The A/D 208 has a reference input 210 that receives the first reference voltage from reference 212. The A/D 208 converts the sequence of analog inputs (AM) 220 to a corresponding sequence of digital outputs (DM) 214. The multiplexer 204 presents the sequence of analog outputs (AM) 220 in a numerical sequence, and the sequence of digital outputs (DM) is also presented in a numerical sequence. The individual digital outputs DM can be presented in either a serial or a parallel format, depending on the type of A/D converter that is used. In one preferred embodiment, an Analog Devices AD571 A/D converter is used, for example. A digital output (for each serial or parallel digital output in the sequence) , includes a number of bits ranging from a least significant bit (LSB) to a most significant bit (MSB) as illustrated. The circuit 200 includes a control circuit 216. The control circuit 216 actuates the select input 218 with a numerical sequence that selects the sequence of the analog outputs to be read by the control circuit 216. The control circuit 216 compares the sequence of digital outputs 214 to a stored sequence of normal ranges 217 that correspond with the digital outputs '214 to provide or actuate an error output 219 when at least one of the digital outputs 214 is not in its stored normal range 217. The control circuit 216 preferably comprises a microcontroller, for example, a National Semiconductor COP8SGE728M8. The error checking (normal range checking) runs in the background on the control circuit 216. The control circuit also provides a real time output 221 that represents some useful parameter of the analog system 202. In a typical transmitter application, the parameter of interest is a compensated pressure, temperature, or flow that is displayed or used for process control . The arrangement illustrated in FIG. 2A provides for checking errors due to short circuits between analog inputs Al , A2 , A3, ... AN which all have unique, non-overlapping normal ranges. When two analog inputs are shorted together by short 230, the resulting voltage can only be in a single one of the normal ranges and cannot lie in two different ranges because the ranges are non-overlapping. This results in at least one, and sometimes both of the shorted analog inputs being detected as outside of normal range. Short-circuiting of two of the plurality of analog inputs causes at least one of the digital outputs to exceed its corresponding normal range. The arrangement illustrated in FIG. 2A also provides for checking errors due to one of the output bits of the A/D 208 being stuck. A bit is considered stuck when the bit remains at one logic state (0 or 1) continuously, or in other words is shorted to one of the power supply rails. When there is a stuck bit, because the analog inputs are each in a different range , the effect of the stuck bit is different percentage for each output in the sequence, and there is a high probability that the control circuit 216 will detect that one of the digital outputs is out of its corresponding stored normal range. The sequence of digital outputs comprises digital words with a series of bits, and sticking of one of the bits causes at least one of the digital outputs to exceed its corresponding normal range. FIG. 2B illustrates a simplified flow chart example of background error checking in the system illustrated in FIG. 2A. Program flow starts at START 250 and proceeds to compare the current output DM (i.e., the output D when the select input is M) to the stored normal range data for range M at decision block 252. If the output DM is in the normal range, then program flow continues along lines 254, 256 to function block 258. At function block 258, the background program waits for the select input M to change to the next number. If the output DM is not in the normal range at decision block 252, then program flow continues along line 260 to function block 262 which actuates the error output 219 (FIG. 2A) and then continues along lines 264, 256 to the function block 258. When the select input M changes, then program flow starts again and continues along lines 266 back to the decision block 252. The arrangements illustrated in FIGS. 2A-2B have the advantage of a high certainty of detecting stuck bits and shorted pins. The problem of providing inaccurate data to a digital output is solved by providing an error output that reliably warns of stuck bits and shorted input pins. FIG. 3A illustrates a second embodiment of a circuit 300 with a dynamically changing input range and an error output 219. Reference numbers used in FIG. 3A that are the same as reference numbers used in FIG. 2A designate the same or similar features. The circuit 300 receives a plurality of analog inputs Al, A2 , A3, ... AN from an analog system 302. Each analog input has a normal operating range (RANGE 1, RANGE 2, RANGE 3, ... RANGE N) associated with it. The analog system 302 has been specially configured so that odd-numbered analog inputs (Al, A3 , ... ) are in an odd normal operating range, and even-numbered analog inputs (A2 , A4 , ...) are in an even normal operating range. In a preferred embodiment, the odd and even operating ranges of the analog inputs are non-overlapping and each of the two operating ranges extends over about one half of the input range of the A/D 208. In another preferred arrangement, there is a small voltage spacing between the even and odd ranges to increase the likelihood of detecting errors. In a typical analog system 302, the analog inputs are conditioned by a combination of scaling, inversion or level shifting so that alternately numbered analog inputs are in alternating normal operating ranges. Shorting between adjacent pins (one even, one odd) has a high probability of pulling one of the adjacent inputs outside of its normal range. A stuck bit at the output 214 produces errors that differ typically by a factor of two between even and odd outputs and the errors are thus easily recognized. Examples of conditioning circuits that can be used to scale, invert or level shift analog voltages are described below in connection with FIGS. 8A, 8B, 8C. In circuit 300, the stored normal range data comprises even normal range data and odd normal range data. In other respects, the circuit 300 is similar to the circuit 200. FIG. 3B illustrates an example of a simplified flow chart of background error checking useful in the system illustrated in FIG. 3A. Program flow begins at START 301 and continues along line 303 to decision block 304. At decision block 304, the current select input number "M" is tested to find out if it is even. If the input number "M" is even, then program flow continues along line 306 to decision block 308. If the number "M" is not even, then program flow continues along line 310 to decision block 312. At decision block 308, the A/D output DM is tested to find out if DM is in the even stored normal range. If DM is in the even stored normal range, then program flow continues along line 314 and 316 to action block 318. Action block 318 provides a wait until the value of M is updated, and then program flow continues along lines 320, 303 to start the process over for the next value of M. If DM is not in the even stored normal range at decision block 308, then program flow continues along line 322 to action block 324. Action block 324 reports an error (actuates output 219 in FIG. 3A) , and then program flow continues along lines 326, 316 to action block 318. If DM is in the odd range at decision block 312, then program flow continues along lines 328, 316 to action block 318. If Dm is not in the odd range at decision block 312, then program flow continues along line 330 to action block 324. The arrangements illustrated in FIGS. 3A-3B provide for error checking using only two stored normal ranges. A single analog voltage, such as a power supply rail can be resistively scaled to provide one analog input in the upper (odd) range and another analog input in the lower (even) range. The control circuit 216 can compare the two readings and test for a constant ratio of resistive scaling as an additional error check. FIG. 4A illustrates a third embodiment of a circuit 400 with a dynamically changing input range and an error output 219. Reference numbers used in
FIG. 4A that are the same as reference numbers used in FIG. 3A identify the same or similar features. Circuit 400 in FIG. 4A comprises a first switch
406 that couples to a reference input 210 on the A/D
208. A reference source 213 generates a first reference 402 and also generates a second reference 404 that is different than the first reference 402. A control circuit 216 controls the first switch 406 to couple the first reference 402 to the analog- to-digital converter 208 when an odd-numbered analog input (Al , A3, ...) is selected. The control circuit 216 controls the first switch 406 to couple the second reference 404 to the analog-to-digital converter when an even-numbered analog input (A2 , A4 , ... ) is selected. The switching provided by the first switch 406 shifts the range of the output of the A/D converter 208. In simple terms, the output DM of the A/D converter is a digital word that is scaled to a product of voltage at the analog output AM divided by voltage at the reference input 210 times the count span of the A/D converter. Accordingly, data 215 in the control circuit 216 is stored shifted normal range data. The arrangement in FIG. 4A provides enhanced A/D converter resolution for the lower range while still providing the error detection between adjacent pins of the analog inputs. In other respects, the circuit 400 of FIG. 4A is similar to the circuit 300 of FIG. 3. FIG. 4B illustrates a simplified flow chart of error checking in the system illustrated in FIG. 4A. Reference numbers used in FIG. 4B that are the same as reference numbers used in FIG. 3B identify the same or similar features. In FIG. 4B, decision blocks 309, 313 test for DM to be in shifted ranges rather than ranges (FIG. 3B) . In other respects, the flow chart in FIG. 4B is similar to the flow chart if FIG. 3B. The arrangements illustrated in FIGS. 4A-4B provide for analog inputs in both the odd and even ranges to use a full output range of the A/D converter 208 because the reference input shifts to boost the lower valued analog inputs in the lower (even) range. FIG. 5 illustrates a fourth embodiment of a circuit 500 with a dynamically changing input range and an error output 219. Reference numbers used in FIG. 5 that are the same as reference numbers used in FIG. 4A identify the same or similar features. In FIG. 5, a circuit 500 comprises a second switch 502. The A/D converter 208 is provided with differential analog inputs +IN and -IN. The second switch 502 is coupled to the -IN differential input and the analog input AM is coupled to +IN differential input. The control circuit 216 controls the second switch 502 to connect a selected one of the second reference 404 and a common conductor 504 (zero volts) to the -IN differential input. The switches 406 and 502 are operated in synchronization so that both the upper and lower limits of the range of the A/D converter 208 can be shifted. This arrangement allows enhanced error detection while retaining high A/D converter resolution. An odd range input value will produce a maximum count A/D output value DM if input into an even range switch configuration. Likewise, an even range input value will produce a minimum count A/D input value DM if input into an odd range switch configuration. In other respects, the circuit 500 in FIG. 5 is similar to the circuit 400 in FIG. 4A. FIG. 6 illustrates an embodiment of a reference switching circuit 600 that provides a selectable level of reference voltage 602 to a reference input on an A/D converter. Selection of the level is controlled by a control line 604 from a control circuit such as a microcontroller. The control line 604 activates a switch 606 to short out a resistor 608. Resistor 608 is in a resistive voltage divider 614 along with resistors 610, 612. The resistive voltage divider 614 provides a reference voltage on line 616 to a buffer circuit 618. The reference switching circuit 600 can be used in place of the reference 213 and the switch 406 in FIG. 4A, for example. The reference switching circuit 600 is controlled to generate the first reference at a first level when an odd-numbered analog input is selected, and controlled to generate the first reference at a second level when an even-numbered analog input is selected. FIG. 7 is a block diagram showing one example of a transmitter circuit 700 in which circuits and software such as described above in FIGS. 2-6 can be used. In FIG. 7, feature module electronics 750 is shown coupled to two wire process control loop 718 through a shunt regulator 699 and a loop feedback resistor 701. A series of cascaded voltage regulators 702, 704, 706 couple power from the loop 718 to the feature module electronics 750 and also to sensor module electronics 752. Sensor module electronics 752 is also shown coupled to a process variable through a process variable sensor 712. An optional output display 714 is also shown. Loop override circuitry 762 serves as an error output and is partially implemented in microcontroller 738 which couples to a digital to analog (D/A) converter 722 and a multiplexed converter circuit 764 that includes an analog-to- digital (A/D) converter, multiplexer and reference as described above in connection with FIGS. 2-5. The multiplexed converter circuit 764 is configured to measure the sense voltage on resistor 701 (sensing loop current) and also senses regulated power supply voltages at nodes 703, 705, 707. The. multiplexed converter circuit 764 also measures a voltage at node 709 which is representative of power supply current from voltage regulator 704. In operation, the microcontroller 738 is configured to control the current I through loop 718, and any digital data modulated onto that current, using D/A 722 and shunt regulator 699. The multiplexed converter circuit 764 provides outputs 765 (comparable to outputs 214 in FIGS. 2-5) that represents the various analog voltages that are sensed. The multiplexed converter circuit 764 can also be connected to other voltages or components within transmitter 700. The microcontroller 738 includes a memory 740 which stores normal range data (comparable to data 215, 217 in FIGS 2-5) used to detect errors such as shorted pins or a stuck output bit as described above in connection with FIGS. 2-5. Upon the detection of a short circuit or stuck bit, the microcontroller 738 transmits an alarm signal on line 761 to activate loop override circuitry 762. The current I flowing through loop 718 is then set to a fixed current level. In some embodiments, circuitry within the device can be disconnected or shut off in order to provide enough power to other circuitry to provide a desired output. One technique to provide a loop override is to disconnect the device, or otherwise take the device offline from the process control loop. The change in loop current indicates a failure in the transmitter 700 to the loop 718 and this can be used by a control system connected to the loop to take action to shut down a controlled process using a Safety Instrumented System (SIS) . FIG. 7 also illustrates an optional watch dog circuit 750 coupled to microcontroller 738. The watch dog circuit 750, when used, must be periodically triggered by microcontroller 738. If microcontroller 738 stops triggering watch dog circuit 750, it can be assumed that a failure has occurred. Examples include, but are not limited to, improper program flow, microprocessor or memory failure, clock errors, etc. If watch dog circuit 750 is not triggered, watch dog circuit 750 sends a signal to loop override circuitry 762 to cause loop override circuitry 762 to drive an alarm current level on the process loop 718. FIGS. 8A, 8B, 8C illustrate circuits that can be used in analog systems to provide scaling, inversion or level shifting of an analog input. FIG. 8A illustrates a conditioning circuit in which an analog voltage 800 from an analog system is amplified by an amplifier 802 to provide a scaled output 804 which can be coupled to an input of an A/D converter. FIG. 8B illustrates a conditioning circuit in which an analog voltage 810 from an analog system is scaled down by a factor controlled by a resistive voltage divider to provide a scaled down output 814 that can be coupled to an input of an A/D converter. FIG. 8C illustrates a conditioning circuit in which an analog voltage 820 is coupled to an inverting input 821 of an amplifier 822 via a resistor. A reference voltage 824 is also coupled to the inverting input 821 via a resistor. The arrangement shown in FIG. 8C provides scaling, inversion and level shifting by the selection of resistor values and reference voltage 824 to provide an output 826 that can be coupled to an input of an A/D converter. Features described in connection with one embodiment can be appropriately applied to other embodiments. Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the scope of the invention.

Claims

WHAT IS CLAIMED IS:
1. A circuit, comprising: a multiplexer having a select input and a sequence of analog outputs that are selected from a plurality of analog inputs; a reference source providing a first reference; an analog-to-digital converter receiving the sequence of analog outputs and the first reference, and providing a sequence of digital outputs; and a control circuit actuating the select input to select the sequence of the analog outputs, the control circuit comparing the sequence of digital outputs to a stored sequence of normal ranges that correspond with the digital outputs to provide an error output when at least one of the digital outputs is not in its normal range.
2. The circuit of Claim 1 wherein at least two of the normal ranges are non-overlapping.
3. The circuit of Claim 2 wherein short-circuiting of two of the plurality of analog inputs causes at least one of the digital outputs to exceed its corresponding normal range .
4. The circuit of Claim 2 wherein the sequence of digital outputs comprises digital words with a series of bits, and wherein a sticking of one of the bits causes at least one of the digital outputs to exceed its corresponding normal range.
5. The circuit of Claim 1, wherein each normal range is different and does not overlap another normal range .
6. The circuit of Claim 1, wherein: the normal ranges comprise an odd range and an even range, and the plurality of analog inputs are connected to the multiplexer in a numbered sequence such that odd-numbered analog inputs generate digital outputs that are in the odd range and even-numbered analog inputs generate digital outputs that are in the even range.
7. The circuit of Claim 6, further comprising: a first switch; wherein the reference source generates a second reference that is different than the first reference; and wherein the control circuit controls the first switch to couple the first reference to the analog-to-digital converter when an odd- numbered analog input is selected, and controls the first switch to couple the second reference to the analog-to-digital converter when an even-numbered analog input is selected.
8. The circuit of Claim 7, further comprising: a second switch; and wherein the analog-to-digital converter comprises first and second differential inputs, the analog output is connected to the first differential input; and the control circuit controls the second switch to connect a selected one of the second reference and a common conductor to the second differential input.
9. The circuit of Claim 1 wherein the control circuit controls the reference source to generates the first reference at a first level when an odd-numbered analog input is selected, and to generate the first reference at a second level when an even-numbered analog input is selected.
10. A method of detecting an error, comprising: generating a sequence of analog outputs that are selected from a plurality of analog inputs as a function of a select input; providing a first reference; receiving the sequence of analog outputs and the first reference, and providing a sequence of digital outputs that represent the sequence of analog outputs; and actuating the select input to select the sequence of the analog outputs; and comparing the sequence of digital outputs to a stored sequence of normal ranges that correspond with the digital outputs to provide an error output when at least one of the digital outputs is not in its normal range .
11. The method of Claim 10 wherein at least two of the normal ranges do not overlap one another.
12. The method of Claim 11 wherein at least one of the analog inputs exceeds its corresponding normal range when two of the plurality of analog inputs short circuit to one another.
13. The method of Claim 11 wherein at least one of the digital outputs exceeds its corresponding normal range when one output bit in the digital outputs sticks .
14. The method of Claim 10, wherein each normal range differs from the other normal ranges and does not overlap another normal range.
15. The method of Claim 10, further comprising: providing the normal ranges as an odd range and an even range, and connecting the plurality of analog inputs to a multiplexer in a numbered sequence such that odd-numbered analog inputs generate digital outputs that are in the odd range and even-numbered analog inputs generate digital outputs that are in the even range.
16. The method of Claim 15, further comprising: providing a first switch; generating a second reference that is different than the first reference; and controlling the first switch to couple the first reference to an analog-to-digital converter when an odd-numbered analog input is selected, and controlling the first switch to couple the second reference to the analog-to-digital converter when an even- numbered analog input is selected.
17. The method of Claim 16, further comprising: providing a second switch; providing first and second differential inputs on the analog-to-digital converter, connecting the analog output to the first differential input; and controlling the second switch to connect a selected one of the second reference and a common conductor to the second differential input .
18. The method of Claim 10, further comprising: controlling a reference source to generates the first reference at a first level when an odd-numbered analog input is selected, and controlling the reference source to generate the first reference at a second level when an even-numbered analog input is selected.
19. A circuit, comprising: a multiplexer having a select input and a sequence of analog outputs that are selected from a plurality of analog inputs; a reference source providing a first reference; an analog-to-digital converter receiving the sequence of analog outputs and the first reference, and providing a sequence of digital outputs; and means for actuating the select input to select the sequence of the analog outputs, and for comparing the sequence of digital outputs to a stored sequence of normal ranges that correspond with the digital outputs to provide an error output when at least one of the digital outputs is not in its normal range .
20. The circuit of Claim 19 wherein at least two of the normal ranges are non-overlapping .
21. The circuit of Claim 20 wherein short-circuiting of two of the plurality of analog inputs causes at least one of the digital outputs to exceed its corresponding normal range .
22. The circuit of Claim 20 wherein the sequence of digital outputs comprises digital words with a series of bits, and wherein a sticking of one of the bits causes at least one of the digital outputs to exceed its corresponding normal range.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009040216A2 (en) * 2007-09-24 2009-04-02 Continental Automotive Gmbh Vehicle control unit having a microcontroller the supply voltage of which is monitored and associated method
CZ301839B6 (en) * 2009-04-01 2010-07-07 Ceské vysoké ucení technické v Praze Fakulta elektrotechnická Circuit arrangement for testing analog-to-digital converters

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10215405A1 (en) * 2002-04-08 2003-10-16 Bosch Gmbh Robert Method and device for testing the function of an analog-digital converter and analog-digital converter
JP4152676B2 (en) * 2002-06-13 2008-09-17 株式会社アドバンテスト Differential voltage measuring equipment, semiconductor testing equipment
US7271646B2 (en) * 2002-09-30 2007-09-18 Magnetrol International, Inc. Loop powered process control instrument power supply
US8180466B2 (en) * 2003-11-21 2012-05-15 Rosemount Inc. Process device with supervisory overlayer
US7464721B2 (en) * 2004-06-14 2008-12-16 Rosemount Inc. Process equipment validation
CN101156119B (en) * 2005-04-04 2011-04-13 费希尔-罗斯蒙德系统公司 Diagnostics in industrial process control system
US7613974B2 (en) * 2006-03-24 2009-11-03 Ics Triplex Technology Limited Fault detection method and apparatus
US7729098B2 (en) 2006-03-24 2010-06-01 Ics Triplex Technology Limited Overload protection method
US7476891B2 (en) * 2006-03-24 2009-01-13 Ics Triplex Technology, Ltd. Fault detection method and apparatus
US7747405B2 (en) * 2006-03-24 2010-06-29 Ics Triplex Technology Ltd. Line frequency synchronization
DE602006013783D1 (en) * 2006-03-24 2010-06-02 Ics Triplex Technology Ltd Mains frequency synchronization
US7688560B2 (en) 2006-03-24 2010-03-30 Ics Triplex Technology Limited Overload protection method
US8166362B2 (en) * 2006-03-24 2012-04-24 Rockwell Automation Limited Fault detection method and apparatus for analog to digital converter circuits
US7504975B2 (en) * 2006-03-24 2009-03-17 Ics Triplex Technology Limited Method and apparatus for output current control
US8032234B2 (en) * 2006-05-16 2011-10-04 Rosemount Inc. Diagnostics in process control and monitoring systems
JP4661718B2 (en) * 2006-07-25 2011-03-30 株式会社デンソー A / D converter
US7463178B2 (en) * 2007-01-16 2008-12-09 Moore Gary W Reconfigurable signal processor for raw data patterns
US7710303B2 (en) * 2007-04-17 2010-05-04 Microchip Technology Incorporated Analog-to-digital converter offset and gain calibration using internal voltage references
US8234298B2 (en) * 2007-07-25 2012-07-31 International Business Machines Corporation System and method for determining driving factor in a data cube
US7826991B2 (en) * 2007-07-25 2010-11-02 Rosemount Inc. Temperature-averaging field device compensation
US7796067B2 (en) * 2008-04-08 2010-09-14 Standard Microsystems Corporation Curvature correction methodology
JP4801180B2 (en) * 2009-03-06 2011-10-26 株式会社日立製作所 Multichannel analog input / output circuit failure diagnosis apparatus and failure diagnosis method
CN101674087B (en) * 2009-09-27 2012-09-05 电子科技大学 Method for obtaining channel mismatching error of time alternative ADC system
DE102010002470A1 (en) * 2010-03-01 2011-09-01 Robert Bosch Gmbh Method for detecting error in flash analog to digital converter utilized for converting analog signals into digital numerical values, involves outputting digital useful signal by converter, and comparing useful signal with comparison signal
US9479188B1 (en) * 2010-05-28 2016-10-25 Maxim Integrated Products, Inc. Programmable multichannel signal selector
DE102010029693A1 (en) * 2010-06-04 2011-12-08 Robert Bosch Gmbh Circuit arrangement for detecting a fault of a converter
US10145882B2 (en) * 2010-09-24 2018-12-04 Infineon Technologies Ag Sensor self-diagnostics using multiple signal paths
US9346441B2 (en) * 2010-09-24 2016-05-24 Infineon Technologies Ag Sensor self-diagnostics using multiple signal paths
US8378872B2 (en) 2011-03-31 2013-02-19 Rosemount Inc. Dynamically adjusted A/D resolution
TWI463153B (en) * 2012-03-30 2014-12-01 Atomic Energy Council Triple-redundant failure auto-detector of analog output module
EP2887079A1 (en) * 2013-12-20 2015-06-24 Electrolux Appliances Aktiebolag Electronic system and method for testing capacitive circuit lines
KR101555498B1 (en) * 2013-12-30 2015-09-24 주식회사 효성 Power supply for high voltage direct current controller
US9436194B1 (en) * 2014-03-06 2016-09-06 Silego Technology, Inc. Power sensing
US10069414B2 (en) 2015-04-01 2018-09-04 Infineon Technologies Austria Ag Switching voltage regulator input voltage and current sensing
US10402251B2 (en) 2015-07-24 2019-09-03 Nxp Usa, Inc. DMA controller for a data processing system, a data processing system and a method of operating a DMA controller
US10367612B2 (en) 2015-09-30 2019-07-30 Rosemount Inc. Process variable transmitter with self-learning loop diagnostics
JP6436105B2 (en) * 2016-01-12 2018-12-12 トヨタ自動車株式会社 Abnormality diagnosis device for A / D converter
JP6739235B2 (en) * 2016-05-26 2020-08-12 ローム株式会社 Coulomb counter circuit, electronic device
EP3465239B1 (en) 2016-06-01 2020-05-20 Signify Holding B.V. Error detection on integrated circuit input/output pins
CN106126363B (en) * 2016-06-20 2019-04-16 芯海科技(深圳)股份有限公司 A kind of verification method of register
US10389242B2 (en) 2017-02-01 2019-08-20 Infineon Technologies Austria Ag Voltage and current sensing calibration for switching voltage regulators
US10224812B1 (en) * 2017-10-13 2019-03-05 Infineon Technologies Austria Ag Sensing network mismatch compensation for switching voltage regulator with input voltage and current sensing
US11206036B2 (en) * 2018-12-11 2021-12-21 Texas Instruments Incorporated Integrated self-test mechanism for an analog-to-digital converter, a reference voltage source, a low dropout regulator, or a power supply
CN110113050B (en) * 2019-05-05 2021-07-06 电子科技大学 Mismatch error correction method applied to successive approximation analog-to-digital converter
JP7243485B2 (en) * 2019-06-27 2023-03-22 セイコーエプソン株式会社 Physical quantity detection circuit, physical quantity sensor, electronic device, moving object, and failure diagnosis method for physical quantity sensor
US11402422B2 (en) 2020-04-15 2022-08-02 Haier Us Appliance Solutions, Inc. Methods for detecting sensor faults in a consumer appliance
US20230246652A1 (en) * 2022-01-31 2023-08-03 Analog Devices, Inc. Adc with precision reference power saving mode

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57196619A (en) * 1981-05-29 1982-12-02 Hitachi Ltd Failure diagnostic system for analog-to-digital converter
GB2317969A (en) * 1996-10-04 1998-04-08 Bosch Gmbh Robert Monitoring the measured data acquisistion in an engine control unit
US6396426B1 (en) * 1998-10-05 2002-05-28 Texas Instruments Incorporated Embedded mechanism offering real-time self failure detection for an analog to digital converter
US6492921B1 (en) * 1999-03-24 2002-12-10 Matsushita Electric Industrial Co., Ltd. Device for clamping multiple signals

Family Cites Families (117)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3096434A (en) 1961-11-28 1963-07-02 Daniel Orifice Fitting Company Multiple integration flow computer
US3404264A (en) 1965-07-19 1968-10-01 American Meter Co Telemetering system for determining rate of flow
US3468164A (en) 1966-08-26 1969-09-23 Westinghouse Electric Corp Open thermocouple detection apparatus
GB1224904A (en) 1968-08-09 1971-03-10 John Stewart Simpson Stewart Improvements in and relating to electromedical apparatus
US3590370A (en) 1969-04-09 1971-06-29 Leeds & Northrup Co Method and apparatus for detecting the open-circuit condition of a thermocouple by sending a pulse through the thermocouple and a reactive element in series
US3701280A (en) 1970-03-18 1972-10-31 Daniel Ind Inc Method and apparatus for determining the supercompressibility factor of natural gas
US3691842A (en) 1970-09-08 1972-09-19 Beckman Instruments Inc Differential pressure transducer
US3688190A (en) 1970-09-25 1972-08-29 Beckman Instruments Inc Differential capacitance circuitry for differential pressure measuring instruments
US3849637A (en) 1973-05-22 1974-11-19 Combustion Eng Reactor megawatt demand setter
US3855858A (en) 1973-08-01 1974-12-24 V Cushing Self synchronous noise rejection circuit for fluid velocity meter
USRE29383E (en) 1974-01-10 1977-09-06 Process Systems, Inc. Digital fluid flow rate measurement or control system
US3948098A (en) * 1974-04-24 1976-04-06 The Foxboro Company Vortex flow meter transmitter including piezo-electric sensor
US3952759A (en) 1974-08-14 1976-04-27 M & J Valve Company Liquid line break control system and method
US3973184A (en) 1975-01-27 1976-08-03 Leeds & Northrup Company Thermocouple circuit detector for simultaneous analog trend recording and analog to digital conversion
US4058975A (en) 1975-12-08 1977-11-22 General Electric Company Gas turbine temperature sensor validation apparatus and method
US4099413A (en) 1976-06-25 1978-07-11 Yokogawa Electric Works, Ltd. Thermal noise thermometer
US4102199A (en) 1976-08-26 1978-07-25 Megasystems, Inc. RTD measurement system
US4122719A (en) 1977-07-08 1978-10-31 Environmental Systems Corporation System for accurate measurement of temperature
JPS54111050A (en) 1978-02-21 1979-08-31 Toyota Motor Corp Automatic speed changer
US4250490A (en) 1979-01-19 1981-02-10 Rosemount Inc. Two wire transmitter for converting a varying signal from a remote reactance sensor to a DC current signal
US4249164A (en) 1979-05-14 1981-02-03 Tivy Vincent V Flow meter
US4279013A (en) 1979-10-31 1981-07-14 The Valeron Corporation Machine process controller
US4337516A (en) 1980-06-26 1982-06-29 United Technologies Corporation Sensor fault detection by activity monitoring
US4417312A (en) 1981-06-08 1983-11-22 Worcester Controls Corporation Electronic controller for valve actuators
US4459858A (en) * 1981-09-18 1984-07-17 Marsh-Mcbirney, Inc. Flow meter having an electromagnetic sensor probe
US4399824A (en) 1981-10-05 1983-08-23 Air-Shields, Inc. Apparatus for detecting probe dislodgement
US4463612A (en) * 1981-12-10 1984-08-07 The Babcock & Wilcox Company Electronic circuit using digital techniques for vortex shedding flowmeter signal processing
US4571689A (en) 1982-10-20 1986-02-18 The United States Of America As Represented By The Secretary Of The Air Force Multiple thermocouple testing device
US4668473A (en) 1983-04-25 1987-05-26 The Babcock & Wilcox Company Control system for ethylene polymerization reactor
US4530234A (en) 1983-06-30 1985-07-23 Mobil Oil Corporation Method and system for measuring properties of fluids
JPH0619666B2 (en) 1983-06-30 1994-03-16 富士通株式会社 Failure diagnosis processing method
US4540468A (en) 1983-09-26 1985-09-10 Board Of Trustees Of The University Of Maine Method for determining the degree of completion and pulp yield
US4707796A (en) 1983-10-19 1987-11-17 Calabro Salvatore R Reliability and maintainability indicator
US4686638A (en) 1983-11-04 1987-08-11 Kabushiki Kaisha Kosumo Keiki Leakage inspection method with object type compensation
EP0158192B1 (en) 1984-03-31 1991-06-05 B a r m a g AG Measurement data acquisition method for a plurality of measurement points
US4649515A (en) 1984-04-30 1987-03-10 Westinghouse Electric Corp. Methods and apparatus for system fault diagnosis and control
US4517468A (en) 1984-04-30 1985-05-14 Westinghouse Electric Corp. Diagnostic system and method
US4642782A (en) 1984-07-31 1987-02-10 Westinghouse Electric Corp. Rule based diagnostic system with dynamic alteration capability
US4644479A (en) 1984-07-31 1987-02-17 Westinghouse Electric Corp. Diagnostic apparatus
US4630265A (en) 1984-09-26 1986-12-16 General Electric Company Method and apparatus for selecting for use between data buses in a redundant bus communication system
JPH0734162B2 (en) 1985-02-06 1995-04-12 株式会社日立製作所 Analogical control method
US4758308A (en) 1985-03-05 1988-07-19 Carr Wayne F System for monitoring contaminants with a detector in a paper pulp stream
US4807151A (en) 1986-04-11 1989-02-21 Purdue Research Foundation Electrical technique for correcting bridge type mass air flow rate sensor errors resulting from ambient temperature variations
GB8611360D0 (en) 1986-05-09 1986-06-18 Eaton Williams Raymond H Air condition monitor unit
US4736367A (en) 1986-12-22 1988-04-05 Chrysler Motors Corporation Smart control and sensor devices single wire bus multiplex system
US5005142A (en) 1987-01-30 1991-04-02 Westinghouse Electric Corp. Smart sensor system for diagnostic monitoring
US4736763A (en) 1987-02-26 1988-04-12 Britton George L Automatic device for the detection and shutoff of unwanted liquid flow in pipes
ATE85124T1 (en) 1987-04-02 1993-02-15 Eftag Entstaubung Foerdertech CIRCUIT ARRANGEMENT FOR EVALUATION OF THE SIGNALS GENERATED BY A SEMICONDUCTOR GAS SENSOR.
US4988990A (en) 1989-05-09 1991-01-29 Rosemount Inc. Dual master implied token communication system
US5122794A (en) 1987-08-11 1992-06-16 Rosemount Inc. Dual master implied token communication system
US4873655A (en) 1987-08-21 1989-10-10 Board Of Regents, The University Of Texas System Sensor conditioning method and apparatus
US4907167A (en) 1987-09-30 1990-03-06 E. I. Du Pont De Nemours And Company Process control system with action logging
US4804958A (en) * 1987-10-09 1989-02-14 Rosemount Inc. Two-wire transmitter with threshold detection circuit
US4818994A (en) 1987-10-22 1989-04-04 Rosemount Inc. Transmitter with internal serial bus
US4831564A (en) 1987-10-22 1989-05-16 Suga Test Instruments Co., Ltd. Apparatus for estimating and displaying remainder of lifetime of xenon lamps
US5274572A (en) 1987-12-02 1993-12-28 Schlumberger Technology Corporation Method and apparatus for knowledge-based signal monitoring and analysis
US5193143A (en) 1988-01-12 1993-03-09 Honeywell Inc. Problem state monitoring
US4841286A (en) 1988-02-08 1989-06-20 Honeywell Inc. Apparatus and method for detection of an open thermocouple in a process control network
US4924418A (en) 1988-02-10 1990-05-08 Dickey-John Corporation Universal monitor
JPH0774961B2 (en) 1988-04-07 1995-08-09 株式会社日立製作所 Auto tuning PID controller
US4926364A (en) 1988-07-25 1990-05-15 Westinghouse Electric Corp. Method and apparatus for determining weighted average of process variable
US4964125A (en) 1988-08-19 1990-10-16 Hughes Aircraft Company Method and apparatus for diagnosing faults
US5197328A (en) 1988-08-25 1993-03-30 Fisher Controls International, Inc. Diagnostic apparatus and method for fluid control valves
US5099436A (en) 1988-11-03 1992-03-24 Allied-Signal Inc. Methods and apparatus for performing system fault diagnosis
US5067099A (en) 1988-11-03 1991-11-19 Allied-Signal Inc. Methods and apparatus for monitoring system performance
EP0369489A3 (en) 1988-11-18 1991-11-27 Omron Corporation Sensor controller system
US5025344A (en) * 1988-11-30 1991-06-18 Carnegie Mellon University Built-in current testing of integrated circuits
JP2714091B2 (en) 1989-01-09 1998-02-16 株式会社日立製作所 Field instrument
NL8900050A (en) * 1989-01-10 1990-08-01 Philips Nv DEVICE FOR MEASURING A CURRENT CURRENT OF AN INTEGRATED MONOLITIC DIGITAL CIRCUIT, INTEGRATED MONOLITIC DIGITAL CIRCUIT PROVIDED WITH SUCH A DEVICE AND TESTING EQUIPMENT PROVIDED WITH SUCH A DEVICE.
US5098197A (en) 1989-01-30 1992-03-24 The United States Of America As Represented By The United States Department Of Energy Optical Johnson noise thermometry
US5089979A (en) 1989-02-08 1992-02-18 Basic Measuring Instruments Apparatus for digital calibration of detachable transducers
US5081598A (en) 1989-02-21 1992-01-14 Westinghouse Electric Corp. Method for associating text in automatic diagnostic system to produce recommended actions automatically
US4939753A (en) 1989-02-24 1990-07-03 Rosemount Inc. Time synchronization of control networks
US5089984A (en) 1989-05-15 1992-02-18 Allen-Bradley Company, Inc. Adaptive alarm controller changes multiple inputs to industrial controller in order for state word to conform with stored state word
US4934196A (en) 1989-06-02 1990-06-19 Micro Motion, Inc. Coriolis mass flow rate meter having a substantially increased noise immunity
US5269311A (en) 1989-08-29 1993-12-14 Abbott Laboratories Method for compensating errors in a pressure transducer
JPH03166601A (en) 1989-11-27 1991-07-18 Hitachi Ltd Symbolizing device and process controller and control supporting device using the symbolizing device
US5019760A (en) 1989-12-07 1991-05-28 Electric Power Research Institute Thermal life indicator
US5111531A (en) 1990-01-08 1992-05-05 Automation Technology, Inc. Process control using neural network
US5235527A (en) 1990-02-09 1993-08-10 Toyota Jidosha Kabushiki Kaisha Method for diagnosing abnormality of sensor
US5134574A (en) 1990-02-27 1992-07-28 The Foxboro Company Performance control apparatus and method in a processing plant
US5122976A (en) 1990-03-12 1992-06-16 Westinghouse Electric Corp. Method and apparatus for remotely controlling sensor processing algorithms to expert sensor diagnoses
US5053815A (en) 1990-04-09 1991-10-01 Eastman Kodak Company Reproduction apparatus having real time statistical process control
US5150289A (en) 1990-07-30 1992-09-22 The Foxboro Company Method and apparatus for process control
US5224203A (en) 1990-08-03 1993-06-29 E. I. Du Pont De Nemours & Co., Inc. On-line process control neural network using data pointers
US5197114A (en) 1990-08-03 1993-03-23 E. I. Du Pont De Nemours & Co., Inc. Computer neural network regulatory process control system and method
US5212765A (en) 1990-08-03 1993-05-18 E. I. Du Pont De Nemours & Co., Inc. On-line training neural network system for process control
US5167009A (en) 1990-08-03 1992-11-24 E. I. Du Pont De Nemours & Co. (Inc.) On-line process control neural network using data pointers
US5142612A (en) 1990-08-03 1992-08-25 E. I. Du Pont De Nemours & Co. (Inc.) Computer neural network supervisory process control system and method
US5121467A (en) 1990-08-03 1992-06-09 E.I. Du Pont De Nemours & Co., Inc. Neural network/expert system process control system and method
US5175678A (en) 1990-08-15 1992-12-29 Elsag International B.V. Method and procedure for neural control of dynamic processes
US5130936A (en) 1990-09-14 1992-07-14 Arinc Research Corporation Method and apparatus for diagnostic testing including a neural network for determining testing sufficiency
US5265031A (en) 1990-11-26 1993-11-23 Praxair Technology, Inc. Diagnostic gas monitoring process utilizing an expert system
US5214582C1 (en) 1991-01-30 2001-06-26 Edge Diagnostic Systems Interactive diagnostic system for an automobile vehicle and method
US5143452A (en) 1991-02-04 1992-09-01 Rockwell International Corporation System for interfacing a single sensor unit with multiple data processing modules
JP2636527B2 (en) 1991-03-04 1997-07-30 三菱電機株式会社 Insulation degradation prevention and insulation degradation prediction diagnostic equipment for electrical equipment storage equipment
US5137370A (en) 1991-03-25 1992-08-11 Delta M Corporation Thermoresistive sensor system
US5282131A (en) 1992-01-21 1994-01-25 Brown And Root Industrial Services, Inc. Control system for controlling a pulp washing system using a neural network controller
US5285152A (en) * 1992-03-23 1994-02-08 Ministar Peripherals International Limited Apparatus and methods for testing circuit board interconnect integrity
US5228780A (en) 1992-10-30 1993-07-20 Martin Marietta Energy Systems, Inc. Dual-mode self-validating resistance/Johnson noise thermometer system
US5392293A (en) * 1993-02-26 1995-02-21 At&T Corp. Built-in current sensor for IDDQ testing
US5570034A (en) * 1994-12-29 1996-10-29 Intel Corporation Using hall effect to monitor current during IDDQ testing of CMOS integrated circuits
DK0770858T3 (en) * 1995-10-26 2000-05-08 Flowtec Ag Coriolis mass flow detector with a single measuring tube
US5781024A (en) * 1996-07-26 1998-07-14 Diametrics Medical, Inc. Instrument performance verification system
US5869772A (en) * 1996-11-27 1999-02-09 Storer; William James A. Vortex flowmeter including cantilevered vortex and vibration sensing beams
US5854993A (en) * 1996-12-10 1998-12-29 Caterpillar Inc. Component machine testing using neural network processed vibration data analysis
US6002952A (en) * 1997-04-14 1999-12-14 Masimo Corporation Signal processing apparatus and method
US6014612A (en) * 1997-10-02 2000-01-11 Fisher Controls International, Inc. Remote diagnostics in a process control network having distributed control functions
FI116587B (en) * 1997-10-17 2005-12-30 Metso Automation Oy Method and apparatus for verifying the proper functioning of the restraint
US6046642A (en) * 1998-09-08 2000-04-04 Motorola, Inc. Amplifier with active bias compensation and method for adjusting quiescent current
US6289735B1 (en) * 1998-09-29 2001-09-18 Reliance Electric Technologies, Llc Machine diagnostic system and method for vibration analysis
US7206646B2 (en) * 1999-02-22 2007-04-17 Fisher-Rosemount Systems, Inc. Method and apparatus for performing a function in a plant using process performance monitoring with process equipment monitoring and control
US6546814B1 (en) * 1999-03-13 2003-04-15 Textron Systems Corporation Method and apparatus for estimating torque in rotating machinery
US6298308B1 (en) * 1999-05-20 2001-10-02 Reid Asset Management Company Diagnostic network with automated proactive local experts
JP3505119B2 (en) * 2000-02-28 2004-03-08 株式会社日立製作所 Input circuit
US6648082B2 (en) * 2000-11-07 2003-11-18 Halliburton Energy Services, Inc. Differential sensor measurement method and apparatus to detect a drill bit failure and signal surface operator
US6970003B2 (en) * 2001-03-05 2005-11-29 Rosemount Inc. Electronics board life prediction of microprocessor-based transmitters

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57196619A (en) * 1981-05-29 1982-12-02 Hitachi Ltd Failure diagnostic system for analog-to-digital converter
GB2317969A (en) * 1996-10-04 1998-04-08 Bosch Gmbh Robert Monitoring the measured data acquisistion in an engine control unit
US6396426B1 (en) * 1998-10-05 2002-05-28 Texas Instruments Incorporated Embedded mechanism offering real-time self failure detection for an analog to digital converter
US6492921B1 (en) * 1999-03-24 2002-12-10 Matsushita Electric Industrial Co., Ltd. Device for clamping multiple signals

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 007, no. 045 (E - 160) 23 February 1983 (1983-02-23) *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009040216A2 (en) * 2007-09-24 2009-04-02 Continental Automotive Gmbh Vehicle control unit having a microcontroller the supply voltage of which is monitored and associated method
WO2009040216A3 (en) * 2007-09-24 2009-08-20 Continental Automotive Gmbh Vehicle control unit having a microcontroller the supply voltage of which is monitored and associated method
DE102007045509B4 (en) * 2007-09-24 2011-06-22 Continental Automotive GmbH, 30165 Vehicle control unit with a supply voltage monitored microcontroller and associated method
CZ301839B6 (en) * 2009-04-01 2010-07-07 Ceské vysoké ucení technické v Praze Fakulta elektrotechnická Circuit arrangement for testing analog-to-digital converters

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