WO2005076356A1 - Layered crossbar memory connected to integrated circuit - Google Patents

Layered crossbar memory connected to integrated circuit Download PDF

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Publication number
WO2005076356A1
WO2005076356A1 PCT/NO2005/000027 NO2005000027W WO2005076356A1 WO 2005076356 A1 WO2005076356 A1 WO 2005076356A1 NO 2005000027 W NO2005000027 W NO 2005000027W WO 2005076356 A1 WO2005076356 A1 WO 2005076356A1
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WO
WIPO (PCT)
Prior art keywords
stack
crossbar
memories
integrated circuit
crossbars
Prior art date
Application number
PCT/NO2005/000027
Other languages
French (fr)
Other versions
WO2005076356B1 (en
Inventor
Kim Oyhus
Original Assignee
Kim Oyhus
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kim Oyhus filed Critical Kim Oyhus
Priority to EP05704640A priority Critical patent/EP1719177A1/en
Publication of WO2005076356A1 publication Critical patent/WO2005076356A1/en
Publication of WO2005076356B1 publication Critical patent/WO2005076356B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/202—Integrated devices comprising a common active layer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Definitions

  • the purpose of this invention is to provide a cheap and simple way to efficiently fabricate 3-dimensional memory, possibly massive 3D memory.
  • Modern memories are typically 2 dimensional objects consisting of a few layers, such as integrated circuits built in a layering process, or stacked 2 sided magnetic plates, or layered DVDs with a transparent layer.
  • One obvious way to produce larger memories is to increase the number of layers, but this introduces a lot of practical problems.
  • In integrated circuits it increases process complexity and fault rate, due to the necessary precision and multiplication of an already complex process.
  • For magnetic and optical plates there is the problem of multiplication of complicated, expensive, and large read/write heads.
  • For holographic storage there is the problem of deformation of material.
  • crossbar memories can be simply stacked, with no interconnections. No strips like in the prior art patent.
  • the crossbars can be uneven, vary in thickness, have cuts and short circuits, and be warped and bent.
  • the thin crossbar- memories can have variable thickness, and non-rectangular cross sections in the crossbars. All provided that the crossbar memories still can be stacked, and the errors are not overly excessive.
  • Crossbar memories are simple devices. Much simpler than most integrated circuits. They can lack complex electronic logic. This makes their production simpler, and thus cheaper.
  • FIG 4 3 dimensional electronic memory consisting of stacked thin layers (Fig 4) with crossbar memories, where the crossbars are diagonally cut (12) (Fig 1) such that the crossbar conductors (13) are connected to the surface of an integrated circuit (13) (Fig 2) .
  • FIG 1 shows a perspective view of a diagonally cut stack of crossbar memories. The cut is visible below the front layer.
  • FIG 2 shows a perspective view of the cut crossbar memory, attached to an integrated circuit.
  • FIG 3 shows the intersection between the integrated circuit and the cut crossbars.
  • the pads on the integrated circuit are represented as simple squares to make the figure visually understandable.
  • the pattern of connections are quite disordered.
  • FIG 4 shows a layer of cut crossbar memory.
  • Crossbar memories are devices consisting of rows of electrically conducting bars in one layer, and columns in a different layer, such that the conductors of one layer cross near the conductors of the other layer. Between these layers there are many different solutions for storing data, such as organic fuses, light emitting and conduction changing polymers, PN semiconductor transitions, etc.
  • the only demand of this invention is that the conductors are accessible through the crossbar, which can be uneven, have faults, and other angles between them than 90 degrees.
  • An example of another angle would be the 60 degrees of hexagonal packing that would facilitate light activated crossbar memory by packing the lighted regions tighter.
  • a preferred embodiment of the invention is in the form of a thin film made from special plastic, as mentioned in claim 3.
  • This thin film have conducting bars printed on each side, so that they cross, thus making a crossbar.
  • This thin film is sandwiched with insulating layers and rolled up in a roll. This roll is cut approximately along the bars, into pieces. These pieces are again cut (12) diagonally relative to the crossbars, as in claim 4, making a wedge, like in Fig 1.
  • the wedge is imprecisely connected to the integrated circuit (14) along the diagonal cut, like in Fig 2.
  • This connection makes the conductive bars in the crossbar (13) connected with the pads on the integrated circuits (15) resulting in a disordered pattern of conductor connections as in Fig 3.
  • Hexagonal pads on the chip can also be an advantage.
  • the size and distance between the pads are not specified, as they are dependent on the specific characteristics of the crossbar conductors. Nor are area of pads on the integrated circuit specified.
  • One among other factors to be adjusted are probability of 2 or more bars connecting to 1 or more pads. As illustrated in Fig 4, an inexact double coupling need not result in a problem, just a "W” like crossing of conducting bars instead of an "X” like crossing.
  • the crossbars need not be as thin and flexible as in thin plastic film.
  • crossbars cross several integrated circuits is an obvious possibility, as well as having several stacks of crossbars coupled to one integrated circuit.
  • This memory device consisting of layers of crossbar memories
  • This memory device consisting of layers of crossbar memories
  • To access the memories multiplexed connections to the conductors in the crossbars are necessary.
  • the stack of memories is cut diagonally, so that all conductors in the stack are accessible on one plane side. This side is then connected to the surfaced of an integrated circuit to provide necessary multiplexing and possibility of necessary error correction and necessary adaption to misalignment of connectors to the chip.
  • the integrated circuit activates the pads 15 (Fig 4) connected to the conducting bars which cross at the memory element 11 (Fig 4) .
  • the integrated circuit can be viewed as a multiplexer to access the bars in the layered crossbar memories.
  • a map of the connections of Fig 3 can be made by measuring the electric behavior between close pads to see if they are connected to crossing bars. This map can be used to order accessible memory units so they can appear to be contiguous. The other strategy is to avoid the map, and instead measure with each access, using hashing techniques to give the appearance of contiguousness . In either case, error correction methods has to be applied. This is known art in the designing of hard disks and error correction codes.

Abstract

3 dimensional electronic memory consisting of stacked thin layers (Fig 4) of crossbar memories, connected to surface of integrated circuit (14) (Fig 2) through crossbar connections (13) accessible by a diagonal cut (12) in the stack (Fig 1).

Description

layered memory
BACKGROUND OF THE INVENTION
The purpose of this invention, is to provide a cheap and simple way to efficiently fabricate 3-dimensional memory, possibly massive 3D memory.
Modern memories are typically 2 dimensional objects consisting of a few layers, such as integrated circuits built in a layering process, or stacked 2 sided magnetic plates, or layered DVDs with a transparent layer. One obvious way to produce larger memories is to increase the number of layers, but this introduces a lot of practical problems. In integrated circuits it increases process complexity and fault rate, due to the necessary precision and multiplication of an already complex process. For magnetic and optical plates there is the problem of multiplication of complicated, expensive, and large read/write heads. For holographic storage there is the problem of deformation of material.
An earlier example of ways of connecting layered memories is US- 6,376,904 which is assigned to Rambus Inc, a company known for their memory technology. This patent regards stacking of interconnected integrated circuits, which can be memories. Disadvantages of this is the usually higher cost and complexity of integrated circuits, as compared to f .ex. simple lattices in thin film. Connecting integrated circuits together also require precision and accuracy in the form of precisely placed conductors, flow soldering, or film with contacts. None of these interconnections are microscopic.
It has been experimented with producing 3-dimensional memories by stacking layers of memories made from thin film electronics, such as in the Norwegian patent application NO-20001360, where the layers are connected together by stacking them very precisely in a pyramid, so that end pads are aligned, and can be connected. That patent says that this makes vias, conductive holes in layers, unnecessary. As of the filing date of this patent, the company of that patent, Thin Film Electronics, is reported to have problems going beyond 8 layers.
A couple of major problems if one stacks many layers of thin films with memories and electronics, is that there are going to be large amounts of faulty electronics, and alignment problems in interconnecting the layers. If the complex electronics are removed, by using simpler cross-bar memories, then the problem of faulty electronics gets smaller. However, the problem of connecting millions to billions of crossbar contacts precisely, when they come from different layers, possibly with variation in thickness and crossbar distances, seems insurmountable.
BACKGROUND OF THE INVENTION-OBJECTS AND ADVANTAGES
Some objects and advantages of the example of the invention are:
(a) The crossbar memories can be simply stacked, with no interconnections. No strips like in the prior art patent.
(b) Great precision is not needed in fabrication of thin crossbar memories. The crossbars can be uneven, vary in thickness, have cuts and short circuits, and be warped and bent. The thin crossbar- memories can have variable thickness, and non-rectangular cross sections in the crossbars. All provided that the crossbar memories still can be stacked, and the errors are not overly excessive.
(c) Crossbar memories are simple devices. Much simpler than most integrated circuits. They can lack complex electronic logic. This makes their production simpler, and thus cheaper.
(d) Connection of millions to billions of conductors from crossbar memories are simplified to the conductively fastening of one cut surface of stacked memories to an integrated circuit. This is mentioned in claims 1 and 4.
(e) All control circuitry and error correction circuitry are accessed through, or embedded into, an integrated circuit
(f) It is possible to make massive memories by using large, and/or numerous stacks of crossbar memories, connected to one or more integrated circuits. One can envision a liter of memory, laying like a big wedge on a whole wafer of integrated circuits. Storing 1 bit per crossbar crossing, and having 1 um distance between them, could give 100 000 GB of storage.
(g) The stacking of thin film crossbar memories, they are mentioned in claim 3, can be done industrially by rolling the film up and cutting it to the required wedges, or other shapes with the diagonal cut. The slight bend that this gives to the stack, is not a problem for alignment.
(h) Thermal expansion and physical stresses can be alleviated by having the stack bent and skewed, thus giving more material flexibility. This reduces the need of having materials with compatible thermal expansion coefficients.
(i) Price. This device should be cheap to manufacture. Cost should be comparable to one integrated circuit.
Further objects and advantages will become apparent from a consideration of the ensuing description and drawings. SUMMARY
3 dimensional electronic memory consisting of stacked thin layers (Fig 4) with crossbar memories, where the crossbars are diagonally cut (12) (Fig 1) such that the crossbar conductors (13) are connected to the surface of an integrated circuit (13) (Fig 2) .
DRAWINGS—FIGURES
Drawings are not to scale, as there is no preferred scale.
FIG 1 shows a perspective view of a diagonally cut stack of crossbar memories. The cut is visible below the front layer.
FIG 2 shows a perspective view of the cut crossbar memory, attached to an integrated circuit.
FIG 3 shows the intersection between the integrated circuit and the cut crossbars. The pads on the integrated circuit are represented as simple squares to make the figure visually understandable. The pattern of connections are quite disordered.
FIG 4 shows a layer of cut crossbar memory.
DRAWINGS—Reference Numerals
10 The front most layer of crossbar memory in the stack.
11 A crossing point of 2 different conducting bars in a memory. 12 The diagonal cut in the stack. The cut of all crossbars are visible.
13 A cut bar in the diagonal cut.
14 An integrated circuit.
15 A contact pad on the integrated circuit.
16 A side of the stack, not the diagonal cut. Only half the bars are visible.
DETAILED DESCRIPTION—FIG 2 -PREFERRED EMBODIMENT (s)
Crossbar memories are devices consisting of rows of electrically conducting bars in one layer, and columns in a different layer, such that the conductors of one layer cross near the conductors of the other layer. Between these layers there are many different solutions for storing data, such as organic fuses, light emitting and conduction changing polymers, PN semiconductor transitions, etc. The only demand of this invention is that the conductors are accessible through the crossbar, which can be uneven, have faults, and other angles between them than 90 degrees. An example of another angle would be the 60 degrees of hexagonal packing that would facilitate light activated crossbar memory by packing the lighted regions tighter.
A preferred embodiment of the invention, is in the form of a thin film made from special plastic, as mentioned in claim 3. This thin film have conducting bars printed on each side, so that they cross, thus making a crossbar. This thin film is sandwiched with insulating layers and rolled up in a roll. This roll is cut approximately along the bars, into pieces. These pieces are again cut (12) diagonally relative to the crossbars, as in claim 4, making a wedge, like in Fig 1. The wedge is imprecisely connected to the integrated circuit (14) along the diagonal cut, like in Fig 2. This connection makes the conductive bars in the crossbar (13) connected with the pads on the integrated circuits (15) resulting in a disordered pattern of conductor connections as in Fig 3.
Alternative Embodiments
Hexagonal pads on the chip can also be an advantage. The size and distance between the pads are not specified, as they are dependent on the specific characteristics of the crossbar conductors. Nor are area of pads on the integrated circuit specified. One among other factors to be adjusted are probability of 2 or more bars connecting to 1 or more pads. As illustrated in Fig 4, an inexact double coupling need not result in a problem, just a "W" like crossing of conducting bars instead of an "X" like crossing.
The crossbars need not be as thin and flexible as in thin plastic film.
Having the crossbars cross several integrated circuits is an obvious possibility, as well as having several stacks of crossbars coupled to one integrated circuit.
It is possible to cut off the top of the wedge, so as to make the device flatter, to fit inside flatter packages. This means some loss of memory, especially if the stack is cut squarely.
Operation
The manner of using this memory device, consisting of layers of crossbar memories, is to access the layers of memory through the integrated circuit. To access the memories, multiplexed connections to the conductors in the crossbars are necessary. To achieve these connections, the stack of memories is cut diagonally, so that all conductors in the stack are accessible on one plane side. This side is then connected to the surfaced of an integrated circuit to provide necessary multiplexing and possibility of necessary error correction and necessary adaption to misalignment of connectors to the chip.
To access a single memory element in a crossbar switch 11 (Fig 4), the integrated circuit activates the pads 15 (Fig 4) connected to the conducting bars which cross at the memory element 11 (Fig 4) . This is the main principle of operation. Thus the integrated circuit can be viewed as a multiplexer to access the bars in the layered crossbar memories.
There are two overlapping strategies for ordered memory access of the device. A map of the connections of Fig 3 can be made by measuring the electric behavior between close pads to see if they are connected to crossing bars. This map can be used to order accessible memory units so they can appear to be contiguous. The other strategy is to avoid the map, and instead measure with each access, using hashing techniques to give the appearance of contiguousness . In either case, error correction methods has to be applied. This is known art in the designing of hard disks and error correction codes.
Conclusion, Ramification, and Scope
Accordingly, the reader will see that this invention can be used to make 3-dimensional memories efficiently and cheaply. Although the description above contains specificities, these should not be construed as limiting the scope of the invention, but as merely providing illustrations of some of the presently preferred embodiments of this invention. Thus the scope of the invention should be determined by the appended claims and their legal equivalents, rather than by the examples given.

Claims

Claims: I claim:
1. A crossbar device, comprising:
(a) a stack, having a plurality of stacked layers with crossbars,
(1) where said stack of crossbars are cut diagonally relative to said crossbars in said stack,
(2) whereby said crossbars become conductively accessible on the surface of said cut of said stack, and
(b) an integrated circuit, at least one, having an array of conductive pads, said pads are connected to said surface of at least one of said stack, whereby said pads are disorderly and imperfectly connected to said crossbars.
2. Said crossbar device of claim 1 wherein said layers of crossbars are memory.
3. Said crossbar device of claim 2 wherein said layers of crossbar memories are thin film.
4. A method for production of memory, comprising:
(a) providing a stack, having a plurality of stacked layers with crossbar memories, (b) cutting said stack of memories diagonally relative to said crossbars in said stack, whereby said crossbars become conductively accessible on the surface of the cut of said stack, and (c) providing an integrated circuit, at least one, having an array of conductive pads, (d) connecting disorderly and imperfectly said pads to said surface of at least one of said stack.
PCT/NO2005/000027 2004-02-03 2005-01-24 Layered crossbar memory connected to integrated circuit WO2005076356A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP05704640A EP1719177A1 (en) 2004-02-03 2005-01-24 Layered crossbar memory connected to integrated circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NO20040502A NO320176B1 (en) 2004-02-03 2004-02-03 Stacked layers of grid memory connected to integrated circuit.
NO20040502 2004-02-03

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WO2005076356A1 true WO2005076356A1 (en) 2005-08-18
WO2005076356B1 WO2005076356B1 (en) 2005-10-06

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6021074A (en) * 1998-09-04 2000-02-01 Advanced Micro Devices, Inc. Direct access to random redundant logic gates by using multiple short addresses
WO2001069679A1 (en) * 2000-03-15 2001-09-20 Thin Film Electronics Asa Vertical electrical interconnections in a stack
WO2001071722A1 (en) * 2000-03-22 2001-09-27 Thin Film Electronics Asa Multidimensional addressing architecture for electronic devices
US6376904B1 (en) * 1999-12-23 2002-04-23 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6021074A (en) * 1998-09-04 2000-02-01 Advanced Micro Devices, Inc. Direct access to random redundant logic gates by using multiple short addresses
US6376904B1 (en) * 1999-12-23 2002-04-23 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package
WO2001069679A1 (en) * 2000-03-15 2001-09-20 Thin Film Electronics Asa Vertical electrical interconnections in a stack
WO2001071722A1 (en) * 2000-03-22 2001-09-27 Thin Film Electronics Asa Multidimensional addressing architecture for electronic devices

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
DATABASE INSPEC [online] THE INSTITUTION OF ELECTRICAL ENGINEERS, STEVENAGE, GB; 4 December 2003 (2003-12-04), ZIEGLER M M ET AL: "CMOS/nano co-design for crossbar-based molecular electronic systems", XP002327737, Database accession no. 7951795 *
MATTHEW M ZIEGLER: "CMOS/Nano Co-Design for Crossbar-Based Molecular Electronics Systems", IEEE TRANSACTIONS ON NANOTECHNOLOGY IEEE USA, vol. 2, no. 4, 4 December 2003 (2003-12-04), pages 217 - 230, XP002327736, ISSN: 1536-125X *
ZIEGLER M M ET AL: "A case for cmos/nano co-design", IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN. ICCAD 2002. IEEE/ACM DIGEST OF TECHNICAL PAPERS. SAN JOSE, CA, NOV. 10 - 14, 2002, IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, NEW YORK, NY : IEEE, US, 10 November 2002 (2002-11-10), 2002-11-10, pages 348 - 352, XP010624669, ISBN: 0-7803-7607-2 *

Also Published As

Publication number Publication date
EP1719177A1 (en) 2006-11-08
WO2005076356B1 (en) 2005-10-06
NO20040502L (en) 2005-08-04
NO320176B1 (en) 2005-11-07

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