WO2005069132A1 - Configuring a shared resource - Google Patents
Configuring a shared resource Download PDFInfo
- Publication number
- WO2005069132A1 WO2005069132A1 PCT/EP2004/053205 EP2004053205W WO2005069132A1 WO 2005069132 A1 WO2005069132 A1 WO 2005069132A1 EP 2004053205 W EP2004053205 W EP 2004053205W WO 2005069132 A1 WO2005069132 A1 WO 2005069132A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- resource
- processing complexes
- configuratfon
- processing
- determining
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
- G06F9/526—Mutual exclusion algorithms
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/54—Link editing before load time
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/10—Protocols in which an application is distributed across nodes in the network
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/34—Network arrangements or protocols for supporting network services or applications involving the movement of software or configuration parameters
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/40—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass for recovering from a failure of a protocol instance or entity, e.g. service redundancy protocols, protocol state redundancy or protocol service redirection
Definitions
- the present disclosure relates to a method, system, and an article of manufacture for configuring a shared resource.
- a multi-cluster system may couple a plurality cf computing nodes together.
- the plurality cf coupled computing nodes may collectively perform as a single computational system.
- the multi-cluster system may be used for parallel processing, bad balancing, fault tolerance, etc., and implement a high-availability system or a redundant information technology system.
- certain multi-cluster systems may store the same data in a plurality cf computing nodes, where a computing node may be a computational unit, a storage unit, etc.
- an alternate computing node cf the multi-cluster system may be used to substitute the unavailable computing node.
- a resource such as a Peripheral Component Interconnect (PCI) bus may be used to interconnect devices, with the focal bus of a processor and main memory.
- PCI Peripheral Component Interconnect
- a PCI adapter may be shared by a plurality of computing nodes via a PCI bus. Hosts may ccmmunicate with the computing nodes cf the multi-cluster system via the shared PCI adapter.
- the failure cf one computing node may still allow the hosts to continue communications with other computing nodes of the multi-cluster system. Such hosts may be able to access the shared PCI adapter and access data associated with the computing nodes that have not failed.
- the shared resource may be in an erroneous state and may then not be shared amongst the computing nodes. Disclosure of Invention
- FIG 1 illustrates a block diagram cf a first computing environment, in accordance with certain described embodiments of the inventfon;
- FIG 2 illustrates a block diagram cf data structures associated with a shared PCI adapter, in accordance with certain described embodiments of the inventfon;
- FIG 3 illustrates fogic for configuring a shared PCI adapter, in accordance with certain described embodiments of the inventfon;
- FIG 4 illustrates fogic for transferring logical ownership of a shared PCI adapter, in accordance with certain described embodiments of the inventfon;
- FIG 5 illustrates a block diagram cf a second computing environment, in accordance with certain described embodiments cf the inventfon; and FIG 6 illustrates a block diagram cf a computer architecture in which certain described aspects cf the inventfon are implemented. Best Mode for Carrying Out the Invention
- FIG 1 illustrates a block diagram cf a first computing environment, in accordance " with certain embodiments of the inventfon.
- a plurality cf processing complexes 100a... lOOn are coupled to a PCI adapter 102 by a PCI bus 104.
- a processing complex such as the processing complex 100a, may include one or more computing nodes, where the computing nodes may include uniprocessor or multiprocessor systems.
- a processing complex 100a... lOOn may include a personal computer, a workstation, a server, a mainframe, a hand held computer, a palm top computer, a telephony device, a network appliance, a blade computer, a storage controller, etc.
- the PCI adapter 102 may be replaced by a PCI-X adapter, or any PCI or PCI-X bus compatible device.
- the PCI bus 104 may be replaced by a PCI-X bus or some other bus.
- the plurality of processing complexes 100a...1 OOn include a plurality cf boot applications 106a...106n and a plurality cf clustering applications 108a....108n.
- the processing complex 100a may include the boot application 106a and the clustering application 108 a
- the processing complex 100b may include the boot applicatbn 106b and the clustering application 108b
- the processing complex lOOn may include the boot application 106n and the clustering ap- plication 108n.
- the boot applications 106a...106n and the clustering applicatfons 108a...108n may be implemented in software, firmware, or hardware or any combination therecf
- a boot applicatfon 106a...106n when executed may perform an initial program load cf the corresponding processing complex 100a... lOOn.
- the boot applicatfon 106a may perform an initial program bad of the processing complex 100a
- the boot applicatfon 106b may perform an initial program load cf the processing complex 100b
- the boot applicatfon 106n may perform an initial program bad cf the processing complex lOOn.
- the operating system (not shown), device drivers (not shown), etc., of the processing complex may be loaded, such that the processing complex becomes ready to execute other applicatfons after the initial program bad is completed.
- the clustering applicatfons 108a...l08n when executed may allow the processing nodes 100a... lOOn to share the PCI adapter 102.
- only one clustering applicatbn may configure the PCI adapter 102 and broadcast the configuration information cf the PCI adapter 102 to the other clustering applicatfons.
- the clustering applicatfon 108a may configure the PCI adapter 102 and broadcast the configuration information of the PCI adapter 102 to the 10 clustering applicatfon 108b....108n that may be executing in the processing complexes 100b... lOOn.
- the plurality cf clustering applicatfons 108a...108n may be part cf a distributed clustering applicatfon associated with the processing complexes 100a... lOOn.
- FIG 2 illustrates a block diagram of data structures associated with the PCI 20 adapter 102, in accordance with certain embodiments of the inventfon.
- a defer configuration indicator 200 may be associated with the PCI adapter 102.
- the defer configuration indicator 200 may represent a single bit cf data, where the single bit cf data may indicate whether configuration of the PCI adapter 102 should be deferred until the completion cf the initial program bads cf the processing complexes 100a... lOOn.
- the boot applicatfons 106a...106n may not configure the PCI adapter 102 during initial program loads of the processing complexes 100a... lOOn.
- only one cf the clustering applicatfons 108a...108n such as, clustering applicatfon 108a, may configure the PCI adapter 102.
- the clustering applicatfons 108a...108n may start executing only after the completion cf the initial program toads of the processing complexes 100a... lOOn.
- FIG 3 illustrates fogic for configuring a shared PCI adapter implemented in the processing complexes 100a... lOOn, in accordance with certain embodiments cf the inventfon.
- Control starts at blocks 300a...300n, where the boot applicatfons 106a...106n execute in the corresponding processing complexes 100a... lOOn.
- the boot applicatfon 106a executes (atbbck 300a) in the processing complex 100a
- the boot applicatfon 106b executes (at block 300b) in the processing complex 100b
- the boot applicatfon 106n executes (at bbck 300n) in the processing complex lOOn.
- the executbn cf the boot applicatfons 106a...106n in the processing complexes 100a... lOOn may be in parallel.
- the initial program toads start in the processing complexes 100a...l00n.
- each of the boot applications 106a...106n may determine (at block 302) from the defer configuration indicator 200 whether the configuration of the PCI adapter 102 is to be deferred until the completion of the initial prcgram foads cf the processing complexes 100a... lOOn. If so, the boot applicatfons 106a...106n complete (at block 304) the initial prcgram toads cf the processing complexes 100a... lOOn without configuring the PCI adapter 102.
- the clustering applicatfons 108a...l08n load (at block 306) in the corresponding processing complexes 100a... lOOn.
- the clustering applications 108a...108n may collectively determine (at block 308) a processing complex that is the logical owner of the PCI adapter 102, where the processing complex that is the logical owner is included in the plurality of processing complexes 100a... lOOn.
- the processing complex 100a may be determined as the logical owner cf the PCI adapter 102.
- the processing complex that is the logical owner of the PCI adapter 102 assumes the responsibility cf configuring the PCI adapter 102 and broadcasting the configuration information of the PCI adapter 102 to the other processing complexes.
- the clustering applicatfons 108a...108n restrict (at block 310) those processing complexes that are not the logical owner of the PCI adapter 102 from attempting to configure the PCI adapter 102.
- the clustering applicatbn in the logical owner configures (at block 312) the PCI adapter 102. For example, in certain embodiments if processing complex 100a is the logical owner then the clustering applicatbn 108a may configure the PCI adapter 102.
- the clustering applicatfon in the logical owner determines (at block 314) whether the configuratfon of the PCI adapter 102 is complete.
- the clustering applicatfon in the logical owner broadcasts (at block 316) the configuratfon information of the PCI adapter 102 to the clustering applicatfons cf the other processing complexes. For example, if processing complex 100a is determined to be the logical owner cf the PCI adapter 102, then the clustering applicatfon 108a distributes the configuratfon information cf the PCI adapter to the clustering applicatfons 108b...108n. The process stops (at block 318) in response to the completion cf the broadcast of the configuratfon information of the PCI adapter 102.
- the clustering applicatfon in the logical owner determines (at block 314) that the configuratfon of the PCI adapter 102 is incomplete, then the clustering applicatfon in the logical owner continues configuring (at block 312) the PCI adapter 102.
- the boot applicatfons 106a...106n may configure (at block 320) one or more PCI adapters associated with the processing complexes 100a... lOOn during the initial prcgram loads cf the processing complexes 100a... lOOn as there may be no shared PCI adapter among the processing complexes 100a... lOOn. Subsequent to the configuratfon, the process stops (at block 318).
- the fogic cf FIG 3 illustrates certain embodiments in which configuratfon of the shared PCI adapter 102 is delayed until the completion cf the initial program bads cf the processing complexes 100a... lOOn.
- configuratfon of the shared PCI adapter 102 is delayed until the completion cf the initial program bads cf the processing complexes 100a... lOOn.
- only one of the plurality of processing complexes 100a... lOOn may configure the shared PCI adapter 102 and broadcast the configuratfon information cf the shared PCI adapter 102 to the other processing complexes.
- FIG 4 illustrates fogic for transferring logical ownership of the shared PCI adapter 102, in accordance with certain described embodiments of the inventfon.
- the fogic for transferring logical ownership of the shared PCI adapter may be implemented in the clustering applicatfons 108a...108n that execute in the processing complexes 100a... lOOn.
- Control starts at bbck 400, where the processing complex that is the logical owner cf the PCI adapter 102 fails.
- the failure may be as a result cf a malfunctioning of the logical owner because of a software, hardware, or firmware error. Failures cf the logical owner may also occur because cf other reasons.
- the clustering applicatfons in the processing complexes that are not the logical owner determine (at block 402) a new logical owner cf the PCI adapter 102.
- the clustering applicatfons 108b...108n determine a new logical owner of the PCI adapter 102 from the processing complexes 100b...100n.
- the clustering applicatfon in the new logical owner assumes (at block 404) responsibility for configuring or reconfiguring the PCI adapter 102 and broadcasting the configuratfon information of the PCI adapter 102 to the clustering applicatfons in the other processing complexes. For example, if processing complex 100a had foiled and the new logical owner is the processing complex 100b, then the new logical owner 100b may assume the responsibility for configuring or reconfiguring the PCI adapter 102 and broadcasting the configuratfon information of the PCI adapter 102 to the clustering apphcations 108c...108n in the processing complexes 100c... lOOn, where the processing complexes 100a, 100b, 100c,.... lOOn share the PCI adapter 102.
- the clustering applicatbn in the new logical owner determines (at bbck 406) whether the failed processing complex has become fiinctbnal and rejoined the processing complexes, where the processing complexes may form a multi-cluster environment. If so, in certain embodiments the clustering applicatbn in the new logical owner may transfer (at block 408) logical ownership cf the shared PCI adapter 102 back to the old logical owner. For example, the new logical owner 100b may optionally transfer logical ownership of the shared PCI adapter 102 back to the original logical owner 100a, if the original logical owner 100a is no longer a failed processing complex.
- the new logical owner determines (at block 406) that the failed processing complex has not become functional, then the new logical owner continues (at block 404) to assume responsibility for configuring the shared PCI adapter 102 and broadcasting the configuratfon information.
- FIG 4 illustrates certain embodiments in which in the event of a failure of a logical owner of the shared PCI adapter 102, the other processing complexes determine a new logical owner that assumes the responsibility of configuring the PCI adapter 102 and broadcasting the configuratfon information of the PCI adapter 102 to the other functioning processing complexes.
- the new logical owner may in transfer the logical ownership cf the PCI adapter back to the original logical owner.
- FIG 5 illustrates a block diagram of a second computing environment 500, in accordance with certain described embodiments cf the inventfon.
- the plurality cf processing complexes 100a...100n may comprise a multi-cluster system 502, where a processing complex in the plurality of processing complexes 100a... lOOn is a node of the multi-cluster system 502.
- the processing complexes 100a...100n in the multi-cluster system 502 may be coupled to a shared resource 504 via a bus 506.
- the shared resource 504 may include the PCI adapter 102 and the bus 506 may be a PCI bus.
- the shared resource 504 may include a defer configuratfon indicator 508 that indicates whether the configuratfon of the shared resource 504 should be delayed until the processing complexes 100a... lOOn cf the multi-cluster system 502 have completed initial prcgram bads. Subsequent to the completion cf the initial prcgram loads of the processing complexes 100a... lOOn cf the multi-cluster system 502, only one of the processing complexes 100a... lOOn may configure the shared resource 504 and broadcast the configuratfon informatfon of the shared resource to the other processing complexes.
- a host 510 that is coupled to the multi-cluster system 502 may access data in the processing complexes 100a... lOOn via the shared resource 504. Even if one or more processing complexes 100a...100n fail, the other processing complexes may still be accessed by the host 510 via the shared resource 504.
- a clustering applicatfon implemented in the plurality cf processing complexes may coordinate the plurality cf processing complexes, such that, only a single processing complex cf the plurality cf processing complexes configures the shared PCI adapter and broadcasts the configuratfon informatfon of the shared PCI adapter to the other processing complexes.
- the shared PCI adapter may be in an erroneous state and may not be shared among the plurality cf processing complexes.
- the embodiments allow the PCI adapter to be shared among the plurality cf processing complexes by configuring the PCI adapter with only one cf the plurality of processing complexes.
- the described techniques may be implemented as a method, apparatus or article of manufacture using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof
- article cf manufacture refers to code or fogic implemented in hardware fogic (e.g., an integrated circuit chip, Programmable Gate Array (PGA), Applicatfon Specific Integrated Circuit (ASIC), etc.) or a computer readable medium (e.g., magnetic storage medium, such as hard disk drives, floppy disks, tape), optical storage (e.g., CD-ROMs, optical disks, etc.), volatile and non- volatile memory devices (e.g., EEPROMs, ROMs, PROMs, RAMs, DRAMs, SRAMs, firmware, programmable fogic, etc.).
- Code in the computer readable medium is accessed and executed by a processor.
- embodiments are made may further be accessible through a transmission media or from a file server over a network.
- the article of manufacture in which the code is implemented may comprise a transmission media, such as a network transmission line, wireless transmission media, signals propagating through space, radio waves, infrared signals, etc.
- a transmission media such as a network transmission line, wireless transmission media, signals propagating through space, radio waves, infrared signals, etc.
- the article of manufacture may comprise any informatfon bearing medium known in the art.
- FIG 6 illustrates a bbck diagram of a computer architecture in which certain aspects cf the inventfon are implemented.
- Any cf the processing complexes 100a... lOOn or the host 510 may implement a computer architecture 600 having a processor 602, a memory 604 (e.g., a volatile memory device), and storage 606 (e.g., a non-volatile storage, magnetic disk drives, optical disk drives, tape drives, etc.).
- the storage 606 may comprise an internal storage device, an attached storage device or a network accessible storage device. Programs in the storage 606 may be loaded into the memory 604 and executed by the processor 602 in a manner known in the art.
- the architecture may further include a network card 608 to enable communication with a network.
- the architecture may also include at least one input 610, such as a keyboard, a touchscreen, a pen, voice-activated input, etc., and at least one output 612, such as a display device, a speaker, a printer,
- FIGs. 3 and 4 describes specific operations occurring in a particular order. Further, the operations may be performed in parallel as well as sequentially. In alternative embodiments, certain of the logic operations may be performed in a different order, modified or removed and still implement embodiments of the present inventfon. Moreover, steps may be added to the above described logic and still conform to the embodiments. Yet further steps may be performed by a single process or distributed processes. [047] Many cf the software and hardware components have been described in separate modules for purposes cf illustratfon. Such components may be integrated into a fewer number cf components or divided into a larger number cf components. Additionally, certain operations described as performed by a specific component may be performed by other components. [048] Therefore, the foregoing description of the embodiments has been presented for the purposes of illustratfon and description. It is not intended to be exhaustive or to limit the inventfon to the precise form disclosed.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04804634A EP1704472A1 (en) | 2004-01-07 | 2004-12-01 | Configuring a shared resource |
JP2006548191A JP2007518168A (en) | 2004-01-07 | 2004-12-01 | Configuring shared resources |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/752,632 | 2004-01-07 | ||
US10/752,632 US7584271B2 (en) | 2004-01-07 | 2004-01-07 | Method, system, and computer readable medium for delaying the configuration of a shared resource |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005069132A1 true WO2005069132A1 (en) | 2005-07-28 |
Family
ID=34794700
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2004/053205 WO2005069132A1 (en) | 2004-01-07 | 2004-12-01 | Configuring a shared resource |
Country Status (6)
Country | Link |
---|---|
US (1) | US7584271B2 (en) |
EP (1) | EP1704472A1 (en) |
JP (1) | JP2007518168A (en) |
KR (1) | KR20070003817A (en) |
CN (1) | CN1902584A (en) |
WO (1) | WO2005069132A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070198982A1 (en) * | 2006-02-21 | 2007-08-23 | International Business Machines Corporation | Dynamic resource allocation for disparate application performance requirements |
CN103003805B (en) | 2010-07-16 | 2016-01-20 | 株式会社东芝 | The customization of bus adapter card |
Citations (2)
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US20030188108A1 (en) * | 2002-03-28 | 2003-10-02 | International Business Machines Corporation | System and method for dual stage persistent reservation preemption protocol |
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US643781A (en) * | 1898-09-19 | 1900-02-20 | Raoul Subrenat | Apparatus for mercerizing. |
US5109484A (en) * | 1986-04-09 | 1992-04-28 | International Business Machines Corporation | Self configuring terminal which polls loop network and generates list of connected devices for use in selectively downloading control programs |
US5590345A (en) * | 1990-11-13 | 1996-12-31 | International Business Machines Corporation | Advanced parallel array processor(APAP) |
JPH0581216A (en) * | 1991-09-20 | 1993-04-02 | Hitachi Ltd | Parallel processor |
US5446869A (en) * | 1993-12-30 | 1995-08-29 | International Business Machines Corporation | Configuration and RAM/ROM control of PCI extension card residing on MCA adapter card |
US5737524A (en) * | 1995-05-22 | 1998-04-07 | International Business Machines Corporation | Add-in board with programmable configuration registers for use in PCI bus computers |
US6021483A (en) * | 1997-03-17 | 2000-02-01 | International Business Machines Corporation | PCI-to-PCI bridges with a timer register for storing a delayed transaction latency |
US6134673A (en) * | 1997-05-13 | 2000-10-17 | Micron Electronics, Inc. | Method for clustering software applications |
US5901310A (en) * | 1997-09-11 | 1999-05-04 | Ati Technologies, Inc. | Storing firmware in compressed form |
US6101559A (en) * | 1997-10-22 | 2000-08-08 | Compaq Computer Corporation | System for identifying the physical location of one or more peripheral devices by selecting icons on a display representing the one or more peripheral devices |
US6336185B1 (en) * | 1998-09-24 | 2002-01-01 | Phoenix Technologies Ltd. | Use of other processors during BIOS boot sequence to minimize boot time |
US6732166B1 (en) * | 1999-05-28 | 2004-05-04 | Intel Corporation | Method of distributed resource management of I/O devices in a network cluster |
JP3626404B2 (en) | 2000-10-20 | 2005-03-09 | シャープ株式会社 | Ink sheet printer |
US6928538B2 (en) * | 2001-04-27 | 2005-08-09 | International Business Machines Corporation | Method and system for delayed booting of a target device in a network environment |
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2004
- 2004-01-07 US US10/752,632 patent/US7584271B2/en not_active Expired - Fee Related
- 2004-12-01 KR KR1020067013533A patent/KR20070003817A/en not_active Application Discontinuation
- 2004-12-01 WO PCT/EP2004/053205 patent/WO2005069132A1/en not_active Application Discontinuation
- 2004-12-01 CN CNA200480039566XA patent/CN1902584A/en active Pending
- 2004-12-01 EP EP04804634A patent/EP1704472A1/en not_active Withdrawn
- 2004-12-01 JP JP2006548191A patent/JP2007518168A/en not_active Withdrawn
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US6401120B1 (en) * | 1999-03-26 | 2002-06-04 | Microsoft Corporation | Method and system for consistent cluster operational data in a server cluster using a quorum of replicas |
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Also Published As
Publication number | Publication date |
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KR20070003817A (en) | 2007-01-05 |
US7584271B2 (en) | 2009-09-01 |
JP2007518168A (en) | 2007-07-05 |
EP1704472A1 (en) | 2006-09-27 |
CN1902584A (en) | 2007-01-24 |
US20050198230A1 (en) | 2005-09-08 |
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