WO2005067526A2 - Flipchip qfn package and method therefore - Google Patents
Flipchip qfn package and method therefore Download PDFInfo
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- WO2005067526A2 WO2005067526A2 PCT/US2005/001202 US2005001202W WO2005067526A2 WO 2005067526 A2 WO2005067526 A2 WO 2005067526A2 US 2005001202 W US2005001202 W US 2005001202W WO 2005067526 A2 WO2005067526 A2 WO 2005067526A2
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- leadframe
- leads
- leadframes
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- panel
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Definitions
- the present invention relates to integrated circuits and packaged integrated circuits and, more particularly, to a packaged integrated circuit formed using two separate leadfra es .
- An integrated circuit (IC) die is a small device formed on a semiconductor wafer, such as a silicon wafer.
- a leadframe is a metal frame that usually includes a paddle that supports an IC die that has been cut from the wafer.
- the leadframe has lead fingers that provide external electrical connections. That is, the die is attached to the die paddle and then bonding pads of the die are connected to the lead fingers via wire bonding or flip chip bumping to provide the external electrical connections.
- Encapsulating the die and wire bonds or flip chip bump with a protective material forms a package.
- the external electrical connections may be used as-is, such as in a Thin Small Outline Package (TSOP) , or further processed, such as by attaching spherical solder balls for a Ball Grid Array (BGA) .
- TSOP Thin Small Outline Package
- BGA Ball Grid Array
- These terminal points allow the die to be electrically connected with other circuits, such as on a printed circuit board.
- FIG. 1 is a top perspective view of a packaged semiconductor device in accordance with an embodiment of the present invention.
- FIG. 2 is a bottom perspective view of the packaged semiconductor device of FIG. 1;
- FIG. 3 is an enlarged top plan view of a portion of a first leadframe panel in accordance an embodiment of the present invention;
- FIG. 4 is a perspective view of a first tape being applied to the first leadframe panel of FIG. 3;
- FIG. 5 is an enlarged top plan view of a portion of a second leadframe panel in accordance an embodiment of the present invention.
- FIG. 6 is a perspective view of a second tape being applied to the second leadframe panel of FIG. 5;
- FIG. 7 is a perspective view of an integrated circuit die being placed in a die receiving area of the second leadframe panel of FIG. 5;
- FIG. 8 is a perspective view of guide pins being inserbed into holes of the second leadframe panel of FIG. 5 in accordance with an embodiment of the invention
- FIG. 9 is an enlarged cross-sectional view of the first and second leadframe panels being stacked in accordance with an embodiment of the present invention
- FIG. 10 is an enlarged cross-sectional view illustrating a molding step in accordance with an embodiment of the invention
- FIG. 11 is an enlarged perspective view of a portion of one of the first and second leadframe panels in accordance with an embodiment of the, present invention
- FIG. 12 is a perspective view illustrating a de- taping procedure in accordance with an embodiment of the invention
- FIG. 13 is a perspective view illustrating a dicing procedure in accordance with an embodiment of the present invention
- FIG. 14 is an enlarged cross-sectional view of the semiconductor device of FIG. 1; and [0019] FIG. 15 is an enlarged top plan view of a lead finger of a first leadframe of the leadframe panel of FIG. 3 in accordance with an embodiment of the invention.
- the present invention is a semiconductor device made with two separate leadframes.
- the device has a first leadframe having a perimeter that defines a cavity and a plurality of leads extending inwardly from the perimeter.
- the second leadframe has a top surface and a bottom surface and a die paddle surrounding a die receiving area.
- An integrated circuit (IC) is disposed within the die receiving area of the second leadframe.
- the IC has a plurality of bonding pads located on a peripheral portion of its first surface.
- the first leadframe and the second leadframe are in facing relation such that the leads of the first leadframe are electrically connected to respective ones of the bonding pads of the IC.
- a mold compound is injected between the first and second leadframes and covers the second leadframe top surface and a central area of the first surface of the IC . At least the bottom surfaces of the leads are exposed.
- the present invention further provides a method of packaging a semiconductor device comprising the steps of: [0024] providing a first leadframe having a perimeter that defines a cavity and a plurality of leads extending inwardly from the perimeter, wherein the first leadframe has first and second sides;
- the present invention further provides a method of packaging a plurality of -semiconductor devices, comprising the steps of: [0033] providing a first leadframe panel, the first leadframe panel having a plurality of first leadframes, each of the first leadframes having a perimeter that defines a cavity and a plurality of leads extending inwardly from the perimeter, wherein the first leadframe panel has first and second sides;
- a second leadframe panel including a plurality of second leadframes, each of the second leadframes including a die paddle having a die receiving area, wherein the second leadframe panel has top and bottom surfaces; [0036] applying a second tape to the bottom surface of the second leadframe panel; [0037] placing a plurality of integrated circuits (IC) within respective ones of the die receiving areas of the die paddles of the second, leadframes of the second leadframe panel, each of the ICs having a top surface with a plurality of bonding pads around a perimeter thereof and a bottom surface, wherein the bottom surfaces of the ICs are attached to the second tape;
- IC integrated circuits
- the packaged device 10 houses an integrated circuit (IC) 12 that has an exposed surface (FIG. 1) .
- the integrated circuit 12 may be of a type known to those of skill in the art, such as a circuit formed on and cut from a silicon wafer.
- Typical circuit (die) sizes may range from 2mm x 2mm to 12mm x 12mm and have a thickness ranging from about 3 mils to about 21 mils.
- the packaged device 10 is known as a QFN (Quad Flat No-Lead) package and may range in size from about 3x3 mm to about 12x12 mm.
- the IC 12 may be connected to other circuits or devices via leads 14 that are exposed on the bottom and side surfaces of the packaged device 10.
- a bottom surface of the IC 12 is exposed.
- FIG. 2 shows the bottom side of the packaged device 10.
- a ground plane 15 is exposed on the bottom side, in the embodiment shown, a ground plane 15 is exposed.
- the ground plane 15 is optional.
- the leads 14 are exposed on the bottom side.
- the first leadframe panel 16 includes a plurality of first leadframes 18 connected together with first connection bars 20.
- the first leadframe panel 16 comprises a 3x3 matrix of the first leadframes 18.
- the first leadframe panel 16 may have more or fewer of the first leadframes 18.
- Each of the first leadframes 18 has a perimeter (i.e. the first connection bars 20) that defines a cavity 22 and a plurality of leads 14 extending inwardly from the perimeter.
- the cavity 22 is shown in dashed lines.
- the embodiment shown includes the ground plan 15, which is located inside the cavity 22.
- the ground plane 15 provides common electrical grounding for the IC 1 .
- the grounding plane 15 also provides a solderable area that further enhances the board level solder joint strength. As previously discussed, the ground plane 15 is an optional feature.
- the size and shape, as well as the number of leads 14, of the first leadframe is determined based on the size, shape and number of bonding pads of the IC 12. Although the leads 14 are shown as being of generally the same length and width, the leads 14 may vary in length and width. For example, leads used for power and ground may be wider than signal leads. [0045]
- the first leadframe panel 16 has first and second sides. In FIG. 3, the first side is shown.
- the first leadframe panel 16 also includes a plurality of spaced first holes 24 located along its perimeter.
- the first leadframe panel 16 is preferably formed of a metal or metal alloy and has a first predetermined thickness.
- the first leadframe panel 16 may comprise copper and be formed by cutting, stamping or etching as known by those of skill in the art.
- the first leadframe panel 16 is formed of copper that is pre-plated with tin.
- FIG. 4 shows another first leadframe panel 17 having three 5x5 matrices of the first leadframes 18. Otherwise, the first leadframe panel 17 is the same as the first leadframe panel 16.
- the first leadframe panel 17 (or 16) has a first tape 26 applied to a first side thereof.
- the first tape 26 is of a type known to those of skill in the art typically used in semiconductor packaging operations that can withstand high temperatures.
- the first tape 26 has an adhesive or glue on one side that allows it to stick to the first leadframe panel 17.
- FIG. 5 is an enlarged top plan view of a portion of a second leadframe panel 30 in accordance with the present invention.
- the second leadframe panel 30 includes a plurality of second leadframes 32.
- FIG. 5 shows a portion of the second leadframe panel 30 including a 3x3 matrix of the second leadframes 32.
- the second leadframe panel 30 may include a number of various size matrices and is not limited to 3x3.
- the second leadframes 32 are connected together with second connection bars 34.
- Each of the second leadframes 32 comprises a die paddle surrounding a cavity or die receiving area 36.
- the second leadframes 32 also have first and second or top and bottom surfaces and a second thickness.
- the die receiving area 36 is sized and shaped to receive the IC 12.
- the die receiving area 36 is rectangular shaped too.
- the die receiving area 36 may be slightly larger than the IC 12. As shown in FIG. 1, the IC 12 fits snugly within the die receiving area 36. As will be understood by those of skill in the art, the IC 12 may be placed within the die receiving area 36 using commercially available die placement equipment.
- the second leadframe 32 has a cavity for receiving the IC 12, the second leadframe 32 could have a solid die paddle area such the IC 12 would be placed on (and attached to) the die paddle.
- the second leadframe panel 30 also includes a plurality of spaced, second holes 38 located along its perimeter. The holes 38 may be formed by any suitable method, such as punching. As discussed in more detail below, when the first and second leadframe panels 16 and 30 are stacked, the first holes 24 line up with the second holes 38.
- FIG. 6 shows a second leadframe panel 31 having three 5x5 matrices of the second leadframes 32. Otherwise, the second leadframe panel 31 is the same as the second leadframe panel 30 (FIG. 5) .
- the second leadframe panel 31 (or 30) has a second tape 40 applied to a bottom side thereof.
- the second tape 40 like the first tape 26, is of a type known to those of skill in the art typically used in semiconductor packaging operations that can withstand high temperatures.
- the second tape 40 has an adhesive or glue on one side that allows it to stick to the second leadframe panel 31.
- the second tape 40 protects the bottom surface of the second leadframe panel 30 or 31 from mold resin bleeding (described below) .
- the second tape 40 also holds the ICs 12 inside the die receiving areas 36 of the second leadframes 32.
- the second leadframe panel 30 is preferably formed of a metal or metal alloy, and may be formed by cutting, stamping or etching as known by those of skill in the art. For more complex and higher density leadframes, a chemical etching method is preferred. As is understood by those of skill in the art, the etching method uses an artwork mask to define the detailed pattern of the leadframe and then the unmasked portion of the metal is etched away. A plating mask is used to mask out no- plating zones, if any, and then the unmasked portions are plated with metal layers with a plating process. Rinsing and cleaning steps are performed between processes. Such masking, etching, plating, rinsing and cleaning processes are well known to those of skill in the art.
- FIG. 7 shows a step of placing the ICs 12 in the die receiving areas 36 of the second leadframes 32. If the die receiving area 36 is a cavity, then the IC 12 is placed inside the cavity where it adheres to the surface of the second tape 40. That is, a bottom surface of the IC 12 adheres to the glue or adhesive of the second tape 40. If the die receiving area 36 is a location within the second leadframe 32, but not a cavity (i.e., a solid die paddle), then an adhesive or die attach material is used to secure the IC 12 to the die paddle of the second leadframe 32.
- a cavity i.e., a solid die paddle
- the IC 12 has a first or bottom side that adheres to either the second tape 40 or the die paddle and a second or topside that has a plurality of bonding pads spaced around its perimeter. As previously discussed, currently available pick and place equipment is able to place integrated circuits in predetermined locations . [0051] After the second leadframe panel 31 is populated with ICs 12, the first and second leadframe panels 17 and 31 are placed in facing relationship such that the bonding pads of the ICs 12 contact respective ones of the leads 14 of the first leadframes 18 such that the bonding pads make an electrical connection with the leads 14.
- FIG. 8 shows the second leadframe panel 31 with guide pins 42 inserted in the second holes 38.
- FIGS. 9 and 10 the first and second leadframe panels 17 and 31 are placed in facing relationship such that the bonding pads of the ICs 12 contact respective ones of the leads 14 of the first leadframes 18, thereby electrically connecting the ICs 12 and the first leadframes 18.
- FIG. 9 is an enlarged cross-sectional view of the first and second leadframe panels 17 and 31 being aligned, one over the other, such that the bonding pads on the top surfaces of the ICs 12 will contact with the leads 14 of the first leadframes 18.
- FIG. 9 is an enlarged cross-sectional view of the first and second leadframe panels 17 and 31 being aligned, one over the other, such that the bonding pads on the top surfaces of the ICs 12 will contact with the leads 14 of the first leadframes 18.
- the 10 is an enlarged cross-sectional view of one of the ICs 12 after it has been placed in contact with a corresponding one of the leadframes 18 and placed in a mold prior to a molding or encapsulation procedure.
- the guide pins 42 extend through the first and second holes 24 and 38 in the first and second leadframe panels 17 and 31, ensuring precise alignment of the panels.
- the leads 14 may directly contact the bonding pads 44 or as is presently preferred, conductive balls 46 are interposed between respective ones of the bonding pads 44 of the ICs 12 and the leads 14 of the first leadframes 18. The leads 14 are thus electrically coupled to the bonding pads 44 via the conductive balls 46.
- the conductive balls 46 are attached to the bonding pads 44 prior to placing the first and second leadframe panels 17 and 31 in facing relationship.
- the conductive balls 46 may be formed of any material that readily conducts an electrical signal. However, it is preferred that the conductive balls 46 are formed of tin solder. Another suitable material is gold.
- the conductive balls 46 may be attached to the bonding pads 44 via electroplating, screen-printing, or gold ball bonding. [0054] Referring to F ⁇ G. 15, a top plan view of four of the leads 14 projecting from one of the connection bars 20 are shown. Each of the leads 14 preferably includes a partially etched portion 60 and an etched trench or groove 62 near a distal end of the lead 14.
- the trench or groove portion 62 aids in aligning and securing the conductive ball 46 with the lead 14.
- the etched portions 60 of the leads 14 allow the leads 14 to bend or deform when the balls 46 are pressed thereagainst .
- Pre-plating of the first leadframe 18 with tin facilitates reflow of the conductive balls 46 without the application of solder paste or flux.
- the stacked leadframes 17 and 31 may be passed through a reflow oven so that the pre-plated tin on the leads 14 will melt and form a solder joint with the conductive balls 46.
- a mold compound e.g., the mold compound 50 described below
- a molding operation is performed for forming a mold compound between the first and second leadframe panels 17 and 31 such that a mold compound 50 injected between the leadframe panels 17 and 31 covers at least the top surface of the second leadframe panel 17, the top surface of the ICs 12, and the electrical connections.
- the mold compound 50 may comprise a plastic as is commonly used in packaged electronic devices .
- Top and bottom mold pieces 52 and 54 press t ie first and second leadframe panels 17 and 31 together to insure good electrical connection between the bonding pads 44 and the leads 14 via the conductive balls 46.
- the first and second leadframes 17 and 31 are electrically isolated from each other.
- one of both of the leadframe panels 17 and 31 may be partially etched to allow for injecting the mold compound 50 between the leadframe panels 17 and 31.
- FIG. 11 shows the second leadframe panel 31 being partially etched to form a passage 56 for the mold compound 50.
- the first and second tapes 26 and 40 prevent resin or mold compound bleeding during a molding or encapsulation process .
- FIG. 12 after the molding operation is completed, the first tape 26 is removed from the first leadframe panel 17 and the second tape 40 is removed from the second leadframe panel 31.
- the tapes 26 and 40 may be removed manually or with automated equipment that is presently commercially available.
- FIG. 14 is an enlarged cross-sectional view of a finished device 10.
- a packaged device was constructed using an integrated circuit 12 having a thickness of about 11 mils as indicated at A.
- the first leadframe 18 had a thickness of about 8 mils, as indicated at B and the conductive balls 46 had a thickness or diameter of about 3 mils as indicated at C.
- the three thicknesses, A, B and C add up to 22 mils.
- the device 10 due to the pressure exerted on the device 10 during the molding operation by the top and bottom molds 52 and 54, the device 10 has an overall thickness of about 20 mils. That is, a mechanical compressive force acts on (and continues to act on) the leads 14.
- the portion of the lead 14 with the partial etch feature 60 is bent downward and has a spring back force that continues to push on or press the conductive balls 46 against the bonding pads 44. This mechanical spring back force enhances the joint strength between the conductive balls 46, the leads 14, and the bonding pads 44.
- the first and second leadframes 18 and 32 may be of different thicknesses.
- the second leadframe 32 to which an IC may be attached can be used as a heat sink.
- the second thickness is greater than the first thickness.
- the first leadframe 18 could be thinner to facilitate saw singulation.
- the second leadframe 32 may be thicker than the first leadframe 18.
- FIG. 14 also shows the ground plane 15.
- the IC 12 may be electrically connected with the ground plane 15 with conductive balls 58 that have a smaller diameter than the conductive balls 46.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006549619A JP4633740B2 (en) | 2004-01-07 | 2005-01-03 | Flip-chip QFN package and method therefor |
KR1020067013745A KR101120733B1 (en) | 2004-01-07 | 2005-01-03 | Flipchip qfn package and method therefor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/752,866 US6867072B1 (en) | 2004-01-07 | 2004-01-07 | Flipchip QFN package and method therefor |
US10/752,866 | 2004-01-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2005067526A2 true WO2005067526A2 (en) | 2005-07-28 |
WO2005067526A3 WO2005067526A3 (en) | 2005-11-17 |
Family
ID=34274886
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2005/001202 WO2005067526A2 (en) | 2004-01-07 | 2005-01-03 | Flipchip qfn package and method therefore |
Country Status (6)
Country | Link |
---|---|
US (2) | US6867072B1 (en) |
JP (1) | JP4633740B2 (en) |
KR (1) | KR101120733B1 (en) |
CN (1) | CN100378934C (en) |
TW (1) | TWI348768B (en) |
WO (1) | WO2005067526A2 (en) |
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-
2005
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- 2005-01-03 CN CNB200580003941XA patent/CN100378934C/en not_active Expired - Fee Related
- 2005-01-03 KR KR1020067013745A patent/KR101120733B1/en not_active IP Right Cessation
- 2005-01-03 WO PCT/US2005/001202 patent/WO2005067526A2/en active Application Filing
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Also Published As
Publication number | Publication date |
---|---|
KR20060123454A (en) | 2006-12-01 |
TWI348768B (en) | 2011-09-11 |
WO2005067526A3 (en) | 2005-11-17 |
JP2007518282A (en) | 2007-07-05 |
US6867072B1 (en) | 2005-03-15 |
CN100378934C (en) | 2008-04-02 |
KR101120733B1 (en) | 2012-03-23 |
TW200534492A (en) | 2005-10-16 |
CN1914719A (en) | 2007-02-14 |
US7112871B2 (en) | 2006-09-26 |
JP4633740B2 (en) | 2011-02-16 |
US20050156291A1 (en) | 2005-07-21 |
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