WO2005067030A1 - Support system for semiconductor wafers and methods thereof - Google Patents

Support system for semiconductor wafers and methods thereof Download PDF

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Publication number
WO2005067030A1
WO2005067030A1 PCT/US2004/043517 US2004043517W WO2005067030A1 WO 2005067030 A1 WO2005067030 A1 WO 2005067030A1 US 2004043517 W US2004043517 W US 2004043517W WO 2005067030 A1 WO2005067030 A1 WO 2005067030A1
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WO
WIPO (PCT)
Prior art keywords
support system
wafer
semiconductor wafer
wafer support
gas pressure
Prior art date
Application number
PCT/US2004/043517
Other languages
French (fr)
Inventor
Brian Wilk
Frank Joyce
Douglas Kreager
Thomas A. Repko
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to JP2006547434A priority Critical patent/JP4408900B2/en
Priority to DE112004002610T priority patent/DE112004002610T5/en
Publication of WO2005067030A1 publication Critical patent/WO2005067030A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/27—Work carriers
    • B24B37/30—Work carriers for single side lapping of plane surfaces
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/53—Means to assemble or disassemble
    • Y10T29/53961—Means to assemble or disassemble with work-holder for assembly

Definitions

  • a semiconductor wafer goes through different processes before its individual dies are packaged
  • a non-exhaustive list of examples for such processes are wafer back side grinding, wafer back side metallization, wafer dicing by laser and saw, testing, good die marking, die ejection and die placement on a tape.
  • the wafer may need to be mechanically supported during processing.
  • the wafer may also need to be transported between process tools in a fabrication plant (FAB) or a packaging facility.
  • a semiconductor wafer may have a diameter of, for example, 300 millimeters, and a thickness of, for example, 762 micrometers. After back side grinding, the wafer thickness may be reduced, for example, to a thickness in the range of approximately 50 to approximately 100 micrometers A wafer with such a thickness may be fragile and may require careful handling.
  • FIG. 1 is an exploded view of an exemplaiy semiconductor wafer and an exemplary wafer support system, in accordance with some embodiments of the invention
  • FIG. 2 is a cross-sectional view of part of the semiconductor wafer of FIG. 1 and part of the wafer support system of FIG. 1, in accordance with some embodiments of the invention
  • FIG 3 is a cross-sectional view of pait of the wafer support system of FIG. 1, in accordance with some embodiments of the invention.
  • FIG 4 is a flowchart illustration of a method for securing a semiconductor wafer to a wafei support system, in accordance with some embodiments of the invention.
  • FIG, 5 is a flowchart illustration of another method for seeming a semiconductor wafer to a wafer support system, in accordance with some embodiments of the invention.
  • FIG 6 is a flowchart illustration of yet another method for securing a semiconductor wafer to a wafer support system, in accordance with some embodiments of the invention.
  • FIG 7 is a flowchart illustration of a further method for securing a semiconductor wafer to a wafer support system, in accordance with some embodiments of the invention.
  • FIGs 8 A, 8B, 8C and 8D are flowchart illustrations of alternate methods for releasing a semiconductor wafer from a wafer support system, in accordance with some embodiments of the invention
  • FIG. 1 is an exploded view of semiconductor wafer 2 and wafer support system 4, while FIG. 2 is a cioss-sectional view of part of semiconductor wafer 2 and part of wafer support system 4 along a cross-section A, and FIG. 3 is a cioss-sectional view of part of wafer support system 4 along a cross-section B.
  • semiconductor wafer 2 may have a disk shape, although any other shape of semiconductor wafer 2 is also contemplated.
  • Semiconductor wafer 2 may include dies, such as exemplary dies 6, separated by scribe lines (also known as "streets"), such as exemplary scribe lines 8. Dies 6 may have a rectangular shape, although any other shape of dies 6 is also contemplated. Moreover, although not shown explicitly in FIG. 1, semiconductor wafer 2 may include dies of different shapes and sizes.
  • Semiconductor wafei 2 may go through different processes, such as, for example, surface grinding and surface metallization.
  • particular dies 6 " such as foi example, the die denoted 6" may be sawed out of semiconductor wafer 2 by, foi example, a laser saw or a mechanical saw.
  • Sawed die 6" may be ejected from semiconductor wafei 2 and may be placed on a tape (not shown) [001 ]
  • a non-exhaustive list of examples for the diametei of semiconductor wafer 2 includes approximately 150 millimeters, approximately 200 millimeters and approximately 00 millimeters.
  • Semiconductor wafer 2 may have a thickness in the lange.
  • Wafer support system 4 may have a substantially rigid perforated surface 10 having openings 12. Openings 12 may be concentrated in an area defined by a curve 14 having substantially the same shape as semiconductor wafer 2. Openings 12 may have a substantially round shape, although any other shape of openings 12 is also contemplated.
  • Semiconductor wafer 2 may be secured to wafer support system 4 by placing a supported surface 16 of semiconductor wafer 2 in contact with perforated surface 10 so that openings 12 are substantially blocked by semiconductor wafer 2, and in addition, by causing an exposed surface 18 of semiconductor wafer 2 to be at a gas pressuie higher than a gas pressure applied to supported surface 16 through openings
  • semiconductor wafer 2 While semiconductor wafer 2 is secured to wafer support system 4, semiconductor wafer 2 may be transported together with wafer support system 4
  • wafer support system 4 processes such as, for example, wafer back side grinding, wafer back side metallization, wafer dicing by laser and saw, testing, good die marking, die ejection and die placement on a tape, may be applied to semiconductor wafer 2.
  • the rigidity of perforated surface 10 may reduce or eliminate flexing of semiconductor wafer 2 during handling, transporting and processing.
  • Secured semiconductor wafer 2 may be released from wafer support system 4 by causing exposed surface 18 to be at a gas pressure lower than or substantially equal to the gas pressuie applied to supported surface 16 through openings 12.
  • one oi more sawed dies of secured semiconductor wafer 2 such as, for example, die 6
  • Sawed die 6 after being released from wafer support system 4, may be separated from wafer support system 4 by a die picking tool (not shown). Since there is no adhesive holding sawed die 6" to wafei support system 4, the removal of sawed die 6" with a die picking tool does not involve the pulling, peeling or prying generally requiied to remove a die from an adhesive surface.
  • wafer support system 4 may include a first part that is a substantially ligid perforated plate 30 having perforated surface 10 and openings 12
  • wafer support system 4 may include a second part 32 having multiple cavities 34
  • cavities 34 may be arranged in a honeycomb structure, although any other arrangement of cavities is also contemplated.
  • cavities 34 may have a hexagonal shape, although any other shape of cavity 34, such as, for example, a rectangle, a ciicle, and the like is also contemplated.
  • part 32 may have a coriesponding cavity 34.
  • a cavity 34" may correspond to opening 12"
  • part 32 may have multiple corresponding cavities 34.
  • perforated plate for every cavity 34 in part 32, perforated plate
  • the number, size, shape and a ⁇ angement of cavities 34 may be chosen to suit the arrangement of dies on the semiconductor wafer.
  • a smallest of cavities 34 may be substantially equivalent in area to an area of a smallest of dies on semiconductor wafer 2.
  • Cavities 34 may have orifices 36 on a surface 38 of part 32. According to one embodiment of the invention, a cavity 34 may have one corresponding orifice 36.
  • a cavity 34 may have more than one coriesponding orifice 36
  • Peiforated plate 30 and part 32 may be attached so that a surface 40 of perforated plate 30 and a suiface 42 of part 32 are touching.
  • perforated plate 30 and part 32 may be manufactured as a single body having surface 10 with openings 12 and an opposite surface 38 with orifices 36, wheie the openings and orifices are joined by cavities
  • Gas may be substantially trapped inside cavities 34 if a, supported surface 16 of semiconductor wafer 2 is in contact with perfoiated surface 10 so that openings 12 are substantially blocked by seraiconductoi wafer 2, with perforated plate 30 functioning substantially as a gasket between supported surface 16 and surface 42 of part 32, and b. a membrane 50 is attached to part 32 so that orifices 36 are substantially sealed
  • Gas trapped in cavities 34 may apply force to supported surface 16 through openings 12
  • gas that is external to cavities 34 may apply force to exposed surface 18
  • FIG. 4 is a flowchart illustration of a method for securing semiconductor wafer 2 to wafer support system 4, in accordance with some embodiments of the invention.
  • Semiconductor wafer 2 and wafer support system 4 may be placed in a first environment, for example, a vacuum chamber, with supported surface 16 placed in contact with perfoiated surface 10 so that openings 12 are substantially blocked (-402- ).
  • the gas pressure inside the first environment may be reduced (-404-).
  • Membrane 50 may be attached to part 32 so that orifices 36 are substantially sealed (-406-).
  • FIG. 5 is a flowchart illustration of another method for securing semiconductor wafer 2 to wafer support system 4, in accordance with some embodiments of the invention.
  • Membrane 50 may be flexible and may be attached to part 32 so that orifices 36 are substantially sealed (-502-). Membrane 50 may be pushed inwards into cavities 34 (-504-).
  • supported surface 16 may be placed in contact with perforated surface 10 so that openings 12 are substantially blocked (-506- ), and membrane 50 may be released so it is no longer pushed into cavities 34 (-508-). Consequently, the gas pressure inside cavities 34 may be lower than the gas pressure on exposed surface 18.
  • FIG 6 is a flowchart illustration of another method for securing semiconductor wafer 2 to wafer support system 4, in accordance with some embodiments of the invention.
  • part 32 may optionally have perimeter walls 54, extending beyond surface 38, and membrane 50 may be rigid, Membiane 50 may be attached to part 32 so that orifices 36 are substantially sealed (-602-).
  • Supported surface 16 may be placed in contact with perforated surface 10 so that openings 12 are substantially blocked (-604-).
  • membiane 50 may be pulled away from surface 38 so membrane 50 is still within perimeter walls 54 to form a void 56 (-606-), Void 56 and cavities 34 may be sealed by membrane 50 and perimetei walls 54.
  • FIG 7 is a flowchart illustration of a further method for securing semiconductor wafei 2 to wafei support system 4, in accordance with some embodiments of the invention
  • Semiconductor wafer 2 and wafer support system 4 may be placed in a first environment at a first temperature, with supported surface 16 placed in contact with perforated surface 10 so that openings 12 are substantially blocked (-702-).
  • FIGs 8A, 8B. 8C and 8D are flowchart illustrations of alternate methods for releasing semiconductor wafer 2 from wafer support system 4, in accordance with some embodiments of the invention.
  • membrane 50 may be removed from wafer support system 4 (- 802-) to cause the gas pressure inside cavities 34 to become substantially equal to the gas pressure on exposed surface 18, thus releasing semiconductor wafer 2 from wafer support system.
  • membrane 50 may be pierced (-804-), and the gas pressure inside cavities 34 may become equal to the gas pressure on exposed surface 18
  • one or more sawed dies may be individually released from wafer support system 4.
  • sawed die 6" may be individually released fi om wafer support system 4 by piercing flexible membrane 50 into orifice 36 M in such a way that the gas pressure in cavity 34" may become equal or higher than the gas pressure suirounding wafei support system 4, and the gas pressure in the other cavities 34 may not be affected
  • membrane 50 may be pushed inwards into cavities 34 (-806-), and the gas pressure inside cavities 34 may become equal or higher than the gas pressure on exposed surface 18.
  • one oi more sawed dies may be individually released from wafer support system 4.
  • sawed die 6" may be individually released from wafer- support system 4 by pushing flexible membrane 50 into orifice 36" in such a way that the gas piessuie in cavity 34" may become equal or higher than the gas pressure suirounding wafer support system 4, and the gas pressure in the other cavities 34 may not be affected
  • FIG 8D is applicable, for example, in the event that part 32 has perimetei walls 54 extending beyond surface 38 and membrane 50 is rigid membrane. Membrane 50 may be moved inwards toward surface 38 (-808-). The gas pressure inside cavities 34 and void 56 may increase and may become equal or higher than the gas piessuie on exposed surface 18.

Abstract

A semiconductor wafer goes through different processes before its individual dies are packaged. A non-exhaustive list of examples for such processes are wafer back side grinding, wafer back side metallization, wafer dicing by laser and saw, testing, good die marking, die ejection and die placement on a tape. The wafer may need to be mechanically supported during processing. The wafer may also need to be transported between process tools in a fabrication plant (FAB) or a packaging facility. A semiconductor wafer may have a diameter of, for example, 300 millimeters, and a thickness of, for example, 762 micrometers. After back side grinding, the wafer thickness may be reduced, for example, to a thickness in the range of approximately 50 to approximately 100 micrometers. A wafer with such a thickness may be fragile and may require careful handling.

Description

SUPPORT SYSTEM FOR SEMICONDUCTOR WAFERS AND METHODS THEREOF
BACKGROUND OF THE INVENTION
[0001] A semiconductor wafer goes through different processes before its individual dies are packaged A non-exhaustive list of examples for such processes are wafer back side grinding, wafer back side metallization, wafer dicing by laser and saw, testing, good die marking, die ejection and die placement on a tape. The wafer may need to be mechanically supported during processing. The wafer may also need to be transported between process tools in a fabrication plant (FAB) or a packaging facility. [0002] A semiconductor wafer may have a diameter of, for example, 300 millimeters, and a thickness of, for example, 762 micrometers. After back side grinding, the wafer thickness may be reduced, for example, to a thickness in the range of approximately 50 to approximately 100 micrometers A wafer with such a thickness may be fragile and may require careful handling.
BRIEF DESCRIPTION OF THE DRAWINGS [0003] Embodiments of the invention are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals indicate corresponding, analogous or similar elements, and in which:
[0004] FIG. 1 is an exploded view of an exemplaiy semiconductor wafer and an exemplary wafer support system, in accordance with some embodiments of the invention;
[0005] FIG. 2 is a cross-sectional view of part of the semiconductor wafer of FIG. 1 and part of the wafer support system of FIG. 1, in accordance with some embodiments of the invention;
[0006] FIG 3 is a cross-sectional view of pait of the wafer support system of FIG. 1, in accordance with some embodiments of the invention;
[0007] FIG 4 is a flowchart illustration of a method for securing a semiconductor wafer to a wafei support system, in accordance with some embodiments of the invention;
[0008] FIG, 5 is a flowchart illustration of another method for seeming a semiconductor wafer to a wafer support system, in accordance with some embodiments of the invention;
[0009] FIG 6 is a flowchart illustration of yet another method for securing a semiconductor wafer to a wafer support system, in accordance with some embodiments of the invention;
[0010] FIG 7 is a flowchart illustration of a further method for securing a semiconductor wafer to a wafer support system, in accordance with some embodiments of the invention; and
[001 1] FIGs 8 A, 8B, 8C and 8D are flowchart illustrations of alternate methods for releasing a semiconductor wafer from a wafer support system, in accordance with some embodiments of the invention
[0012] It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of tire elements may be exaggerated relative to other elements for clarity DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION [003 ] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the invention However it will be understood by those of ordinary skill in the art that the embodiments of the invention may be practiced without these specific details. In other instances, well- known methods, procedures, components and circuits have not been described in detail so as not to obscure the embodiments of the invention.
[0014] Refeiring to FIG 1 and FIG, 2, an exemplary semiconductor wafei 2 and a wafer support system 4 in accordance with some embodiments of the invention is illustiated. FIG. 1 is an exploded view of semiconductor wafer 2 and wafer support system 4, while FIG. 2 is a cioss-sectional view of part of semiconductor wafer 2 and part of wafer support system 4 along a cross-section A, and FIG. 3 is a cioss-sectional view of part of wafer support system 4 along a cross-section B. [0015] As shown in FIG. 1, semiconductor wafer 2 may have a disk shape, although any other shape of semiconductor wafer 2 is also contemplated. Semiconductor wafer 2 may include dies, such as exemplary dies 6, separated by scribe lines (also known as "streets"), such as exemplary scribe lines 8. Dies 6 may have a rectangular shape, although any other shape of dies 6 is also contemplated. Moreover, although not shown explicitly in FIG. 1, semiconductor wafer 2 may include dies of different shapes and sizes.
[0016] Semiconductor wafei 2 may go through different processes, such as, for example, surface grinding and surface metallization. In addition, particular dies 6", such as foi example, the die denoted 6", may be sawed out of semiconductor wafer 2 by, foi example, a laser saw or a mechanical saw. Sawed die 6" may be ejected from semiconductor wafei 2 and may be placed on a tape (not shown) [001 ] A non-exhaustive list of examples for the diametei of semiconductor wafer 2 includes approximately 150 millimeters, approximately 200 millimeters and approximately 00 millimeters. Semiconductor wafer 2 may have a thickness in the lange. for example, of appioximately 700 micrometers to approximately 800 micrometers, such as, for example, a thickness of approximately 762 micrometers A surface grinding piocess may reduce the thickness of semiconductor wafer 2 to a thickness in the range, for example, of approximately 50 to approximately 100 micrometeis. [0018] Wafer support system 4 may have a substantially rigid perforated surface 10 having openings 12. Openings 12 may be concentrated in an area defined by a curve 14 having substantially the same shape as semiconductor wafer 2. Openings 12 may have a substantially round shape, although any other shape of openings 12 is also contemplated.
[001 ] Semiconductor wafer 2 may be secured to wafer support system 4 by placing a supported surface 16 of semiconductor wafer 2 in contact with perforated surface 10 so that openings 12 are substantially blocked by semiconductor wafer 2, and in addition, by causing an exposed surface 18 of semiconductor wafer 2 to be at a gas pressuie higher than a gas pressure applied to supported surface 16 through openings
12.
[0020] While semiconductor wafer 2 is secured to wafer support system 4, semiconductor wafer 2 may be transported together with wafer support system 4
Moreover, while semiconductor wafer 2 is secured to wafer support system 4, processes such as, for example, wafer back side grinding, wafer back side metallization, wafer dicing by laser and saw, testing, good die marking, die ejection and die placement on a tape, may be applied to semiconductor wafer 2. The rigidity of perforated surface 10 may reduce or eliminate flexing of semiconductor wafer 2 during handling, transporting and processing.
[0021] Secured semiconductor wafer 2 may be released from wafer support system 4 by causing exposed surface 18 to be at a gas pressure lower than or substantially equal to the gas pressuie applied to supported surface 16 through openings 12.
[0022] Moreover, one oi more sawed dies of secured semiconductor wafer 2, such as, for example, die 6", may be released from wafer support system 4 by increasing the gas pressure applied to supported surface 16 through openings that are blocked by those sawed dies, for example, opening 12", while maintaining the gas pressure applied to supported surface 16 through other openings 12. Sawed die 6", after being released from wafer support system 4, may be separated from wafer support system 4 by a die picking tool (not shown). Since there is no adhesive holding sawed die 6" to wafei support system 4, the removal of sawed die 6" with a die picking tool does not involve the pulling, peeling or prying generally requiied to remove a die from an adhesive surface.
[0023] As shown in FIG. 2, wafer support system 4 may include a first part that is a substantially ligid perforated plate 30 having perforated surface 10 and openings 12
In addition, wafer support system 4 may include a second part 32 having multiple cavities 34
[0024] As shown in FIG. 3, cavities 34 may be arranged in a honeycomb structure, although any other arrangement of cavities is also contemplated. For example, cavities 34 may have a hexagonal shape, although any other shape of cavity 34, such as, for example, a rectangle, a ciicle, and the like is also contemplated.
[0025] According to a fust embodiment of the invention, for every opening 12 in perforated plate 30, part 32 may have a coriesponding cavity 34. For example, a cavity 34" may correspond to opening 12",
[0026] According to a second embodiment of the invention, for every opening 12 in perforated plate 30, part 32 may have multiple corresponding cavities 34. According to a third embodiment of the invention, for every cavity 34 in part 32, perforated plate
30 may have multiple openings 12
[0027] The number, size, shape and aπangement of cavities 34 may be chosen to suit the arrangement of dies on the semiconductor wafer. In addition, a smallest of cavities 34 may be substantially equivalent in area to an area of a smallest of dies on semiconductor wafer 2.
[0028] Cavities 34 may have orifices 36 on a surface 38 of part 32. According to one embodiment of the invention, a cavity 34 may have one corresponding orifice 36.
According to a second embodiment of the invention, a cavity 34 may have more than one coriesponding orifice 36
[0029] Peiforated plate 30 and part 32 may be attached so that a surface 40 of perforated plate 30 and a suiface 42 of part 32 are touching. Alternatively, perforated plate 30 and part 32 may be manufactured as a single body having surface 10 with openings 12 and an opposite surface 38 with orifices 36, wheie the openings and orifices are joined by cavities
[0030] Gas may be substantially trapped inside cavities 34 if a, supported surface 16 of semiconductor wafer 2 is in contact with perfoiated surface 10 so that openings 12 are substantially blocked by seraiconductoi wafer 2, with perforated plate 30 functioning substantially as a gasket between supported surface 16 and surface 42 of part 32, and b. a membrane 50 is attached to part 32 so that orifices 36 are substantially sealed
[0031] Gas trapped in cavities 34 may apply force to supported surface 16 through openings 12 In addition, gas that is external to cavities 34 may apply force to exposed surface 18
[0032] FIG. 4 is a flowchart illustration of a method for securing semiconductor wafer 2 to wafer support system 4, in accordance with some embodiments of the invention, Semiconductor wafer 2 and wafer support system 4 may be placed in a first environment, for example, a vacuum chamber, with supported surface 16 placed in contact with perfoiated surface 10 so that openings 12 are substantially blocked (-402- ). The gas pressure inside the first environment may be reduced (-404-). Membrane 50 may be attached to part 32 so that orifices 36 are substantially sealed (-406-). Then, wafei support system 4 and semiconductor wafer 2 may be removed from the first environment to a second environment at a gas pressure higher than the gas pressure inside the first envhonment (-408-) Consequently, the gas pressure inside cavities 34 may be lower than the gas pressure on exposed surface 18. [0033] FIG. 5 is a flowchart illustration of another method for securing semiconductor wafer 2 to wafer support system 4, in accordance with some embodiments of the invention. Membrane 50 may be flexible and may be attached to part 32 so that orifices 36 are substantially sealed (-502-). Membrane 50 may be pushed inwards into cavities 34 (-504-). Then, supported surface 16 may be placed in contact with perforated surface 10 so that openings 12 are substantially blocked (-506- ), and membrane 50 may be released so it is no longer pushed into cavities 34 (-508-). Consequently, the gas pressure inside cavities 34 may be lower than the gas pressure on exposed surface 18.
[0034] FIG 6 is a flowchart illustration of another method for securing semiconductor wafer 2 to wafer support system 4, in accordance with some embodiments of the invention. In some embodiments of the invention, part 32 may optionally have perimeter walls 54, extending beyond surface 38, and membrane 50 may be rigid, Membiane 50 may be attached to part 32 so that orifices 36 are substantially sealed (-602-). Supported surface 16 may be placed in contact with perforated surface 10 so that openings 12 are substantially blocked (-604-). Then, membiane 50 may be pulled away from surface 38 so membrane 50 is still within perimeter walls 54 to form a void 56 (-606-), Void 56 and cavities 34 may be sealed by membrane 50 and perimetei walls 54. Consequently, the gas pressure inside cavities 34 and void 56 may be lower than the gas pressure on exposed surface 18 [0035] FIG 7 is a flowchart illustration of a further method for securing semiconductor wafei 2 to wafei support system 4, in accordance with some embodiments of the invention Semiconductor wafer 2 and wafer support system 4 may be placed in a first environment at a first temperature, with supported surface 16 placed in contact with perforated surface 10 so that openings 12 are substantially blocked (-702-). Membrane 50 may be attached to part 32 so that orifices 36 are substantially sealed (-704-) Then, wafer support system 4 and semiconductor wafer 2 may be removed from the first environment to a second environment at a second temperature that is lower than the first temperature (-706-) Since the air in the first environment is less dense than that in the second environment, once wafer support system 4 and semiconductor wafei 2 are in the second environment, the air pressure inside cavities 34 may be lower than the air pressure on exposed surface 18 [0036] FIGs 8A, 8B. 8C and 8D are flowchart illustrations of alternate methods for releasing semiconductor wafer 2 from wafer support system 4, in accordance with some embodiments of the invention.
[0037] In FIG 8A, membrane 50 may be removed from wafer support system 4 (- 802-) to cause the gas pressure inside cavities 34 to become substantially equal to the gas pressure on exposed surface 18, thus releasing semiconductor wafer 2 from wafer support system.
[0038] In FIG. 8B, membrane 50 may be pierced (-804-), and the gas pressure inside cavities 34 may become equal to the gas pressure on exposed surface 18 In a modified version of this method, one or more sawed dies may be individually released from wafer support system 4. For example, sawed die 6" may be individually released fi om wafer support system 4 by piercing flexible membrane 50 into orifice 36M in such a way that the gas pressure in cavity 34" may become equal or higher than the gas pressure suirounding wafei support system 4, and the gas pressure in the other cavities 34 may not be affected
[0039] In FIG 8C, if membrane 50 is flexible, membrane 50 may be pushed inwards into cavities 34 (-806-), and the gas pressure inside cavities 34 may become equal or higher than the gas pressure on exposed surface 18. In a modified version of this method, one oi more sawed dies may be individually released from wafer support system 4. For example, sawed die 6" may be individually released from wafer- support system 4 by pushing flexible membrane 50 into orifice 36" in such a way that the gas piessuie in cavity 34" may become equal or higher than the gas pressure suirounding wafer support system 4, and the gas pressure in the other cavities 34 may not be affected
[0040] FIG 8D is applicable, for example, in the event that part 32 has perimetei walls 54 extending beyond surface 38 and membrane 50 is rigid membrane. Membrane 50 may be moved inwards toward surface 38 (-808-). The gas pressure inside cavities 34 and void 56 may increase and may become equal or higher than the gas piessuie on exposed surface 18.
[0041] While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims aie intended to covei all such modifications and changes as fall within the spirit of the invention

Claims

[0042] What is claimed is: 1 A method comprising: securing a semiconductor wafer to a wafer support system by causing a supported surface of said semiconductor wafer to be at a lower gas pressure than an exposed surface of said semiconductor wafer.
2 The method of claim 1, wherein causing said supported surface to be at said lower gas pressure includes at least: placing said supported surface of said semiconductor wafer in contact with a peifoiated surface of said wafer support system inside a vacuum chamber; reducing a gas piessure inside said vacuum chamber to substantially said lower gas pressure; sealing an opposite surface of said wafer support system; and removing said wafei support system and said secured semiconductor wafer from said vacuum chamber
3. The method of claim 1, wherein causing said supported surface to be at said lower gas piessure includes at least: placing said supported surface of said semiconductor wafer in contact with a perforated surface of said wafer support system in a first environment at a first temper atuie; sealing an opposite surface of said wafer support system; and removing said wafer support system and said secured semiconductor wafer from said first environment to a second environment at a second temperature that is lower than said first temperature.
4, The method of claim 1, wherein causing said supported surface to be at said lower gas pressure includes at least: pushing a flexible surface of said wafer support system inwards towards a perforated surface of said wafer support system; placing said supported surface of said semiconductor wafer in contact with said perforated surface of said wafer support system; and releasing said flexible surface.
5, The method of claim 1, wherein causing said supported surface to be at said lowei gas pressuie includes at least: placing said supported surface of said semiconductor wafer in contact with a perfoiated surface of said wafer support system; and pulling an opposite surface of said support system outwards away from said perfoiated surface
6 The method of claim 1 , further comprising: releasing said semiconductor wafer from said wafer support system by increasing said lower gas pressuie
7, The method of claim 6, wherein said supported surface is supported by a perforated surface of said wafer support system, and increasing said lower gas pressure includes at least: removing an opposite surface of said wafer support system.
8 The method of claim 6, wherein increasing said lower gas pressure includes at least: pushing a flexible surface of said wafer support system inwards towards said semiconductor wafer.
9. The method of claim 1, furthei comprising: releasing said semiconductor wafer from said wafer support system by causing said exposed surface to be at a pressure lowei than or substantially equal to said lower gas pressure
10 The method of claim 1 , further comprising: releasing one or moie dies of said semiconductor wafer from said wafer- support system by increasing said lower gas pressuie on the supported surface of said one or moie dies while maintaining said lower gas pressure on the supported surface of other portions of said semiconductor wafer
1 1. The method of claim 10, wherein increasing said lower gas pressure on the supported surface of said one or more dies includes at least: pushing one or more portions of a flexible surface of said wafer support system inwards towards said one or more dies of said semiconductor wafer. 12 The method of claim 10, wherein increasing said lower gas pressure on the supported surface of said one or more dies includes at least: piercing one or more portions of a flexible surface of said wafer support system corresponding to said one or more dies of said semiconductor wafer.
13 The method of claim 10, further comprising: sepaialing one of said one or more dies from said semiconductor wafer by coupling a die picker to the exposed surface of said one of said one or more dies.
14 A wafer support system comprising: a body having a perforated surface to support a semiconductor wafer, said body having multiple cavities between said perforated surface and an opposite surface of said body, wheiein said cavities have orifices to said opposite surface; and a membrane to be attached to said body to seal said orifices.
15 The wafer support system of claim 14, wherein a smallest of said cavities is substantially equivalent in area to an area of a smallest of dies on said semiconductoi wafer.
16 The wafer support system of claim 14, wheiein said cavities have openings to said perforated surface and a number of said cavities substantially equals a number of said openings
17 The wafer support system of claim 14, wherein said body includes at least a first part having said perforated surface and a second part having said opposite surface.
18 The wafei support system of claim 14, wherein said membrane is removable.
19 The wafer support system of claim 14, wherein said membrane is flexible,
20 The wafei support system of claim 14, wherein said membrane is rigid.
21 The wafei support system of claim 14, wherein said perforated surface is rigid.
PCT/US2004/043517 2003-12-31 2004-12-28 Support system for semiconductor wafers and methods thereof WO2005067030A1 (en)

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DE112004002610T DE112004002610T5 (en) 2003-12-31 2004-12-28 Holding system for semiconductor wafers and method thereof

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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7055229B2 (en) * 2003-12-31 2006-06-06 Intel Corporation Support system for semiconductor wafers and methods thereof
WO2007086064A2 (en) * 2006-01-27 2007-08-02 Camtek Ltd Diced wafer adaptor and a method for transferring a diced wafer
DE102009044305A1 (en) * 2009-10-21 2011-05-05 Fooke Gmbh Method for holding and processing a workpiece with clamping plate, and device for stiffening a workpiece with clamping plate
JP5776090B2 (en) * 2010-07-21 2015-09-09 株式会社 天谷製作所 Deposition process
WO2012011581A1 (en) * 2010-07-23 2012-01-26 住友化学株式会社 Fixing jig, fixing method, and honeycomb filter production method
JP5617659B2 (en) * 2011-01-25 2014-11-05 信越化学工業株式会社 Manufacturing method of solar cell
US8376334B1 (en) * 2011-10-26 2013-02-19 Swedcord Development AB Glue free vacuum sealing gasket structure
GB2502303A (en) 2012-05-22 2013-11-27 Applied Microengineering Ltd Method of handling a substrate using a pressure variance
CN102962762A (en) * 2012-12-07 2013-03-13 日月光半导体制造股份有限公司 Bearing disk component for wafer grinding
CN105097501B (en) * 2015-07-09 2017-10-31 无锡中微高科电子有限公司 MPW chip back metal methods
JP7370201B2 (en) * 2019-09-20 2023-10-27 株式会社Ｓｃｒｅｅｎホールディングス Substrate processing equipment
CN114783931B (en) * 2022-04-06 2023-03-21 苏州汉天下电子有限公司 Semiconductor sample wafer bearing table and semiconductor sample wafer probe testing device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4603466A (en) * 1984-02-17 1986-08-05 Gca Corporation Wafer chuck
US20030037400A1 (en) * 2001-08-27 2003-02-27 Applied Materials, Inc. Factory interface particle removal platform
US20030234078A1 (en) * 2002-06-19 2003-12-25 United Microelectronics Corp. Wafer carrier assembly for a chemical mechanical polishing apparatus and a polishing method using the same

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4551192A (en) * 1983-06-30 1985-11-05 International Business Machines Corporation Electrostatic or vacuum pinchuck formed with microcircuit lithography
US4556362A (en) * 1983-12-21 1985-12-03 At&T Technologies, Inc. Methods of and apparatus for handling semiconductor devices
US4535834A (en) * 1984-05-02 1985-08-20 Varian Associates, Inc. Method and apparatus for controlling thermal transfer in a cyclic vacuum processing system
US5584746A (en) * 1993-10-18 1996-12-17 Shin-Etsu Handotai Co., Ltd. Method of polishing semiconductor wafers and apparatus therefor
US5423716A (en) * 1994-01-05 1995-06-13 Strasbaugh; Alan Wafer-handling apparatus having a resilient membrane which holds wafer when a vacuum is applied
CN2218627Y (en) * 1994-10-19 1996-01-31 张允清 Vacuum suction disc type porous sheet stacking machine
JPH09181156A (en) 1995-12-25 1997-07-11 Sony Corp Vacuum chuck
JPH09326385A (en) * 1996-06-04 1997-12-16 Tokyo Electron Ltd Substrate cooling method
US6056632A (en) * 1997-02-13 2000-05-02 Speedfam-Ipec Corp. Semiconductor wafer polishing apparatus with a variable polishing force wafer carrier head
TW524873B (en) * 1997-07-11 2003-03-21 Applied Materials Inc Improved substrate supporting apparatus and processing chamber
US6173948B1 (en) * 1999-01-20 2001-01-16 International Business Machines Corporation Dimensional compensating vacuum fixture
US6241825B1 (en) * 1999-04-16 2001-06-05 Cutek Research Inc. Compliant wafer chuck
KR100565138B1 (en) 1999-07-26 2006-03-30 비코 인스트루먼츠 인코포레이티드 Apparatus for growing epitaxial layers on wafers
US6484790B1 (en) * 1999-08-31 2002-11-26 Cummins Inc. Metallurgical bonding of coated inserts within metal castings
JP2001093864A (en) 1999-09-24 2001-04-06 Toshiba Corp Semiconductor wafer fixing jig and method for manufacturing semiconductor device
US6283693B1 (en) 1999-11-12 2001-09-04 General Semiconductor, Inc. Method and apparatus for semiconductor chip handling
EP1174910A3 (en) * 2000-07-20 2010-01-06 Applied Materials, Inc. Method and apparatus for dechucking a substrate
WO2002015237A2 (en) * 2000-08-11 2002-02-21 Rodel Holdings, Inc. Changing local compressibility of a wafer support member
JP2002187060A (en) * 2000-10-11 2002-07-02 Ebara Corp Substrate holding device, polishing device and grinding method
JP4021614B2 (en) * 2000-12-11 2007-12-12 株式会社東芝 Semiconductor element pickup jig, semiconductor element pickup device, semiconductor element pickup method, semiconductor device manufacturing method, and semiconductor device manufacturing apparatus
JP2002270571A (en) 2001-03-14 2002-09-20 Mitsubishi Materials Silicon Corp Apparatus and method for treating semiconductor wafer
CN2470953Y (en) * 2001-03-29 2002-01-09 中国科学院微电子中心 Suction disc of silicon-chip polishing machine head
US6641462B2 (en) * 2001-06-27 2003-11-04 Speedfam-Ipec Corporation Method and apparatus for distributing fluid to a polishing surface during chemical mechanical polishing
US6896929B2 (en) * 2001-08-03 2005-05-24 Applied Materials, Inc. Susceptor shaft vacuum pumping
US7018268B2 (en) * 2002-04-09 2006-03-28 Strasbaugh Protection of work piece during surface processing
JP3817733B2 (en) 2003-09-30 2006-09-06 セイコーエプソン株式会社 Surface treatment jig
JP4574980B2 (en) 2003-12-11 2010-11-04 シャープ株式会社 Semiconductor device manufacturing method, grinding reinforcing member, and method of attaching the same
US7055229B2 (en) * 2003-12-31 2006-06-06 Intel Corporation Support system for semiconductor wafers and methods thereof
ES2533901T3 (en) * 2006-08-10 2015-04-15 California Institute Of Technology Microfluidic valves with floating element and manufacturing procedure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4603466A (en) * 1984-02-17 1986-08-05 Gca Corporation Wafer chuck
US20030037400A1 (en) * 2001-08-27 2003-02-27 Applied Materials, Inc. Factory interface particle removal platform
US20030234078A1 (en) * 2002-06-19 2003-12-25 United Microelectronics Corp. Wafer carrier assembly for a chemical mechanical polishing apparatus and a polishing method using the same

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US7055229B2 (en) 2006-06-06
TWI284956B (en) 2007-08-01
US20050139228A1 (en) 2005-06-30
JP2007517409A (en) 2007-06-28
JP4408900B2 (en) 2010-02-03
DE112004002610T5 (en) 2006-11-16
US20060179632A1 (en) 2006-08-17
CN100449726C (en) 2009-01-07
CN1898791A (en) 2007-01-17
US7757363B2 (en) 2010-07-20

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