WO2005064678A1 - Wafer with optical control modules in dicing paths - Google Patents
Wafer with optical control modules in dicing paths Download PDFInfo
- Publication number
- WO2005064678A1 WO2005064678A1 PCT/IB2004/052721 IB2004052721W WO2005064678A1 WO 2005064678 A1 WO2005064678 A1 WO 2005064678A1 IB 2004052721 W IB2004052721 W IB 2004052721W WO 2005064678 A1 WO2005064678 A1 WO 2005064678A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- ocm
- dicing
- fields
- control module
- wafer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/584,102 US7508051B2 (en) | 2003-12-23 | 2004-12-09 | Wafer with optical control modules in dicing paths |
JP2006546424A JP2007516618A (en) | 2003-12-23 | 2004-12-09 | Wafer with optical control module in dicing path |
EP04801509A EP1700340A1 (en) | 2003-12-23 | 2004-12-09 | Wafer with optical control modules in dicing paths |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03104953 | 2003-12-23 | ||
EP03104953.9 | 2003-12-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005064678A1 true WO2005064678A1 (en) | 2005-07-14 |
Family
ID=34717249
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2004/052721 WO2005064678A1 (en) | 2003-12-23 | 2004-12-09 | Wafer with optical control modules in dicing paths |
Country Status (6)
Country | Link |
---|---|
US (1) | US7508051B2 (en) |
EP (1) | EP1700340A1 (en) |
JP (1) | JP2007516618A (en) |
KR (1) | KR20060117974A (en) |
CN (1) | CN100481438C (en) |
WO (1) | WO2005064678A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9620456B2 (en) | 2007-07-12 | 2017-04-11 | Nxp B.V. | Integrated circuits on a wafer and methods for manufacturing integrated circuits |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5466820B2 (en) * | 2007-10-18 | 2014-04-09 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor substrate and method for manufacturing semiconductor device |
CN108957960A (en) * | 2018-06-06 | 2018-12-07 | 中国电子科技集团公司第五十五研究所 | A kind of promotion substrate Effective number of chips purpose exposure method |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5868560A (en) * | 1997-03-31 | 1999-02-09 | Mitsubishi Denki Kabushiki Kaisha | Reticle, pattern transferred thereby, and correction method |
US6114072A (en) * | 1998-01-14 | 2000-09-05 | Mitsubishi Denki Kabushiki Kaisha | Reticle having interlocking dicing regions containing monitor marks and exposure method and apparatus utilizing same |
EP1284499A2 (en) * | 2001-08-16 | 2003-02-19 | Broadcom Corporation | Apparatus and method for a production testline to monitor cmos srams |
US20030211700A1 (en) * | 2002-04-19 | 2003-11-13 | Nikon Precision Inc. | Methods for critical dimension and focus mapping using critical dimension test marks |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5129974A (en) * | 1990-08-23 | 1992-07-14 | Colorcode Unlimited Corporation | Microlabelling system and method of making thin labels |
US6400173B1 (en) * | 1999-11-19 | 2002-06-04 | Hitachi, Ltd. | Test system and manufacturing of semiconductor device |
US6699627B2 (en) * | 2000-12-08 | 2004-03-02 | Adlai Smith | Reference wafer and process for manufacturing same |
US6503765B1 (en) * | 2001-07-31 | 2003-01-07 | Xilinx, Inc. | Testing vias and contacts in integrated circuit fabrication |
WO2003030214A2 (en) * | 2001-09-28 | 2003-04-10 | Koninklijke Philips Electronics N.V. | Method of manufacturing an integrated circuit, integrated circuit obtained in accordance with said method, wafer provided with an integrated circuit obtained in accordance with the method, and system comprising an integrated circuit obtained by means of the method |
US6967348B2 (en) * | 2002-06-20 | 2005-11-22 | Micron Technology, Inc. | Signal sharing circuit with microelectric die isolation features |
US7102363B2 (en) * | 2003-11-21 | 2006-09-05 | Neocera, Inc. | Method and system for non-contact measurement of microwave capacitance of miniature structures of integrated circuits |
-
2004
- 2004-12-09 US US10/584,102 patent/US7508051B2/en not_active Expired - Fee Related
- 2004-12-09 EP EP04801509A patent/EP1700340A1/en not_active Withdrawn
- 2004-12-09 KR KR1020067012630A patent/KR20060117974A/en not_active Application Discontinuation
- 2004-12-09 CN CNB2004800384275A patent/CN100481438C/en not_active Expired - Fee Related
- 2004-12-09 JP JP2006546424A patent/JP2007516618A/en not_active Withdrawn
- 2004-12-09 WO PCT/IB2004/052721 patent/WO2005064678A1/en not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5868560A (en) * | 1997-03-31 | 1999-02-09 | Mitsubishi Denki Kabushiki Kaisha | Reticle, pattern transferred thereby, and correction method |
US6114072A (en) * | 1998-01-14 | 2000-09-05 | Mitsubishi Denki Kabushiki Kaisha | Reticle having interlocking dicing regions containing monitor marks and exposure method and apparatus utilizing same |
EP1284499A2 (en) * | 2001-08-16 | 2003-02-19 | Broadcom Corporation | Apparatus and method for a production testline to monitor cmos srams |
US20030211700A1 (en) * | 2002-04-19 | 2003-11-13 | Nikon Precision Inc. | Methods for critical dimension and focus mapping using critical dimension test marks |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9620456B2 (en) | 2007-07-12 | 2017-04-11 | Nxp B.V. | Integrated circuits on a wafer and methods for manufacturing integrated circuits |
Also Published As
Publication number | Publication date |
---|---|
US7508051B2 (en) | 2009-03-24 |
US20070111352A1 (en) | 2007-05-17 |
CN1898796A (en) | 2007-01-17 |
KR20060117974A (en) | 2006-11-17 |
EP1700340A1 (en) | 2006-09-13 |
JP2007516618A (en) | 2007-06-21 |
CN100481438C (en) | 2009-04-22 |
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