WO2005064678A1 - Wafer with optical control modules in dicing paths - Google Patents
Wafer with optical control modules in dicing paths Download PDFInfo
- Publication number
- WO2005064678A1 WO2005064678A1 PCT/IB2004/052721 IB2004052721W WO2005064678A1 WO 2005064678 A1 WO2005064678 A1 WO 2005064678A1 IB 2004052721 W IB2004052721 W IB 2004052721W WO 2005064678 A1 WO2005064678 A1 WO 2005064678A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- ocm
- dicing
- fields
- control module
- wafer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the invention relates to a wafer, which wafer comprises a number of exposure fields and which wafer comprises a number of intersecting, lattice-like dicing path sections and a number of lattice grids in each exposure field, wherein each lattice field contains an IC, and which wafer comprises a first group of first dicing paths and a second group of second dicing paths, wherein all of the first dicing paths of the first group run parallel to a first direction and have a first path width and wherein all of the second dicing paths of the second group run parallel to a second direction intersecting the first direction and have a second path width, and wherein the first dicing paths consist of a plurality of first dicing path sections arranged consecutive to one another in the first direction and the second dicing paths consist of a plurality of second dicing path sections arranged consecutive to one another in the second direction, and wherein the first dicing paths and the second dicing paths are provided and designed for a subsequent segregation of the
- Such a wafer according to the design described in the first paragraph is known, for instance, from patent specification US 6,114,072 A, wherein the design described with reference to Figure 21 deserves particular attention.
- the known wafer is so designed that a first control module field of each exposure field immediately adjoins a first edge of the exposure field in question and that a second control module field of each exposure field immediately adjoins the second edge of the exposure field in question.
- Each control module field lies in a half of a first dicing path.
- a first control module field and a second control module field of the two exposure fields in question lie between two rows of lattice fields of two exposure fields, which are arranged immediately adjacent to one another in the second direction, so that the distance extending in the second direction between two rows of lattice fields of two exposure fields, which are arranged immediately adjacent to one another in the second direction, is determined by the double value of the width of a control module field.
- a wafer according to the invention can be characterized in the following way: Wafer, which wafer comprises a number of exposure fields and which wafer comprises a number of intersecting, lattice-like dicing path sections and a number of lattice grids in each exposure field, wherein each lattice field contains an IC, and which wafer comprises a first group of first dicing paths and a second group of second dicing paths, wherein all of the first dicing paths of the first group run parallel to a first direction and have a first path width and wherein all of the second dicing paths of the second group run parallel to a second direction intersecting the first direction and have a second path width, and wherein the first dicing paths consist of a plurality of first dicing path sections arranged consecutive to one another in the first direction and the second dicing
- control module field this being a first control module field
- the width of the dicing paths provided between adjacent lattice fields within each exposure field is expediently likewise determined by the width of such a control module field only, i.e.
- the widths of the first dicing paths running between the lattice fields and of the control module fields are known to lie in the range between 90 ⁇ m and 120 ⁇ m, whereas in a wafer according to the invention - depending on the wafer manufacturing technology and the wafer process technology used - the widths of the first dicing paths and of the control module fields are or can be reduced to values between 80 ⁇ m and 20 ⁇ m or 15 ⁇ m or 10 ⁇ m respectively, wherein particularly thin dicing blades are used for widths between 80 ⁇ m and 50 ⁇ m and the very small widths are subject to the precondition that so-called laser dicers are used for the subsequent segregation of the lattice fields or ICs, wherein so-called “red lasers” or "blue lasers” are used.
- each exposure field preferably has the shape of a rectangle or a square, may, however, alternatively have the shape of a diamond or a triangle.
- a second control module field of each exposure field can lie in the central area of the exposure field in question. It has been found to be particularly advantageous if the second control module field of each exposure field immediately adjoins the row of lattice fields, which row of lattice fields immediately adjoins the second edge of the exposure field in question.
- the exposure fields are approximately 21.0 mm x 21.0 mm in size and if approximately 320 to 128 000 ICs (chips) are implemented on the wafer if its diameter is, for instance, 8.0 inches, amounting to a usable area of approximately 32 000 mm 2 for ICs.
- the measures according to the invention can, however, also be applied in wafers with a diameter of 4.0, 5.0, 6.0 and 12.0 inches.
- Fig. 1 is a diagrammatic top view of a wafer according to an embodiment of the invention.
- Fig. 2 is a section of the wafer according to Fig. 1, which is considerably enlarged compared to Fig. 1.
- Figure 1 shows a wafer 1.
- the wafer 1 has semi-conductor characteristics in the known way.
- the wafer 1 is based on silicon.
- the wafer 1 can, however, alternatively be based on a polymer to obtain so-called polymer ICs with the aid of the wafer.
- the wafer 1 comprises a number of exposure fields 2.
- the exposure fields 2 are shown without the components they contain.
- Figure 2 only shows two complete exposure fields 2 by means of broken lines.
- the wafer 1 has a number of intersecting and lattice-like dicing path sections 6A, 6B, 6C, 8A, 8B 8C, 8D in each exposure field 2.
- the wafer 1 further comprises a number of lattice fields 3 between the dicing path sections 6A, 6B, 6C, 8A, 8B 8C, 8D, wherein each lattice field 3 contains one IC 4.
- Each IC 4 includes a plurality of IC components as has been known for a long time. The IC components are not shown in Figures 1 and 2. Small areas of each IC 4 do not contain any IC components.
- the wafer 1 comprises a first group 5 of first dicing paths 6 and a second group 7 of second dicing paths 8. All of the first dicing paths 6 of the first group 5 run parallel to a first direction X indicated by a dot-dash line in Figure 1.
- All of the second dicing paths 8 of the second group 7 run parallel to a second direction Y intersecting the first direction X and likewise indicated by a dot-dash line in Figure 1.
- the first direction X and the second direction Y intersect at right angles. This is, however, not absolutely necessary, and the two directions X and Y can intersect at an angle other than 90°, for instance at an angle of 85°, 80°, 75° or 70°.
- All of the first dicing paths 6 have a first path width Wl .
- All of the second dicing paths 8 have a second path width W2. In the wafer 1, the two path widths Wl, W2 are different, the first path width Wl being less than the second path width W2.
- the two path widths Wl and W2 may be equal, which is usually preferred. It is also possible to choose a first path width Wl larger than the second path width W2.
- the first dicing paths 6 comprise several first dicing path sections 6A, 6B, 6C arranged consecutively in the first direction X, while the second dicing paths 8 comprise several second dicing path sections 8A, 8B, 8C, 8D arranged consecutively in the second direction Y.
- the first dicing paths 6 and the second dicing paths 8 are provided and designed for the subsequent segregation of the lattice fields 3 and thus of the ICs contained therein.
- a third group of third dicing paths can be provided, resulting in a wafer with triangular lattice fields and triangular ICs.
- the design can be so chosen that the dicing paths of the three groups intersect at an angle of 60°, giving the lattice fields and the ICs the planar shape of an equilateral triangle. This is, however, not necessary, because other angular relationships and thus other triangle shapes are feasible as well.
- the first, second and third dicing paths can have equal or different path widths.
- Each exposure field 2 has a first edge Rl, SI, Tl, Ul, VI, Zl extending parallel to the first direction X and a second edge R2, S2, U2, V2 extending parallel to the second direction Y and lying opposite the first edge Rl, SI, Tl, Ul, VI, Zl.
- the first edge of a viewed exposure field 2 and the second edge of an exposure field 2 arranged immediately adjacent to the viewed exposure field 2 in the second direction virtually coincide.
- the lower edge in Figure 2 i.e.
- the wafer 1 comprises control module fields, each of which contains an optical control module.
- the provision of optical control modules on a wafer as such has been known for some time. These optical control modules contain square or rectangular interference fields detectable, depending on size, either by the naked eye or by computer- aided detection devices and used for mask adjustment and layer thickness testing.
- control module fields and the optical control modules contained therein in the wafer 1 according to Figure 1 is described in detail below with reference to Figure 2.
- two control module fields Al, A2, Bl, B2, CI, Dl, D2, El, E2, FI are assigned to each exposure field 2.
- Each of the control module fields Al , A2, B 1 , B2, C 1 , D 1 , D2, El , E2, F 1 runs parallel to the first direction X and thus to the first dicing paths 6.
- Each of the control module fields Al, A2, Bl, B2, CI, Dl, D2, El, E2, FI contains an optical control module.
- An optical control module of this type has a known three-dimensional structure, because a control module component is implemented in each process step, with the result that at least a control module component of an optical control module which is implemented in a last process step is visible from outside of the wafer 1 or detectable by means of a computer-based detection device, whereas any control module components of a control module which have been implemented in a process step executed before the last process step are not visible or detectable from outside of the wafer.
- control modules in the control module fields Al, A2, Bl, B2, CI, Dl, D2, El, E2, FI are identified by the reference numbers OCM-A1, OCM-A2, OCM-BI, OCM-B2, OCM-C1, OCM-D1, OCM-D2, OCM-E1, OCM-E2, OCM-F1.
- Reference numbers for the control module components are only entered for the optical control module OCM-A2 in Figure 2.
- the control module components located deeper inside the wafer 1 and therefore less visible from outside of the wafer 1 and indicated by broken lines have been given the reference numbers 10, 11, 12, 13, 14, 15, 16, 17, 18 and 19.
- the two control module components located higher in the wafer 1 and therefore visible from outside of the wafer 1 have been given the reference numbers 20 and 21.
- a first control module field Al, Bl, Cl, Dl, El, Fl of each exposure field 2 is located in the edge area of the exposure field 2 in question and immediately adjoins the first edge Rl, SI, Tl, Ul, VI, Zl of the exposure field 2 in question, and the first control module field Al, Bl, CI, Dl, El, FI of each exposure field 2 lies between the first edge Rl, SI, Tl, Ul, VI, Zl and a row of lattice fields 3 extending parallel to the first direction X.
- Each first control module field A1, B1, C1, U1, V1, Z1 lies in a first dicing path section 6A, 6B, 6C and thus in a first dicing path 6.
- a second control module field A2, B2, D2, E2 is located within the exposure field 2 in question.
- Each second control module field A2, B2, D2, E2 lies at a preset distance from the second edge R2, S2, U2, V2 of the exposure field 2 in question between two rows of lattice fields 3 extending parallel to the first direction X and arranged next to one another in a first dicing path section 6A, 6B, 6C and thus likewise in a first dicing path 6.
- the wafer 1 is so arranged that the second control module field A2, B2, E2 of each exposure field 2 immediately adjoins the row of lattice fields 3 extending parallel to the first direction X, which row of lattice fields 3 adjoins the second edge R2, S2, U2, V2, which second edge R2, S2, U2, V2 virtually coincides with the first edge Rl, SI, Ul, VI.
- the wafer 1 offers the great advantage that each control module field Al, A2,
- each of the dicing paths 6 provided for this purpose contains only one control module field Al, A2, Bl, B2, CI, Dl, D2, El, E2, FI and thus only one control module OCM-A1, OCM-A2, OCM-BI, OCM-B2, OCM-Cl, OCM-Dl, OCM-D2, OCM-El, OCM-E2, OCM-Fl, so that all of the first dicing paths 6 can be and therefore are designed narrow.
- all first dicing paths 6 have a first path width Wl of 60 ⁇ m.
- the first path width may alternatively be 70 ⁇ m or 50 ⁇ m or 40 ⁇ m or even less, for instance 30 ⁇ m or 20 ⁇ m or in future technologies even only 10 ⁇ m, because the first path width Wl is essentially not determined by the width of the optical control modules, but by the cutting or separation equipment with which the wafer is cut or divided to segregate the ICs.
- control modules OCM-A1, OCM-A2, OCM-BI, OCM-B2, OCM-Cl, OCM-Dl, OCM-D2, OCM-El, OCM-E2, OCM-Fl it should finally be mentioned that the control modules OCM-A1, OCM-A2, OCM-BI, OCM-B2, OCM-Cl, OCM-Dl, OCM-D2, OCM-El, OCM-E2, OCM-Fl preferably have the dimensions stated below, i.e. a dimension of 10.0 ⁇ m to 60.0 ⁇ m in the first direction X and a dimension of 10.0 ⁇ m to 35.0 ⁇ m in the second direction Y. Actual dimensions depend on the technology used.
- the surface areas of the ICs 4 are slightly smaller than those of the lattice fields 3.
- the surface areas of the ICs 4 may, however, be equal to the surface areas of the lattice fields 3 if preferred.
- three, four, five, six or more control module fields can be provided instead of a total of two control module fields per exposure field.
- the wafer 1 further includes so-called process control modules (PCMs) located in the second dicing paths 8 running parallel to the second direction 8.
- PCMs process control modules
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/584,102 US7508051B2 (en) | 2003-12-23 | 2004-12-09 | Wafer with optical control modules in dicing paths |
JP2006546424A JP2007516618A (en) | 2003-12-23 | 2004-12-09 | Wafer with optical control module in dicing path |
EP04801509A EP1700340A1 (en) | 2003-12-23 | 2004-12-09 | Wafer with optical control modules in dicing paths |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03104953 | 2003-12-23 | ||
EP03104953.9 | 2003-12-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005064678A1 true WO2005064678A1 (en) | 2005-07-14 |
Family
ID=34717249
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2004/052721 WO2005064678A1 (en) | 2003-12-23 | 2004-12-09 | Wafer with optical control modules in dicing paths |
Country Status (6)
Country | Link |
---|---|
US (1) | US7508051B2 (en) |
EP (1) | EP1700340A1 (en) |
JP (1) | JP2007516618A (en) |
KR (1) | KR20060117974A (en) |
CN (1) | CN100481438C (en) |
WO (1) | WO2005064678A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9620456B2 (en) | 2007-07-12 | 2017-04-11 | Nxp B.V. | Integrated circuits on a wafer and methods for manufacturing integrated circuits |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5466820B2 (en) * | 2007-10-18 | 2014-04-09 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor substrate and method for manufacturing semiconductor device |
CN108957960A (en) * | 2018-06-06 | 2018-12-07 | 中国电子科技集团公司第五十五研究所 | A kind of promotion substrate Effective number of chips purpose exposure method |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5868560A (en) * | 1997-03-31 | 1999-02-09 | Mitsubishi Denki Kabushiki Kaisha | Reticle, pattern transferred thereby, and correction method |
US6114072A (en) * | 1998-01-14 | 2000-09-05 | Mitsubishi Denki Kabushiki Kaisha | Reticle having interlocking dicing regions containing monitor marks and exposure method and apparatus utilizing same |
EP1284499A2 (en) * | 2001-08-16 | 2003-02-19 | Broadcom Corporation | Apparatus and method for a production testline to monitor cmos srams |
US20030211700A1 (en) * | 2002-04-19 | 2003-11-13 | Nikon Precision Inc. | Methods for critical dimension and focus mapping using critical dimension test marks |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5129974A (en) * | 1990-08-23 | 1992-07-14 | Colorcode Unlimited Corporation | Microlabelling system and method of making thin labels |
US6400173B1 (en) * | 1999-11-19 | 2002-06-04 | Hitachi, Ltd. | Test system and manufacturing of semiconductor device |
US6699627B2 (en) * | 2000-12-08 | 2004-03-02 | Adlai Smith | Reference wafer and process for manufacturing same |
US6503765B1 (en) * | 2001-07-31 | 2003-01-07 | Xilinx, Inc. | Testing vias and contacts in integrated circuit fabrication |
WO2003030214A2 (en) * | 2001-09-28 | 2003-04-10 | Koninklijke Philips Electronics N.V. | Method of manufacturing an integrated circuit, integrated circuit obtained in accordance with said method, wafer provided with an integrated circuit obtained in accordance with the method, and system comprising an integrated circuit obtained by means of the method |
US6967348B2 (en) * | 2002-06-20 | 2005-11-22 | Micron Technology, Inc. | Signal sharing circuit with microelectric die isolation features |
US7102363B2 (en) * | 2003-11-21 | 2006-09-05 | Neocera, Inc. | Method and system for non-contact measurement of microwave capacitance of miniature structures of integrated circuits |
-
2004
- 2004-12-09 US US10/584,102 patent/US7508051B2/en not_active Expired - Fee Related
- 2004-12-09 EP EP04801509A patent/EP1700340A1/en not_active Withdrawn
- 2004-12-09 KR KR1020067012630A patent/KR20060117974A/en not_active Application Discontinuation
- 2004-12-09 CN CNB2004800384275A patent/CN100481438C/en not_active Expired - Fee Related
- 2004-12-09 JP JP2006546424A patent/JP2007516618A/en not_active Withdrawn
- 2004-12-09 WO PCT/IB2004/052721 patent/WO2005064678A1/en not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5868560A (en) * | 1997-03-31 | 1999-02-09 | Mitsubishi Denki Kabushiki Kaisha | Reticle, pattern transferred thereby, and correction method |
US6114072A (en) * | 1998-01-14 | 2000-09-05 | Mitsubishi Denki Kabushiki Kaisha | Reticle having interlocking dicing regions containing monitor marks and exposure method and apparatus utilizing same |
EP1284499A2 (en) * | 2001-08-16 | 2003-02-19 | Broadcom Corporation | Apparatus and method for a production testline to monitor cmos srams |
US20030211700A1 (en) * | 2002-04-19 | 2003-11-13 | Nikon Precision Inc. | Methods for critical dimension and focus mapping using critical dimension test marks |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9620456B2 (en) | 2007-07-12 | 2017-04-11 | Nxp B.V. | Integrated circuits on a wafer and methods for manufacturing integrated circuits |
Also Published As
Publication number | Publication date |
---|---|
US7508051B2 (en) | 2009-03-24 |
US20070111352A1 (en) | 2007-05-17 |
CN1898796A (en) | 2007-01-17 |
KR20060117974A (en) | 2006-11-17 |
EP1700340A1 (en) | 2006-09-13 |
JP2007516618A (en) | 2007-06-21 |
CN100481438C (en) | 2009-04-22 |
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