WO2005062381A3 - Bump power connections of a semiconductor die - Google Patents

Bump power connections of a semiconductor die Download PDF

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Publication number
WO2005062381A3
WO2005062381A3 PCT/US2004/039639 US2004039639W WO2005062381A3 WO 2005062381 A3 WO2005062381 A3 WO 2005062381A3 US 2004039639 W US2004039639 W US 2004039639W WO 2005062381 A3 WO2005062381 A3 WO 2005062381A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor die
bump
power connections
passivation
layer
Prior art date
Application number
PCT/US2004/039639
Other languages
French (fr)
Other versions
WO2005062381A2 (en
Inventor
Mark Bohr
Bob Martell
Original Assignee
Intel Corp
Mark Bohr
Bob Martell
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Mark Bohr, Bob Martell filed Critical Intel Corp
Priority to DE112004002466T priority Critical patent/DE112004002466B4/en
Priority to JP2006543858A priority patent/JP4563400B2/en
Publication of WO2005062381A2 publication Critical patent/WO2005062381A2/en
Publication of WO2005062381A3 publication Critical patent/WO2005062381A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/13001—Core members of the bump connector
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    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H01L2224/13028—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being disposed on at least two separate bonding areas, e.g. bond pads
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    • H01L2224/1405—Shape
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
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    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Abstract

An apparatus comprising: a die having a top metal layer, the top metal layer comprised of at least a first metal line and a second metal line; a passivation layer covering the top metal layer; a C4 bump on the passivation layer; and a first passivation opening and a second passivation opening in the passivation layer, the first passivation opening to connect the first metal line to the C4 bump, and the second passivation opening to connect the second metal line to the C4 bump.
PCT/US2004/039639 2003-12-17 2004-11-24 Bump power connections of a semiconductor die WO2005062381A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE112004002466T DE112004002466B4 (en) 2003-12-17 2004-11-24 Apparatus and method for improved energy management
JP2006543858A JP4563400B2 (en) 2003-12-17 2004-11-24 Bump power connection of semiconductor die

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/739,726 US7180195B2 (en) 2003-12-17 2003-12-17 Method and apparatus for improved power routing
US10/739,726 2003-12-17

Publications (2)

Publication Number Publication Date
WO2005062381A2 WO2005062381A2 (en) 2005-07-07
WO2005062381A3 true WO2005062381A3 (en) 2005-10-27

Family

ID=34677691

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/039639 WO2005062381A2 (en) 2003-12-17 2004-11-24 Bump power connections of a semiconductor die

Country Status (6)

Country Link
US (2) US7180195B2 (en)
JP (1) JP4563400B2 (en)
CN (1) CN100477190C (en)
DE (1) DE112004002466B4 (en)
TW (1) TWI255517B (en)
WO (1) WO2005062381A2 (en)

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US7208402B2 (en) 2007-04-24
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US20050133894A1 (en) 2005-06-23
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US20050233570A1 (en) 2005-10-20
JP4563400B2 (en) 2010-10-13

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