WO2005062381A2 - Bump power connections of a semiconductor die - Google Patents
Bump power connections of a semiconductor die Download PDFInfo
- Publication number
- WO2005062381A2 WO2005062381A2 PCT/US2004/039639 US2004039639W WO2005062381A2 WO 2005062381 A2 WO2005062381 A2 WO 2005062381A2 US 2004039639 W US2004039639 W US 2004039639W WO 2005062381 A2 WO2005062381 A2 WO 2005062381A2
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- WIPO (PCT)
- Prior art keywords
- metal
- bump
- metal line
- passivation
- layer
- Prior art date
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
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Definitions
- the present invention relates generally to the field of semiconductor packaging, and more specifically to the interconnect between a C4 bump and a semiconductor die.
- FIG. 1 illustrates the connection between a C4 bump 102 and the top metal layer of the die 100. This connection is presently done through a single passivation opening, as illustrated in Figure 1.
- C4 bump 102 is connected to a metal line 104 in the top metal layer through a single passivation opening 106.
- the C4 bump 102 has a diameter of 110 microns.
- the lines of the top metal layer are 20 microns wide, and the passivation opening 106 has an area of approximately 256 square microns (16um x 16um).
- Power is routed through the die by way of a number of metal layers.
- the top two metal layers are illustrated in Figure 1.
- the metal lines 104 on the top metal layer distribute power to metal lines on lower metal layers, including metal lines 112 on the top-1 metal layer.
- power travels from a C4 bump 102, through a single passivation opening 106, to a top metal line 104 in the die, and is then routed to the top-1 metal layer lines 112 and other lower layer metal lines.
- Current density and the ability for the power grid to reliably deliver current is a function of the metal stack and the EM (electromigration) capabilities of the metals and vias in the metal stack. Presently EM issues may be solved in several ways.
- an additional metal layer may be added to the metal stack to reduce current crowding, however this may increase the cost of manufacturing.
- Another alternative that may be used to reduce current crowding is to use a thicker metal layer or increase the pitch of the metal lines. This alternative may result in an undesirable reduction of signal routing capability.
- a further option is doping of the metal layers to allow for greater EM margins. Doping of the metal layers may increase the resistance of the metal lines, which is undesirable.
- Figure 1 is an illustration of an overhead view of an array of C4 bumps connected to the top metal layer of a die.
- Figure 2 is an illustration of an overhead view of a C4 bump connected to the top metal layer of the die in accordance with one embodiment of the present invention.
- Figure 3 is an illustration of an overhead view of a C4 bump connected to the top metal layer of the die in accordance with one embodiment of the present invention.
- Figure 4 is an illustration of a cross-sectional view of a C4 bump connected to the top metal layer of the die in accordance with one embodiment of the present invention.
- Figure 5 is an illustration of an overhead view of an array of C4 bumps connected to the top metal layer of the die in accordance with one embodiment of the present invention.
- Figure 6 is an illustration of a cross-sectional view of C4 bumps connecting a die to a package in accordance with one embodiment of the present invention.
- Figure 7 is a flow diagram illustrating a method in accordance with one embodiment of the present invention.
- FIG. 2 illustrates a top view of a die 200 with a C4 bump 202 attached to the die according to one embodiment of the present invention.
- the C4 bump may be comprised of solder.
- the C4 bump may be comprised of another conductive material, such as copper.
- the C4 bump may have a diameter of approximately llOum.
- C4 bump 202 may be connected to multiple top layer metal lines 204 through passivation openings 206 in the passivation layer.
- each of the two passivation openings under the C4 bump may be approximately equal to one another in size, however they may be of different sizes as well.
- each of the two passivation openings under the C4 bump may be approximately 6um wide by 30um long.
- the passivation opening may be narrower than the width of the metal line 204.
- the total area of both passivation openings may be approximately 360um 2 .
- One passivation opening 206 may be provided for each metal line 204 to which the C4 bump connects.
- the metal lines 204 in the top metal layer may run substantially parallel to one another. In one embodiment of the present invention, the top layer metal lines are approximately lOum wide, and are separated by approximately 50um.
- Metal lines 204 may be comprised of copper or another conductive material.
- FIG. 3 illustrates another embodiment of the present invention. Two or more passivation openings 206 may be used to connect the C4 bump 202 to a single metal line 204. This may also effectively decrease the resistance between the package and the die by increasing the total connection area between the C4 bump and the metal line.
- Each of the passivation openings 206 may be the same size, or they may be of different sizes. While the passivation openings 206 are shown vertically oriented with respect to each other in Figure 3, the passivation openings 206 may also be horizontally oriented with respect to each another, such as in a side-by- side passivation opening configuration.
- Figure 4 illustrates a cross-sectional view of the die of Figure 2.
- Die 200 contains a substrate 201 and top metal layer metal lines 204.
- Die 200 may also contain multiple additional lower layer metal lines, such as top-1 metal line 212.
- Metal lines within the metal stack are connected to one another by vias, 213.
- Vias 213 connect top layer metal lines 204 to top-1 metal line 212.
- Integrated circuits 250 such as transistors or capacitors, may be formed within substrate 201.
- the integrated circuits may be connected to a metal layer in the metal stack by vias 213.
- a passivation layer 210 formed on the top surface of the die 200 protects the surface of the die from external contamination and dust.
- Openings 206 are formed in the passivation layer such that the C4 bump 202 may be connected to multiple top layer metal lines 204.
- a C4 bump may be positioned over two passivation openings so that it may connect to two metal lines.
- the C4 bump may be connected to more than two metal lines through more than two passivation openings.
- At least one passivation opening may be provided to connect the C4 bump to each metal line.
- multiple passivation openings may be provided to connect the C4 bump to each metal line.
- ball limiting metallurgy (BLM) 215 may be present beneath the C4 bump.
- the BLM layer(s) may be comprised of materials including, but not limited to, titanium, vanadium, aluminum, or nitride.
- Figure 5 illustrates a top view of a die 500 having a high power region and a low power region according to one embodiment.
- multiple passivation openings 510 are used to connect each C4 bump 503 to multiple metal lines, 508A or 508B, on the top metal layer of the die for power and ground connections.
- the high power regions of the die may be defined as those regions for which a lower current density is desirable in the local region around the C4 bumps and in the underlying metal layer.
- the high power regions of the die typically have a current density that is 3 to 4 times as great as the current density in the low power regions of the die.
- Embodiments of the present invention decrease current density and current crowding on the top metal layer as well as on the metal layer immediately below the top metal layer of the die. For example, for a die having 8 metal layers, when current crowding exceeds EM (electromigration) margins on the 7th metal layer, it is desirable to use multiple passivation openings to connect the C4 bump to multiple metal lines on the top (8th) metal layer. Where multiple passivation openings are used to connect a single C4 bump to multiple metal lines on the top metal layer, current crowding may be decreased by up to 90% .
- the higher power regions of the die may also be defined as those regions for which a decreased IR drop is desirable.
- Embodiments of the present invention allow a decrease in IR drop for regions of the die where multiple passivation openings are used to connect the C4 bump to multiple metal lines on the top metal layer. Simulations show as much as a 60% improvement in IR drop. This improvement is cause by a reduction in resistance for the top two metal layers due to the enlarged passivation opening(s).
- C4 bumps 503 located in the high power region of the die are each connected to two narrow metal lines 508A or 508B on the top metal layer by two passivation openings 510.
- each passivation opening 510 which connects a single C4 bump to two narrow metal lines may be approximately 6um x 30um in size, or a total area of approximately 360um 2 .
- embodiments of the present invention may be used to increase the total area of the connection between the C4 bump and the die, as compared to the area of the connection in the low power region.
- Power (Vcc) and ground (Vss) in the high power region 520 of the die are distributed to the die on alternate pairs of narrow top metal lines 508 A and 508B.
- Narrow metal lines 508A are power rails (Vcc)
- narrow metal lines 504B are ground rails (Vss).
- narrow metal lines 508 A and 508B run substantially parallel to one another, and are approximately lOum wide.
- the spacing between the narrow metal lines 508A and between narrow metal lines 508B may be between 20 and 70 um, and more particularly may be approximately equal to 50um.
- Metal lines 508 distribute power to the lower metal layers, including metal lines 512.
- Metal lines 512 are on the top-1 metal layer lie directly beneath the top metal layer and run substantially perpendicular to top layer metal lines 508. In the high power regions of the die, power must travel a distance equal to DH on the top-1 metal lines 512 between the top layer Vcc and Vss C4 bumps to complete the current path. In one embodiment, this distance may be approximately 114um.
- die 500 may also include a low power region.
- each passivation opening 506 may be used to connect each C4 bump 502 to a single metal line, 504A or 504B, on the top metal layer of the die for power and ground connections. Single passivation openings may also be used for C4 bumps which are connected to I/O signals on the die. In one embodiment of the present invention, each passivation opening 506 which connects a single C4 bump to a single wide metal line may be approximately 16um x 16um in size, or approximately 256um 2 .
- Wide metal lines 504A are power rails (Vcc), and wide metal line 504B is a ground rail (Vss).
- Vcc power rails
- Vss ground rail
- metal lines 504A and 504B may run substantially parallel to one another, and may be approximately 20um wide. The spacing of the wide metal lines 504 may be approximately 70-75um.
- Metal lines 504 distribute power to the lower metal layers, including metal lines 512.
- Metal lines 512 on the top-1 metal layer lie directly beneath the top metal layer and run substantially perpendicular to top layer metal lines 504.
- FIG. 6 illustrates a cross-sectional view of a die and a package according to an embodiment of the present invention.
- C4 bumps 602 and 603 connect the flip-chip package 620 to the die 600.
- Power may be distributed from the flip chip package 620 through the C4 bump and through passivation opening(s) beneath the C4 bump, to multiple top layer metal lines. Power may then be further distributed throughout the die from the top metal layer metal line to additional metal layers located beneath the top metal layer, including top-1 metal layer 612.
- Top-1 metal layer 612 is connected to top metal layer lines 608 by vias 613.
- Multiple passivation openings 610 may be used to connect each C4 bump 603 to multiple metal lines 608 on the top metal layer of the die for power and ground connections in the high power regions of the die, as described above with respect to Figure 5.
- Single passivation openings 606 may be used to connect the C4 bump 602 to a single metal line 604 on the top metal layer of the die 600 for power and ground connections in regions of lower power, as described above.
- Single passivation openings may also be used for C4 bumps which are connected to I/O signals on the die.
- FIG. 7 is a flow diagram, 700, showing a process in accordance with one embodiment of the present invention.
- a passivation layer is formed on the top surface of a semiconductor die.
- the semiconductor die may contain metal lines, integrated circuits, or other circuit elements therein.
- the passivation layer may be grown or deposited on the top surface of the die.
- passivation openings may be formed in the passivation layer.
- the passivation openings may be formed by patterning using a conventional lithography process.
- the passivation openings may be any shape or size, so long as they are no larger than the C4 bump that covers the passivation opening.
- the passivation openings may be square, rectangular, octagonal, or circular in shape.
- the passivation openings may range in size from approximately 50 um 2 to 500 um 2 . When formed, the passivation openings may expose metal lines on the top metal layer of the die.
- a plurality of C4 bumps may be placed on the top surface of the die, over the passivation layer, as set forth in block 730.
- each C4 bump may cover at least two passivation openings, and may connect to at least two top layer metal lines.
- each C4 bump may cover only one passivation opening, and may connect to only one top layer metal line.
- a package may be placed over the die and the C4 bumps, so that the C4 bumps electrically connect the die to the package.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006543858A JP4563400B2 (en) | 2003-12-17 | 2004-11-24 | Bump power connection of semiconductor die |
DE112004002466T DE112004002466B4 (en) | 2003-12-17 | 2004-11-24 | Apparatus and method for improved energy management |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/739,726 | 2003-12-17 | ||
US10/739,726 US7180195B2 (en) | 2003-12-17 | 2003-12-17 | Method and apparatus for improved power routing |
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WO2005062381A2 true WO2005062381A2 (en) | 2005-07-07 |
WO2005062381A3 WO2005062381A3 (en) | 2005-10-27 |
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PCT/US2004/039639 WO2005062381A2 (en) | 2003-12-17 | 2004-11-24 | Bump power connections of a semiconductor die |
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US (2) | US7180195B2 (en) |
JP (1) | JP4563400B2 (en) |
CN (1) | CN100477190C (en) |
DE (1) | DE112004002466B4 (en) |
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WO (1) | WO2005062381A2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011505705A (en) * | 2007-12-04 | 2011-02-24 | エーティーアイ・テクノロジーズ・ユーエルシー | Method and apparatus for under bump wiring layer |
WO2012142701A1 (en) | 2011-04-22 | 2012-10-26 | Ati Technologies Ulc | A routing layer for mitigating stress in a semiconductor die |
EP2471096A4 (en) * | 2009-10-23 | 2015-04-29 | Ati Technologies Ulc | A routing layer for mitigating stress in a semiconductor die |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2540279C (en) | 2005-03-01 | 2009-10-20 | Variation Biotechnologies Inc. | Hiv vaccine composition |
FR2894716A1 (en) * | 2005-12-09 | 2007-06-15 | St Microelectronics Sa | INTEGRATED CIRCUIT CHIP WITH EXTERNAL PLATES AND METHOD OF MANUFACTURING SUCH CHIP |
US8212357B2 (en) * | 2008-08-08 | 2012-07-03 | International Business Machines Corporation | Combination via and pad structure for improved solder bump electromigration characteristics |
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US20180166419A1 (en) * | 2016-12-12 | 2018-06-14 | Nanya Technology Corporation | Semiconductor package |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5404045A (en) * | 1991-10-19 | 1995-04-04 | Nec Corporation | Semiconductor device with an electrode pad having increased mechanical strength |
US6437431B1 (en) * | 2001-08-07 | 2002-08-20 | Lsi Logic Corporation | Die power distribution system |
US20030067066A1 (en) * | 2001-10-10 | 2003-04-10 | Nec Corporation | Semiconductor device |
US20030122258A1 (en) * | 2001-12-28 | 2003-07-03 | Sudhakar Bobba | Current crowding reduction technique using slots |
Family Cites Families (51)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6016103B2 (en) | 1977-09-13 | 1985-04-23 | セイコーエプソン株式会社 | semiconductor integrated circuit |
JPS5444881A (en) | 1977-09-16 | 1979-04-09 | Nec Corp | Electrode wiring structure of integrated circuit |
JPS57106056A (en) | 1980-12-23 | 1982-07-01 | Mitsubishi Electric Corp | Electrode structural body of semiconductor device |
JPS607758A (en) | 1983-06-27 | 1985-01-16 | Nec Corp | Semiconductor device |
JPS6149452A (en) | 1984-08-17 | 1986-03-11 | Matsushita Electronics Corp | Semiconductor element |
JPS62176140A (en) | 1986-01-30 | 1987-08-01 | Seiko Epson Corp | Shape of pad in semiconductor integrated circuit |
JPH0319248A (en) | 1989-06-15 | 1991-01-28 | Nec Corp | Semiconductor device |
JPH0513418A (en) | 1991-07-04 | 1993-01-22 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
JP3035012B2 (en) | 1991-07-16 | 2000-04-17 | 株式会社ブリヂストン | Pneumatic radial tire |
JP3170758B2 (en) * | 1991-10-02 | 2001-05-28 | 富士通株式会社 | Semiconductor integrated circuit |
JPH05206198A (en) | 1992-01-29 | 1993-08-13 | Nec Corp | Semiconductor device |
JP3383329B2 (en) | 1992-08-27 | 2003-03-04 | 株式会社東芝 | Method for manufacturing semiconductor device |
US5436412A (en) * | 1992-10-30 | 1995-07-25 | International Business Machines Corporation | Interconnect structure having improved metallization |
US5410184A (en) | 1993-10-04 | 1995-04-25 | Motorola | Microelectronic package comprising tin-copper solder bump interconnections, and method for forming same |
US5426266A (en) | 1993-11-08 | 1995-06-20 | Planar Systems, Inc. | Die bonding connector and method |
JPH07335679A (en) | 1994-06-03 | 1995-12-22 | Fujitsu Ten Ltd | Soldering structure for aluminum post |
US5492235A (en) | 1995-12-18 | 1996-02-20 | Intel Corporation | Process for single mask C4 solder bump fabrication |
US6300688B1 (en) | 1994-12-07 | 2001-10-09 | Quicklogic Corporation | Bond pad having vias usable with antifuse process technology |
JPH08204136A (en) | 1995-01-31 | 1996-08-09 | Rohm Co Ltd | Semiconductor device |
KR100327442B1 (en) * | 1995-07-14 | 2002-06-29 | 구본준, 론 위라하디락사 | Bump structure of semiconductor device and fabricating method thereof |
US5674780A (en) | 1995-07-24 | 1997-10-07 | Motorola, Inc. | Method of forming an electrically conductive polymer bump over an aluminum electrode |
JPH0982714A (en) | 1995-09-14 | 1997-03-28 | Citizen Watch Co Ltd | I/o terminal of semiconductor integrated circuit |
JP3457123B2 (en) | 1995-12-07 | 2003-10-14 | 株式会社リコー | Semiconductor device |
US5883435A (en) * | 1996-07-25 | 1999-03-16 | International Business Machines Corporation | Personalization structure for semiconductor devices |
JPH10270484A (en) | 1997-03-25 | 1998-10-09 | Matsushita Electron Corp | Semiconductor device and manufacture thereof |
US5929521A (en) | 1997-03-26 | 1999-07-27 | Micron Technology, Inc. | Projected contact structure for bumped semiconductor device and resulting articles and assemblies |
JP3592486B2 (en) | 1997-06-18 | 2004-11-24 | 株式会社東芝 | Soldering equipment |
US6875681B1 (en) | 1997-12-31 | 2005-04-05 | Intel Corporation | Wafer passivation structure and method of fabrication |
US6927491B1 (en) * | 1998-12-04 | 2005-08-09 | Nec Corporation | Back electrode type electronic part and electronic assembly with the same mounted on printed circuit board |
SG93278A1 (en) * | 1998-12-21 | 2002-12-17 | Mou Shiung Lin | Top layers of metal for high performance ics |
US6179200B1 (en) | 1999-02-03 | 2001-01-30 | Industrial Technology Research Institute | Method for forming solder bumps of improved height and devices formed |
US6387734B1 (en) * | 1999-06-11 | 2002-05-14 | Fujikura Ltd. | Semiconductor package, semiconductor device, electronic device and production method for semiconductor package |
KR20010004529A (en) * | 1999-06-29 | 2001-01-15 | 김영환 | wafer level package and method of fabricating the same |
JP3353748B2 (en) * | 1999-07-19 | 2002-12-03 | 日本電気株式会社 | Semiconductor device and method of manufacturing the same |
US6596624B1 (en) * | 1999-07-31 | 2003-07-22 | International Business Machines Corporation | Process for making low dielectric constant hollow chip structures by removing sacrificial dielectric material after the chip is joined to a chip carrier |
JP4021104B2 (en) * | 1999-08-05 | 2007-12-12 | セイコーインスツル株式会社 | Semiconductor device having bump electrodes |
US6191023B1 (en) * | 1999-11-18 | 2001-02-20 | Taiwan Semiconductor Manufacturing Company | Method of improving copper pad adhesion |
JP2001176966A (en) * | 1999-12-20 | 2001-06-29 | Matsushita Electronics Industry Corp | Semiconductor device |
JP2001196413A (en) * | 2000-01-12 | 2001-07-19 | Mitsubishi Electric Corp | Semiconductor device, method of manufacturing the same, cmp device and method |
US6495917B1 (en) * | 2000-03-17 | 2002-12-17 | International Business Machines Corporation | Method and structure of column interconnect |
JP2001291720A (en) * | 2000-04-05 | 2001-10-19 | Hitachi Ltd | Semiconductor integrated circuit device and its manufacturing method |
JP4750926B2 (en) * | 2000-06-06 | 2011-08-17 | 富士通セミコンダクター株式会社 | Semiconductor device |
JP3523189B2 (en) * | 2000-12-27 | 2004-04-26 | 株式会社東芝 | Semiconductor device |
US6815324B2 (en) * | 2001-02-15 | 2004-11-09 | Megic Corporation | Reliable metal bumps on top of I/O pads after removal of test probe marks |
JP4248761B2 (en) * | 2001-04-27 | 2009-04-02 | 新光電気工業株式会社 | Semiconductor package, manufacturing method thereof, and semiconductor device |
US6686664B2 (en) * | 2001-04-30 | 2004-02-03 | International Business Machines Corporation | Structure to accommodate increase in volume expansion during solder reflow |
JP2003100803A (en) * | 2001-09-27 | 2003-04-04 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method thereof |
US6841413B2 (en) * | 2002-01-07 | 2005-01-11 | Intel Corporation | Thinned die integrated circuit package |
FR2842351A1 (en) * | 2002-07-12 | 2004-01-16 | St Microelectronics Sa | ADAPTATION OF AN INTEGRATED CIRCUIT TO SPECIFIC NEEDS |
US7023067B2 (en) * | 2003-01-13 | 2006-04-04 | Lsi Logic Corporation | Bond pad design |
US6913946B2 (en) * | 2003-06-13 | 2005-07-05 | Aptos Corporation | Method of making an ultimate low dielectric device |
-
2003
- 2003-12-17 US US10/739,726 patent/US7180195B2/en not_active Expired - Lifetime
-
2004
- 2004-08-20 TW TW093125197A patent/TWI255517B/en active
- 2004-11-24 DE DE112004002466T patent/DE112004002466B4/en active Active
- 2004-11-24 WO PCT/US2004/039639 patent/WO2005062381A2/en active Application Filing
- 2004-11-24 JP JP2006543858A patent/JP4563400B2/en not_active Expired - Fee Related
- 2004-11-24 CN CNB2004800360942A patent/CN100477190C/en active Active
-
2005
- 2005-06-03 US US11/144,974 patent/US7208402B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5404045A (en) * | 1991-10-19 | 1995-04-04 | Nec Corporation | Semiconductor device with an electrode pad having increased mechanical strength |
US6437431B1 (en) * | 2001-08-07 | 2002-08-20 | Lsi Logic Corporation | Die power distribution system |
US20030067066A1 (en) * | 2001-10-10 | 2003-04-10 | Nec Corporation | Semiconductor device |
US20030122258A1 (en) * | 2001-12-28 | 2003-07-03 | Sudhakar Bobba | Current crowding reduction technique using slots |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011505705A (en) * | 2007-12-04 | 2011-02-24 | エーティーアイ・テクノロジーズ・ユーエルシー | Method and apparatus for under bump wiring layer |
EP2471096A4 (en) * | 2009-10-23 | 2015-04-29 | Ati Technologies Ulc | A routing layer for mitigating stress in a semiconductor die |
US9035471B2 (en) | 2009-10-23 | 2015-05-19 | Ati Technologies Ulc | Routing layer for mitigating stress in a semiconductor die |
US9059159B2 (en) | 2009-10-23 | 2015-06-16 | Ati Technologies Ulc | Routing layer for mitigating stress in a semiconductor die |
WO2012142701A1 (en) | 2011-04-22 | 2012-10-26 | Ati Technologies Ulc | A routing layer for mitigating stress in a semiconductor die |
EP2700091A1 (en) * | 2011-04-22 | 2014-02-26 | ATI Technologies ULC | A routing layer for mitigating stress in a semiconductor die |
EP2700091A4 (en) * | 2011-04-22 | 2015-04-29 | Ati Technologies Ulc | A routing layer for mitigating stress in a semiconductor die |
Also Published As
Publication number | Publication date |
---|---|
WO2005062381A3 (en) | 2005-10-27 |
CN1890808A (en) | 2007-01-03 |
DE112004002466B4 (en) | 2013-08-14 |
JP2007514318A (en) | 2007-05-31 |
TW200522235A (en) | 2005-07-01 |
TWI255517B (en) | 2006-05-21 |
CN100477190C (en) | 2009-04-08 |
US7208402B2 (en) | 2007-04-24 |
US7180195B2 (en) | 2007-02-20 |
US20050233570A1 (en) | 2005-10-20 |
US20050133894A1 (en) | 2005-06-23 |
JP4563400B2 (en) | 2010-10-13 |
DE112004002466T5 (en) | 2008-03-27 |
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