WO2005062352A1

WO2005062352A1 - A semiconductor substrate with solid phase epitaxial regrowth with reduced junction leakage and method of producing same

Info

Publication number: WO2005062352A1
Application number: PCT/IB2004/052757
Authority: WO
Inventors: Bartlomiej J. Pawlak
Original assignee: Koninklijke Philips Electronics N.V.; Interuniversitair Microelektronica Centrum Vzw
Priority date: 2003-12-18
Filing date: 2004-12-10
Publication date: 2005-07-07

Abstract

Method of producing a semiconductor device comprising: a) providing a semiconductor substrate, b) making an amorphous layer in a top layer of said semiconductor substrate by a suitable implant, c) implanting a dopant into said semiconductor substrate to provide said amorphous layer with a predetermined doping profile, d) applying a solid phase epitaxial regrowth action to regrow said amorphous layer and activate said dopant, e) passivating post-implantation defects in an ambient comprising at least hydrogen and nitrogen in order to reduce junction leakage currents.

Description

A semiconductor substrate with solid phase epitaxial regrowth with reduced junction leakage and method of producing same

The present invention relates to a method of producing a semiconductor device, comprising: a) providing a semiconductor substrate, b) making an amorphous layer in a top layer of the semiconductor substrate by a suitable implant, c) implanting a dopant into the semiconductor substrate to provide the amorphous layer with a predetermined doping profile, d) applying a solid phase epitaxial regrowth action to regrow the amorphous layer and activate the dopant. Such a technique is known as SPER (Solid Phase Epitaxial Regrowth).

The technique of SPER is disclosed a.o., by US-A-6,063,682. According to this prior art document, heavy ions are implanted into a silicon substrate. The implanted heavy ions create an amorphous layer at the top surface of the substrate. The amorphous layer is free of channels. Then, a silicon implanting step is performed to create an excess of vacancies compared to interstitials within a top layer of the substrate. Since the amorphized silicon layer is free of channels, the depth of implant is mainly restricted to this amorphized silicon layer. One of the most promising approaches for future generations of CMOS technology nodes is low temperature processing. This is due to a few reasons, such as metal gate and junction formation that require a reduced thermal budget. Ultra-shallow (source and drain extensions) junctions formed by Solid Phase Epitaxial Regrowth (SPER) can be obtained with good metastable B activation, limited dopant diffusion and excellent abruptness. Typical temperatures used for the junction regrowth are between T=550°C and T=750°C. Processing at these low temperatures does not remove the post-implantation damage completely and therefore such junctions suffer from a higher leakage current. Deep Level Transient Spectroscopy (DLTS) studies prove that the typical defects are positioned 0.457 eV below the conduction band. Therefore, it is an object of the present invention to reduce the leakage current. To achieve this object, the method as defined at the outset is characterized in that the action d) is followed by passivating post-implantation defects in an ambient comprising at least hydrogen and nitrogen. Experiments have shown that such an ambient passivates the post-implantation defects and reduces leakage current considerably. Preferably, the passivating process is performed by a Forming Gas Anneal Action (FGA). The ambient may comprise 80% nitrogen and 20% hydrogen. The invention also relates to a semiconductor device made by a method according to any of the preceding claims. Moreover, the invention relates to a metal oxide semiconductor device comprising such a semiconductor device. Finally, the invention relates to an apparatus provided with such a semiconductor device.

Figs, la-lf show different stages of producing a semiconductor device in accordance with the present invention. Fig. 2 shows an example of a dopant concentration and a conductivity profile as a function of depth in a semiconductor substrate in accordance with a method known from the prior art. Fig. 3 shows examples of leakage current and sheet resistance for some experiments.

In the description to follow, same reference numbers refer to same elements in all Figures. Figures la-lf refer to producing a metal oxide semiconductor device in which the present invention is used. However, as will be evident to a person skilled in the art, the inventive features may be applied in the production of any other type of semiconductor device where shallow junctions are desired. Figure la shows a semiconductor substrate 1 of a p-type. Field oxide regions 3 are provided on a top surface of the semiconductor substrate 1. At certain locations, a thin oxide layer 5 is provided by a technique known to a person skilled in the art. The thin oxide layer 5 can later be used as the gate oxide layer within the MOS device to be produced. However, the present invention is not restricted to the application of a thin oxide layer 5 to obtain the desired effect as will become clear from the description below. The structure of Figure la is provided with a suitable photoresist layer 30 having an opening above the thin oxide layer 5. Then, an implanting action is performed to produce an n-well 11 within the substrate 1. The thin oxide layer 5 may be removed and substituted by a new, fresh oxide layer and used later on as the gate oxide layer in the MOS device to be produced. However, here it is assumed that the thin oxide layer 5 remains in place. As shown in Figure lc, on top of the thin oxide layer 5, a polysilicon layer 13 is provided which will be used later as the gate of the MOS device to be produced. An amorphization implant 15 is performed to produce an amoφhous layer in the top of the substrate 1. The depth of the implant that defines the depth of the amoφhous layer is indicated by means of reference number 17. For the implant 15 carried out to produce this amoφhous layer use may be made of Ge, GeF₂ or Si. The amoφhous layer 17 may, e.g., be produced with Ge in a dose of 10¹⁵ atoms/cm² and an energy between 2 and 30 keV. Other values are, of course, possible. However, other atoms, like indium, may be applied instead. In this case, the doping process is carried out at the same time. By this implant, the channels in the silicon substrate 1 are eliminated in the amoφhous layer. This step of producing the amoφhous layer is followed by a subsequent dopant implant, e.g., with boron or arsenic. Since there are no channels within the amorphous layer, the dopant implant atoms, like boron or arsenic, will penetrate the silicon substrate 1 to a depth only slightly below the amorphous layer. The depth of this subsequent dopant implant is indicated by means of reference number 19. It is to be understood that the depth of implant 19 is only slightly larger than the depth of the amoφhous layer 17. The distances between the dashed line 17 and the top surface, and the distance between the dashed line 19 and the top surface of substrate 1 are not drawn to scale. They are drawn only to illustrate the principle of the present invention. Implanting boron (B) or arsenic (As) may, e.g., be performed at an energy of less than 5 keV and a dose of 10¹⁵ atoms/cm². However, other values are possible. Now, reference is made to Figure 2. Figure 2 shows the top of the silicon substrate, the depth of the amoφhous layer 17 and the depth of the implant of boron (as an example) 19. The boron profile corresponds to the boron profile as shown in prior art document US-A-6,063,682. A next action is to apply a so-called low temperature approach, i.e. a solid phase epitaxial regrowth (SPER) technique. In SPER, the silicon crystal is first pre- amorphized, then doped and finally regrown at a temperature typically between 550° C and 750° C. By this temperature action, the amoφhous layer is regrown and the dopant (e.g., boron) is activated. The main advantages of SPER are limited dopant diffusion (hardly beyond the amoφhous layer 17) and above solid solubility dopant activation. Investigations have shown that processing at these low temperatures does not remove the post-implantation damage completely. Defects remain that are typically located slightly deeper than the original amoφhous layer 17. Deep level transient spectroscopy (DLTS) studies prove that the typical defects are positioned 0.457 eV below the conduction band. Si interstitial clusters remain as well as 311 errors. This results in too high a junction leakage current. Moreover, there may be thermal instability for the junction. For example, if a further process step would be performed at a temperature of 800°C, then there is a high risk that this junction will be damaged by these defects. In accordance with the present invention it is proposed to passivate these post- implantation defects in an ambient containing hydrogen and nitrogen. Preferably, the ambient comprises 20% hydrogen and 80% nitrogen. Moreover, preferably, this is done in a forming gas anneal (FGA) action. The temperature of this passivating action is preferably in the range between 350°C and 550°C. If the temperature is lower than 350°C the hydrogen might hardly diffuse into the substrate, whereas at a temperature of more than 550°C the junction may be damaged by the hydrogen. As an example, the passivating action may be performed at a temperature of 420°C for 20 minutes. However, the invention is not restricted to this example. Figure 3 shows a few results of some experiments. Figure 3 shows both sheet resistance (Rs) and leakage current of the junction formed by the present invention. The sheet resistance is measured to obtain an indication of the activation in the junction. The leakage current is measured to learn whether the device operates properly. The sheet resistance Rs and the leakage current are both measured at a voltage of U = -1 V. The SPER process was performed at T = 650°C for 1 minute, indicated in Figure 3 by 650Clmin. Post-processing of the junction made in this way in a hydrogen/nitrogen ambient by a FGA action (FGA = Forming Gas Anneal), indicated by 650Clmin&FGA in Figure 3, reduces both the sheet resistance Rs and the leakage current. In this example, the FGA action was performed at 420°C during 20 minutes in a hydrogen/nitrogen atmosphere. Moreover, as shown in Figure 3, other post-processing combinations like pre- anneal indicated by FGA&650Clmin, or post-anneal in pure nitrogen ambient, indicated by 650Clmin&RTA, always result in an increase of the sheet resistance Rs. Here, FGA&650Clmin means: first a FGA action was performed at 420°C during 20 minutes in a hydrogen/nitrogen atmosphere followed by a SPER activation action at 650°C during 1 minute. Moreover, 650Clmin&RTA means: first a SPER activation at 650°C during 1 minute was performed followed by a post anneal action at 420°C during 20 minutes in a nitrogen atmosphere. Figure 3 presents sheet resistance Rs and leakage currents for these different combinations. Combination 1 seems to offer the best results for both. In the post-anneal experiment in a pure nitrogen ambient (650Clmin&RTA) the leakage current is also reduced but not as significantly as in the optimum processing scheme indicated by 650Clmin&FGA. Some advantages of the method according to the invention are: the addition of the FGA action reduces simultaneously both the leakage current and the sheet resistance Rs of the junction, which generally improves the performance of the junction; the FGA action can be combined with other passivation actions in the process flow performed to produce the final semiconductor device, like passivation of a gate dielectric interface or other electrically active defects. Now, with reference to Figures ld-lf, the completion of the semiconductor device to be produced will be explained. As shown in Figure Id, after the SPER process, lightly doped regions 18 result that will become source/drain extension regions of the MOS transistor on the substrate 1. The depth of these doped regions 18 will be substantially equal to the depth of the earlier amorphous layer 17. On top of the structure, a spacer material 21 is deposited. The spacer material 21 may be silicon dioxide. However, other spacer materials may be used, as is known to a person skilled in the art. The spacer material 21 is etched with a suitable etchant in such a manner that only side spacers 23 adjacent to the polysilicon layer 13 remain. See Figure le. This is all prior art and needs no further explanation here. It is noted that, due to the etch process, only a portion of the thin oxide layer 5 remains, i.e. the portion below the polysilicon layer 13 and the portions below the side spacers 23. The portions of the thin oxide layer 5 that are situated elsewhere are removed by the etch process. A further ion implant action is performed as shown in Figure If. In the embodiment shown, this is a p⁺ implant 29 to produce a p⁺ source region 27 and a p⁺ drain region 25. These source and drain regions 27, 25 extend deeper into the substrate 1 than the previously doped regions 18. The side spacers 23 act as a mask to protect portions of the previously doped regions 18 from this latter p⁺ implant 29. Thus, extension regions 18 remain after this action. As is known to a person skilled in the art, the manufacture of the MOS device is completed by, e.g., providing a suitable silicide process to form silicide on the drain 25, the source 27 and the polysilicon layer 13 which acts as a gate. This latter silicide process is known to a person skilled in the art and not shown in figure If.

Claims

CLAIMS:

1. Method of producing a semiconductor device comprising: a) providing a semiconductor substrate, b) making an amoφhous layer in a top layer of said semiconductor substrate by a suitable implant, c) implanting a dopant into said semiconductor substrate to provide said amoφhous layer with a predetermined doping profile, d) applying a solid phase epitaxial regrowth action to regrow said amoφhous layer and activate said dopant, wherein said action d) is followed by: passivating post-implantation defects in an ambient comprising at least hydrogen and nitrogen.

2. Method according to claim 1 , wherein said passivating is performed by a forming gas anneal action.

3. Method according to claim 2, wherein said gas anneal action is performed at T = 420 °C for 20 minutes.

4. Method according to any of the preceding claims, wherein the ambient comprises 80% nitrogen and 20% hydrogen.

5. Method according to any of the preceding claims, wherein said action b) is performed using Ge in a dose of 10¹⁵ atoms/cm² and an energy between 2 and 30 keV.

6. Method according to any of the preceding claims, wherein said action c) is performed using B or As at an energy of less than 5 keV and a dose of 10¹⁵ atoms/cm².

7. Method according to any of the preceding claims, wherein action d) is performed at a temperature of 550-750 °C during about 1 minute.

8. Semiconductor device made by a method according to any of the preceding claims.

9. Metal oxide semiconductor device comprising a device as claimed in claim 8.

10. Apparatus provided with a semiconductor device as claimed in claim 8 or 9.