WO2005045901A3 - METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES - Google Patents
METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES Download PDFInfo
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- WO2005045901A3 WO2005045901A3 PCT/US2004/037049 US2004037049W WO2005045901A3 WO 2005045901 A3 WO2005045901 A3 WO 2005045901A3 US 2004037049 W US2004037049 W US 2004037049W WO 2005045901 A3 WO2005045901 A3 WO 2005045901A3
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- type device
- semiconductor substrate
- cmos devices
- strain layer
- forming strained
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- 238000000034 method Methods 0.000 title abstract 4
- 239000004065 semiconductor Substances 0.000 abstract 4
- 239000000758 substrate Substances 0.000 abstract 4
- 238000004519 manufacturing process Methods 0.000 abstract 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04810466A EP1680804A4 (en) | 2003-11-05 | 2004-11-05 | METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES |
JP2006538524A JP4959337B2 (en) | 2003-11-05 | 2004-11-05 | Method and structure for forming strained Si for CMOS devices |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/605,906 | 2003-11-05 | ||
US10/605,906 US7129126B2 (en) | 2003-11-05 | 2003-11-05 | Method and structure for forming strained Si for CMOS devices |
Publications (3)
Publication Number | Publication Date |
---|---|
WO2005045901A2 WO2005045901A2 (en) | 2005-05-19 |
WO2005045901A8 WO2005045901A8 (en) | 2006-02-02 |
WO2005045901A3 true WO2005045901A3 (en) | 2006-08-17 |
Family
ID=34549690
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2004/037049 WO2005045901A2 (en) | 2003-11-05 | 2004-11-05 | METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES |
Country Status (6)
Country | Link |
---|---|
US (5) | US7129126B2 (en) |
EP (1) | EP1680804A4 (en) |
JP (1) | JP4959337B2 (en) |
KR (1) | KR100866826B1 (en) |
CN (1) | CN100555600C (en) |
WO (1) | WO2005045901A2 (en) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7037770B2 (en) * | 2003-10-20 | 2006-05-02 | International Business Machines Corporation | Method of manufacturing strained dislocation-free channels for CMOS |
US7129126B2 (en) * | 2003-11-05 | 2006-10-31 | International Business Machines Corporation | Method and structure for forming strained Si for CMOS devices |
US7029964B2 (en) * | 2003-11-13 | 2006-04-18 | International Business Machines Corporation | Method of manufacturing a strained silicon on a SiGe on SOI substrate |
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US7550338B2 (en) | 2009-06-23 |
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US20080283824A1 (en) | 2008-11-20 |
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KR20060108663A (en) | 2006-10-18 |
US7429752B2 (en) | 2008-09-30 |
US7129126B2 (en) | 2006-10-31 |
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