WO2005045901A3 - METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES - Google Patents

METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES Download PDF

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Publication number
WO2005045901A3
WO2005045901A3 PCT/US2004/037049 US2004037049W WO2005045901A3 WO 2005045901 A3 WO2005045901 A3 WO 2005045901A3 US 2004037049 W US2004037049 W US 2004037049W WO 2005045901 A3 WO2005045901 A3 WO 2005045901A3
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WIPO (PCT)
Prior art keywords
type device
semiconductor substrate
cmos devices
strain layer
forming strained
Prior art date
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PCT/US2004/037049
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French (fr)
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WO2005045901A8 (en
WO2005045901A2 (en
Inventor
An L Steegen
Haining S Yang
Ying Zhang
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Ibm
An L Steegen
Haining S Yang
Ying Zhang
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Publication date
Application filed by Ibm, An L Steegen, Haining S Yang, Ying Zhang filed Critical Ibm
Priority to EP04810466A priority Critical patent/EP1680804A4/en
Priority to JP2006538524A priority patent/JP4959337B2/en
Publication of WO2005045901A2 publication Critical patent/WO2005045901A2/en
Publication of WO2005045901A8 publication Critical patent/WO2005045901A8/en
Publication of WO2005045901A3 publication Critical patent/WO2005045901A3/en

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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate (200) and forming a gap (219) in the semiconductor substrate (200) by removing at least a portion of the doped portion of the semiconductor substrate (200). The method further involves growing a strain layer (227) in at least a portion of the gap (219) in the semiconductor substrate (200). For the n-type device, the strain layer (227) is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device.
PCT/US2004/037049 2003-11-05 2004-11-05 METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES WO2005045901A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP04810466A EP1680804A4 (en) 2003-11-05 2004-11-05 METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES
JP2006538524A JP4959337B2 (en) 2003-11-05 2004-11-05 Method and structure for forming strained Si for CMOS devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/605,906 2003-11-05
US10/605,906 US7129126B2 (en) 2003-11-05 2003-11-05 Method and structure for forming strained Si for CMOS devices

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WO2005045901A2 WO2005045901A2 (en) 2005-05-19
WO2005045901A8 WO2005045901A8 (en) 2006-02-02
WO2005045901A3 true WO2005045901A3 (en) 2006-08-17

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