WO2005043385A1 - Method and system for alternating instructions sets in a central processing unit - Google Patents
Method and system for alternating instructions sets in a central processing unit Download PDFInfo
- Publication number
- WO2005043385A1 WO2005043385A1 PCT/US2004/034730 US2004034730W WO2005043385A1 WO 2005043385 A1 WO2005043385 A1 WO 2005043385A1 US 2004034730 W US2004034730 W US 2004034730W WO 2005043385 A1 WO2005043385 A1 WO 2005043385A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- fuse
- central processing
- processing unit
- instruction set
- value
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30196—Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/3822—Parallel decoding, e.g. parallel decode units
Definitions
- the present invention relates generally to microprocessors. More specifically, the present invention is related to selectively identifying one or more instruction sets for implementation by a central processing unit.
- Microcontroller units have been used in the manufacturing and electrical industries for many years. Microcontrollers are typically equipped with a central processing unit (“CPU”) and ancillary elements. As with all hardware based devices, however, once the device has been released to the market, some users find need for modifications to the instruction set of the CPU. Unfortunately, once the CPU has been embedded within the semiconductor, modifications to the semiconductor substrate, and hence the behavior of the device is not possible. There is, therefore, a need in the art for a CPU that can accommodate new instructions yet still operate with older instructions.
- CPU central processing unit
- the invention overcomes the above-identified problems as well as other shortcomings and deficiencies of existing technologies by providing a microcontroller that has a fuse setting that selects between alternate instruction sets.
- a microcontroller that has a limited number of instructions that can be encoded as part of its opcode space, the ability to select between two or more instruction sets is desirable.
- behavior of existing instructions has to be altered.
- the CPU in order to facilitate backward compatibility with previously-developed code, the CPU must exhibit dual behavior: one or more targeted to the new instructions, and one targeted toward the legacy code. Additional instructions (in alternative sets) may be added.
- instruction selection mechanisms can be arranged in parallel and/or series in order to broaden the selections possible to two or more instruction sets.
- Figure 1 is a block diagram illustrating the configuration of a central processing unit with an instruction set selector according to the teachings of the present invention.
- Figure 2 is a block diagram illustrating the configuration of a central processing unit with a fuse according to the teachings of the present invention.
- Figure 3 is a flowchart illustrating a method of instruction set selection according to the teachings of the present invention.
- Figure 4 is a flowchart illustrating another embodiment of the method of instruction set selection according to the teachings of the present invention.
- a method, system and apparatus are provided for alternating instruction sets in central processing units.
- a microcontroller is provided with a fuse setting that, depending upon that setting, determines which of multiple instruction sets will be processed by the central processing unit. By changing the fuse setting the characteristics of the central processing unit, and thus the microcontroller as a whole, can be changed.
- the fuse settings can be changed so that one of two or more instruction sets can be chosen for implementation by the central processing unit. Alternatively, the fuse setting can be changed so that one or more subsets of a single instruction set can be executed, or disabled.
- a second instruction set, or parts of a first instruction set are enabled for execution by the central processor unit can be accomplished in a variety of ways.
- One example of switching is to use a fuse.
- the fuse can be a flash- based fuse that can reside externally to the processor or be . embedded, ithin the processor.
- the fuse can be set at the time of manufacture by, for example, burning away an element of the fuse, so that the processor exhibits different behaviors based on the fuse setting (and thus which instructions are executable). While a single fuse is depicted in the illustrative examples below, it will be understood that multiple fuses, or fuse equivalents, may be arranged in series and/or parallel to provide a richer array of choices of instructions, and thus behaviors for the same processor.
- enhancements other than instructions may be implemented by setting (or unsetting) the fuse or fuses. While it is preferable that the fuse be programmable or configurable (via, for example, flashing), it is not necessary that the fuse be programmable in order to practice the invention.
- the illustrative embodiment has two instruction sets. However, the present invention is capable of utilizing more than two instruction sets, or one or more parts of the same instruction set.
- the special operating modes and RESET modes are configured using two registers, conveniently called "CONFIG4L” and "TCFG4L”.
- a STVREN setting enables/disables the stack overflow/stack underflow reset. When set, the RESET due to stack overflow/underflow is enabled.
- Table 1 illustrates the registers and their potential settings.
- Configuration Register 4L CONFIG4L R/P-1 R/P-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 TCFG4L: R/W-1 R/W-1 U-0 U-0 U-0 R/W-1 U-0 ' R/W-1 BKBUG ENHCPU - - - LVP - STVREN bit 7 bit O
- 'R' indicates a readable bit
- 'W' indicates a writeable bit
- 'P' indicates a programmable bit
- 'U' indicates an unimplemented bit (but read as ⁇ 0')
- 0 indicates that the bit is cleared
- 'x' indicates the bit is unknown
- a dash ('-') followed by a digit indicates the fuse, namely the factory programmed value register, and the value at test RESET.
- the BKBUG is the background debugger enable bit.
- the ENHCPU is the enhanced CPU enable bit. In other words, in this embodiment, the ENHCPU bit is the fuse that enables alternate (or enhanced) instructions to be executed by the processor.
- LVP is the low voltage programming enable bit
- STVREN is the stack overflow reset enable bit.
- Each of the forgoing bits can be enabled or disabled by setting the bit to, for example, ' 1' or '0', respectively.
- the LVP fuse enables/disables low- voltage programming selection.
- low-voltage programming When set, low-voltage programming is enabled.
- ISP In-circuit serial programming
- PGM logic high on the program
- ICP In-circuit serial programming
- the parameter conveniently named "ENHCPU” enables/disables enhanced features of the CPU that are meant to be used with the C- compiler. Backwards compatibility is provided when the ENHCPU fuse is set to '0'.
- the instruction set selector 104 may be positioned in any convenient location, either as part of the central processing unit (see Figure lb), or elsewhere on, for example, the motherboard (not shown).
- Figure 2 illustrates another embodiment, wherein the instruction set selector is a fuse 204 that is external to the central processing unit 102.
- the fuse 204 similar to the embodiment of Figure lb, may be embedded within the central processing unit 102. Although a fuse 204 is contemplated, other embodiments of the present invention are possible so long as the instruction set selector 104 is capable of changing the mode within the central processing unit.
- Figure 3 illustrates a method of selecting an instruction set. The method begins generally at step 302.
- the central processing unit 102 is given a set of one or more instructions.
- step 304 determines of the fuse 204 is set. If the fuse 204 is set, then the central processing unit 102 uses the first instruction set in step 308. Otherwise, the central processing unit 102 uses the second instruction set in step 306. In either case, the instructions are executed and the method ends generally at step 310.
- Figure 4 illustrates another embodiment of the method of selecting an instruction set. In this case, the result of the fuse 204 being set is opposite from the method illustrated in Figure 3. Referring to Figure 4, the method begins generally at step 402. The central processing unit 102 is given a set of one or more instructions. A check is made in step 404 to determine of the fuse 204 is set.
- the central processing unit 102 uses the second instruction set in step 408. Otherwise, the central processing unit 102 uses the first instruction set in step 406. In either case, the instructions are executed and the method ends generally at step 410.
- the invention therefore, is well adapted to carry out the objects and attain the ends and advantages mentioned, as well as others inherent therein. While the invention has been depicted, described, and is defined by reference to exemplary embodiments of the invention, such references do not imply a limitation on the invention, and no such limitation is to be inferred. The invention is capable of considerable modification, alternation, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent arts and having the benefit of this disclosure. The depicted and described embodiments of the invention are exemplary only, and are not exhaustive of the scope of the invention. Consequently, the invention is intended to be limited only by the spirit and scope of the appended claims, giving full cognizance to equivalents in all respects.
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- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04795838A EP1687713A1 (en) | 2003-10-24 | 2004-10-20 | Method and system for alternating instructions sets in a central processing unit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US51427103P | 2003-10-24 | 2003-10-24 | |
US60/514,271 | 2003-10-24 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005043385A1 true WO2005043385A1 (en) | 2005-05-12 |
Family
ID=34549323
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2004/034730 WO2005043385A1 (en) | 2003-10-24 | 2004-10-20 | Method and system for alternating instructions sets in a central processing unit |
Country Status (6)
Country | Link |
---|---|
US (1) | US20050091474A1 (en) |
EP (1) | EP1687713A1 (en) |
KR (1) | KR20060125740A (en) |
CN (1) | CN1871580A (en) |
TW (1) | TW200521858A (en) |
WO (1) | WO2005043385A1 (en) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2006179124A (en) * | 2004-12-22 | 2006-07-06 | Renesas Technology Corp | Semiconductor memory |
US7975131B2 (en) * | 2005-12-23 | 2011-07-05 | Koninklijke Kpn N.V. | Processor lock |
US20090031108A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | Configurable fuse mechanism for implementing microcode patches |
US20090031110A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | Microcode patch expansion mechanism |
US20090031121A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | Apparatus and method for real-time microcode patch |
US20090031090A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | Apparatus and method for fast one-to-many microcode patch |
US20090031109A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | Apparatus and method for fast microcode patch from memory |
US20090031103A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | Mechanism for implementing a microcode patch during fabrication |
US20090031107A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | On-chip memory providing for microcode patch overlay and constant update functions |
US9274796B2 (en) | 2009-05-11 | 2016-03-01 | Arm Finance Overseas Limited | Variable register and immediate field encoding in an instruction set architecture |
US8880857B2 (en) | 2011-04-07 | 2014-11-04 | Via Technologies, Inc. | Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor |
US8880851B2 (en) | 2011-04-07 | 2014-11-04 | Via Technologies, Inc. | Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline |
US9645822B2 (en) | 2011-04-07 | 2017-05-09 | Via Technologies, Inc | Conditional store instructions in an out-of-order execution microprocessor |
US9176733B2 (en) | 2011-04-07 | 2015-11-03 | Via Technologies, Inc. | Load multiple and store multiple instructions in a microprocessor that emulates banked registers |
US9146742B2 (en) | 2011-04-07 | 2015-09-29 | Via Technologies, Inc. | Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA |
US9043580B2 (en) | 2011-04-07 | 2015-05-26 | Via Technologies, Inc. | Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA) |
US9032189B2 (en) | 2011-04-07 | 2015-05-12 | Via Technologies, Inc. | Efficient conditional ALU instruction in read-port limited register file microprocessor |
US9244686B2 (en) | 2011-04-07 | 2016-01-26 | Via Technologies, Inc. | Microprocessor that translates conditional load/store instructions into variable number of microinstructions |
US9128701B2 (en) | 2011-04-07 | 2015-09-08 | Via Technologies, Inc. | Generating constant for microinstructions from modified immediate field during instruction translation |
US9141389B2 (en) | 2011-04-07 | 2015-09-22 | Via Technologies, Inc. | Heterogeneous ISA microprocessor with shared hardware ISA registers |
US9292470B2 (en) | 2011-04-07 | 2016-03-22 | Via Technologies, Inc. | Microprocessor that enables ARM ISA program to access 64-bit general purpose registers written by x86 ISA program |
US8924695B2 (en) | 2011-04-07 | 2014-12-30 | Via Technologies, Inc. | Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor |
US9378019B2 (en) | 2011-04-07 | 2016-06-28 | Via Technologies, Inc. | Conditional load instructions in an out-of-order execution microprocessor |
US9336180B2 (en) | 2011-04-07 | 2016-05-10 | Via Technologies, Inc. | Microprocessor that makes 64-bit general purpose registers available in MSR address space while operating in non-64-bit mode |
US9274795B2 (en) | 2011-04-07 | 2016-03-01 | Via Technologies, Inc. | Conditional non-branch instruction prediction |
US9898291B2 (en) | 2011-04-07 | 2018-02-20 | Via Technologies, Inc. | Microprocessor with arm and X86 instruction length decoders |
US9317288B2 (en) | 2011-04-07 | 2016-04-19 | Via Technologies, Inc. | Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline |
CN111209186A (en) * | 2019-12-25 | 2020-05-29 | 上海亮牛半导体科技有限公司 | Protection structure of MCU user program code and fusing test method thereof |
Citations (3)
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GB2289353A (en) * | 1994-05-03 | 1995-11-15 | Advanced Risc Mach Ltd | Data processing with multiple instruction sets. |
US5758115A (en) * | 1994-06-10 | 1998-05-26 | Advanced Risc Machines Limited | Interoperability with multiple instruction sets |
US6076155A (en) * | 1995-10-24 | 2000-06-13 | S3 Incorporated | Shared register architecture for a dual-instruction-set CPU to facilitate data exchange between the instruction sets |
-
2004
- 2004-10-20 KR KR1020067008965A patent/KR20060125740A/en not_active Application Discontinuation
- 2004-10-20 EP EP04795838A patent/EP1687713A1/en not_active Withdrawn
- 2004-10-20 CN CNA200480031140XA patent/CN1871580A/en active Pending
- 2004-10-20 WO PCT/US2004/034730 patent/WO2005043385A1/en active Application Filing
- 2004-10-20 US US10/969,512 patent/US20050091474A1/en not_active Abandoned
- 2004-10-22 TW TW093132258A patent/TW200521858A/en unknown
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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GB2289353A (en) * | 1994-05-03 | 1995-11-15 | Advanced Risc Mach Ltd | Data processing with multiple instruction sets. |
US5758115A (en) * | 1994-06-10 | 1998-05-26 | Advanced Risc Machines Limited | Interoperability with multiple instruction sets |
US6076155A (en) * | 1995-10-24 | 2000-06-13 | S3 Incorporated | Shared register architecture for a dual-instruction-set CPU to facilitate data exchange between the instruction sets |
Also Published As
Publication number | Publication date |
---|---|
CN1871580A (en) | 2006-11-29 |
EP1687713A1 (en) | 2006-08-09 |
US20050091474A1 (en) | 2005-04-28 |
TW200521858A (en) | 2005-07-01 |
KR20060125740A (en) | 2006-12-06 |
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