WO2005038870A8 - Current starved dac-controlled delay locked loop - Google Patents

Current starved dac-controlled delay locked loop

Info

Publication number
WO2005038870A8
WO2005038870A8 PCT/US2004/032746 US2004032746W WO2005038870A8 WO 2005038870 A8 WO2005038870 A8 WO 2005038870A8 US 2004032746 W US2004032746 W US 2004032746W WO 2005038870 A8 WO2005038870 A8 WO 2005038870A8
Authority
WO
WIPO (PCT)
Prior art keywords
locked loop
delay locked
dac
controlled delay
current starved
Prior art date
Application number
PCT/US2004/032746
Other languages
French (fr)
Other versions
WO2005038870A2 (en
WO2005038870A3 (en
Inventor
Daniel J Meyer
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Priority to EP04794187A priority Critical patent/EP1692763A4/en
Publication of WO2005038870A2 publication Critical patent/WO2005038870A2/en
Publication of WO2005038870A3 publication Critical patent/WO2005038870A3/en
Publication of WO2005038870A8 publication Critical patent/WO2005038870A8/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1077—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the phase or frequency detection means

Abstract

A delay locked loop circuit with improved restart features. The circuit includes a clock input (1120, a clock output (116), a divider circuit (114), phase detector (118) and control logic (124). The circuit includes a means (126) for implementing a binary search of outputs from the control logic (124) for generating a calibration bit, which is applied to the transmission on an output line (120).
PCT/US2004/032746 2003-10-10 2004-10-04 Current starved dac-controlled delay locked loop WO2005038870A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP04794187A EP1692763A4 (en) 2003-10-10 2004-10-04 Current starved dac-controlled delay locked loop

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US51073903P 2003-10-10 2003-10-10
US60/510,739 2003-10-10
US10/836,704 US6927612B2 (en) 2003-10-10 2004-04-29 Current starved DAC-controlled delay locked loop
US10/836,704 2004-04-29

Publications (3)

Publication Number Publication Date
WO2005038870A2 WO2005038870A2 (en) 2005-04-28
WO2005038870A3 WO2005038870A3 (en) 2005-09-01
WO2005038870A8 true WO2005038870A8 (en) 2006-07-27

Family

ID=34426253

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/032746 WO2005038870A2 (en) 2003-10-10 2004-10-04 Current starved dac-controlled delay locked loop

Country Status (4)

Country Link
US (1) US6927612B2 (en)
EP (1) EP1692763A4 (en)
TW (1) TW200516860A (en)
WO (1) WO2005038870A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7024324B2 (en) * 2004-05-27 2006-04-04 Intel Corporation Delay element calibration
US7158443B2 (en) * 2005-06-01 2007-01-02 Micron Technology, Inc. Delay-lock loop and method adapting itself to operate over a wide frequency range
US7079064B1 (en) * 2005-09-26 2006-07-18 Motorola, Inc. Method and apparatus for phase control of a digital-to-analog converter
KR100834400B1 (en) * 2005-09-28 2008-06-04 주식회사 하이닉스반도체 DLL for increasing frequency of DRAM and output driver of the DLL
JP5290589B2 (en) * 2008-02-06 2013-09-18 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit
US8144529B2 (en) * 2009-03-31 2012-03-27 Intel Corporation System and method for delay locked loop relock mode
CA2693938A1 (en) * 2010-02-22 2011-08-22 Ibm Canada Limited - Ibm Canada Limitee Software object lock management using observations
KR102034150B1 (en) * 2012-06-27 2019-10-18 에스케이하이닉스 주식회사 Delay circuit and semiconductor apparatus including the same
CN105337611A (en) * 2014-07-04 2016-02-17 硅存储技术公司 Numerical control delay-locked ring reference generator

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5334952A (en) * 1993-03-29 1994-08-02 Spectralink Corporation Fast settling phase locked loop
JP3180780B2 (en) * 1998-10-13 2001-06-25 日本電気株式会社 Digital DLL circuit
US6204705B1 (en) * 1999-05-28 2001-03-20 Kendin Communications, Inc. Delay locked loop for sub-micron single-poly digital CMOS processes
JP4190662B2 (en) * 1999-06-18 2008-12-03 エルピーダメモリ株式会社 Semiconductor device and timing control circuit
US6323705B1 (en) * 2000-04-25 2001-11-27 Winbond Electronics Corporation Double cycle lock approach in delay lock loop circuit
US6691214B1 (en) * 2000-08-29 2004-02-10 Micron Technology, Inc. DDR II write data capture calibration
US6492852B2 (en) * 2001-03-30 2002-12-10 International Business Machines Corporation Pre-divider architecture for low power in a digital delay locked loop
KR100413764B1 (en) * 2001-07-14 2003-12-31 삼성전자주식회사 Variable delay circuit and method for controlling delay time
US6570420B1 (en) * 2002-08-29 2003-05-27 Sun Microsystems, Inc. Programmable current source adjustment of leakage current for delay locked loop

Also Published As

Publication number Publication date
US20050077937A1 (en) 2005-04-14
EP1692763A4 (en) 2006-10-04
WO2005038870A2 (en) 2005-04-28
TW200516860A (en) 2005-05-16
EP1692763A2 (en) 2006-08-23
WO2005038870A3 (en) 2005-09-01
US6927612B2 (en) 2005-08-09

Similar Documents

Publication Publication Date Title
US5629651A (en) Phase lock loop having a reduced synchronization transfer period
KR100512935B1 (en) Internal clock signal generating circuit and method
TW200701647A (en) Delay locked loop circuit
KR102001691B1 (en) Delay Locked Loop
WO2001069786A3 (en) A phase detector
TW200614677A (en) Delay locked loop and locking method thereof
WO2002001233A3 (en) Method and apparatus for adjusting the phase of input/output circuitry
TW200711316A (en) Clock generation circuit and clock generation method
WO2005038870A3 (en) Current starved dac-controlled delay locked loop
US6127866A (en) Delay-locked-loop (DLL) having symmetrical rising and falling clock edge type delays
TW454388B (en) A variable phase shifting clock generator
TW200501586A (en) Delay locked loop (DLL) circuit and method for locking clock delay by using the same
JPWO2002095947A1 (en) Semiconductor integrated circuit
US8963591B2 (en) Clock signal initialization circuit and its method
US7554371B2 (en) Delay locked loop
US8526559B2 (en) Communication systems and clock generation circuits thereof with reference source switching
JP3851511B2 (en) FM transmitter
US11251800B2 (en) Frequency divider circuit, demultiplexer circuit, and semiconductor integrated circuit
TW200715716A (en) DLL circuit having two input standard clocks, clock signal generation circuit having the DLL circuit and clock signal generation method
WO2004048000A3 (en) Phase-locked loop comprising a pulse generator, and method for operating said phase-locked loop
US8970268B2 (en) Semiconductor apparatus
KR0155523B1 (en) Secondary synchronizer of direct spread spectrum system
JP2021073767A (en) Demultiplexer circuit and semiconductor integrated circuit
JP2006303688A (en) Serial data transmitting device and serial data receiving device
JP2005328107A (en) Data transmission system, controller, and its method

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200480033601.7

Country of ref document: CN

AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2004794187

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 2004794187

Country of ref document: EP