WO2005038637A3 - Well-matched echo clock in memory system - Google Patents

Well-matched echo clock in memory system Download PDF

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Publication number
WO2005038637A3
WO2005038637A3 PCT/EP2004/011918 EP2004011918W WO2005038637A3 WO 2005038637 A3 WO2005038637 A3 WO 2005038637A3 EP 2004011918 W EP2004011918 W EP 2004011918W WO 2005038637 A3 WO2005038637 A3 WO 2005038637A3
Authority
WO
WIPO (PCT)
Prior art keywords
echo clock
controller
data bus
well
matched
Prior art date
Application number
PCT/EP2004/011918
Other languages
French (fr)
Other versions
WO2005038637A2 (en
Inventor
Jean-Marc Dortu
Jong-Hoon Oh
Original Assignee
Infineon Technologies Ag
Jean-Marc Dortu
Jong-Hoon Oh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Jean-Marc Dortu, Jong-Hoon Oh filed Critical Infineon Technologies Ag
Publication of WO2005038637A2 publication Critical patent/WO2005038637A2/en
Publication of WO2005038637A3 publication Critical patent/WO2005038637A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Abstract

The present invention is a random access memory device with a well-matched echo clock signa. The dynamic memory storage device includes a controller, a data bus and multiple memory modules. The data bus is coupled to the controller such that data read and data write information is transferred to and from the controller over the data bus. Multiple memory modules are coupled to the data bus and to the controller. Each of the memory module have a driver that produces an echo clock signal on an echo clock pin. The echo clock pin of each memory module is tied to each of the other memory modules and to the controller. In this way, during a read operation of the random access memory device the data bus and echo clock have matched loading conditions.
PCT/EP2004/011918 2003-10-21 2004-10-21 Well-matched echo clock in memory system WO2005038637A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/689,954 2003-10-21
US10/689,954 US20050086424A1 (en) 2003-10-21 2003-10-21 Well-matched echo clock in memory system

Publications (2)

Publication Number Publication Date
WO2005038637A2 WO2005038637A2 (en) 2005-04-28
WO2005038637A3 true WO2005038637A3 (en) 2008-01-03

Family

ID=34465620

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2004/011918 WO2005038637A2 (en) 2003-10-21 2004-10-21 Well-matched echo clock in memory system

Country Status (2)

Country Link
US (1) US20050086424A1 (en)
WO (1) WO2005038637A2 (en)

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US7296129B2 (en) 2004-07-30 2007-11-13 International Business Machines Corporation System, method and storage medium for providing a serialized memory interface with a bus repeater
US20060095620A1 (en) * 2004-10-29 2006-05-04 International Business Machines Corporation System, method and storage medium for merging bus data in a memory subsystem
US7512762B2 (en) 2004-10-29 2009-03-31 International Business Machines Corporation System, method and storage medium for a memory subsystem with positional read data latency
US7331010B2 (en) 2004-10-29 2008-02-12 International Business Machines Corporation System, method and storage medium for providing fault detection and correction in a memory subsystem
US7299313B2 (en) 2004-10-29 2007-11-20 International Business Machines Corporation System, method and storage medium for a memory subsystem command interface
US7478259B2 (en) * 2005-10-31 2009-01-13 International Business Machines Corporation System, method and storage medium for deriving clocks in a memory system
US7685392B2 (en) 2005-11-28 2010-03-23 International Business Machines Corporation Providing indeterminate read data latency in a memory system
US20080213853A1 (en) * 2006-02-27 2008-09-04 Antonio Garcia Magnetofluidics
WO2007101174A2 (en) * 2006-02-27 2007-09-07 Arizona Board Of Regents For And On Behalf Of Arizona State University Digital magnetofluidic devices and methods
US7594055B2 (en) * 2006-05-24 2009-09-22 International Business Machines Corporation Systems and methods for providing distributed technology independent memory controllers
US7669086B2 (en) 2006-08-02 2010-02-23 International Business Machines Corporation Systems and methods for providing collision detection in a memory system
US7870459B2 (en) 2006-10-23 2011-01-11 International Business Machines Corporation High density high reliability memory module with power gating and a fault tolerant address and command bus
US7721140B2 (en) * 2007-01-02 2010-05-18 International Business Machines Corporation Systems and methods for improving serviceability of a memory system
US7941689B2 (en) * 2008-03-19 2011-05-10 International Business Machines Corporation Minimizing clock uncertainty on clock distribution networks using a multi-level de-skewing technique
JP5025785B2 (en) * 2010-12-17 2012-09-12 株式会社東芝 Semiconductor memory device

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US6016282A (en) * 1998-05-28 2000-01-18 Micron Technology, Inc. Clock vernier adjustment
US6240024B1 (en) * 2000-04-10 2001-05-29 Motorola, Inc. Method and apparatus for generating an echo clock in a memory
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US20020161968A1 (en) * 2001-02-09 2002-10-31 Samsung Electronics Co., Ltd. Memory system having stub bus configuration
US20020184461A1 (en) * 2001-05-31 2002-12-05 Zumkehr John F. Method and apparatus for control calibration of multiple memory modules within a memory channel

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US5978931A (en) * 1997-07-16 1999-11-02 International Business Machines Corporation Variable domain redundancy replacement configuration for a memory device
US6100733A (en) * 1998-06-09 2000-08-08 Siemens Aktiengesellschaft Clock latency compensation circuit for DDR timing
US6043694A (en) * 1998-06-24 2000-03-28 Siemens Aktiengesellschaft Lock arrangement for a calibrated DLL in DDR SDRAM applications
US6127866A (en) * 1999-01-28 2000-10-03 Infineon Technologies North America Corp. Delay-locked-loop (DLL) having symmetrical rising and falling clock edge type delays
US6229364B1 (en) * 1999-03-23 2001-05-08 Infineon Technologies North America Corp. Frequency range trimming for a delay line
US6252443B1 (en) * 1999-04-20 2001-06-26 Infineon Technologies North America, Corp. Delay element using a delay locked loop

Patent Citations (6)

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US6330637B1 (en) * 1996-08-15 2001-12-11 Micron Technology, Inc. Synchronous DRAM modules including multiple clock out signals for increasing processing speed
US20020038404A1 (en) * 1996-08-15 2002-03-28 Ryan Kevin J. Synchronous DRAM modules with multiple clock out signals
US6016282A (en) * 1998-05-28 2000-01-18 Micron Technology, Inc. Clock vernier adjustment
US6240024B1 (en) * 2000-04-10 2001-05-29 Motorola, Inc. Method and apparatus for generating an echo clock in a memory
US20020161968A1 (en) * 2001-02-09 2002-10-31 Samsung Electronics Co., Ltd. Memory system having stub bus configuration
US20020184461A1 (en) * 2001-05-31 2002-12-05 Zumkehr John F. Method and apparatus for control calibration of multiple memory modules within a memory channel

Also Published As

Publication number Publication date
US20050086424A1 (en) 2005-04-21
WO2005038637A2 (en) 2005-04-28

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