WO2005034208A3 - METHOD TO REDUCE STACKING FAULT NUCLEATION SITES AND REDUCE Vf DRIFT IN BIPOLAR DEVICES - Google Patents

METHOD TO REDUCE STACKING FAULT NUCLEATION SITES AND REDUCE Vf DRIFT IN BIPOLAR DEVICES Download PDF

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Publication number
WO2005034208A3
WO2005034208A3 PCT/US2004/030041 US2004030041W WO2005034208A3 WO 2005034208 A3 WO2005034208 A3 WO 2005034208A3 US 2004030041 W US2004030041 W US 2004030041W WO 2005034208 A3 WO2005034208 A3 WO 2005034208A3
Authority
WO
WIPO (PCT)
Prior art keywords
reduce
substrate
drift
silicon carbide
thereafter
Prior art date
Application number
PCT/US2004/030041
Other languages
French (fr)
Other versions
WO2005034208A2 (en
Inventor
Joseph John Sumakeris
Original Assignee
Cree Inc
Joseph John Sumakeris
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cree Inc, Joseph John Sumakeris filed Critical Cree Inc
Priority to CA002539618A priority Critical patent/CA2539618A1/en
Priority to JP2006528051A priority patent/JP4723500B2/en
Priority to EP04784035A priority patent/EP1665343B1/en
Priority to DE602004025479T priority patent/DE602004025479D1/en
Priority to AT04784035T priority patent/ATE457523T1/en
Publication of WO2005034208A2 publication Critical patent/WO2005034208A2/en
Publication of WO2005034208A3 publication Critical patent/WO2005034208A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02019—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/931—Silicon carbide semiconductor

Abstract

A method is disclosed for preparing a substrate and epilayer for reducing stacking fault nucleation and reducing forward voltage (Vf) drift in silicon carbide-based bipolar devices. The method includes the steps of etching the surface of a silicon carbide substrate with a nonselective etch to remove both surface and subsurface damage, thereafter etching the same surface with a selective etch to thereby develop etch-generated structures from at least any basal plane dislocation reaching the substrate surface that will thereafter tend to either terminate or propagate as threading defects during subsequent epilayer growth on the substrate surface, and thereafter growing a first epitaxial layer of silicon carbide on the twice-etched surface.
PCT/US2004/030041 2003-09-22 2004-09-14 METHOD TO REDUCE STACKING FAULT NUCLEATION SITES AND REDUCE Vf DRIFT IN BIPOLAR DEVICES WO2005034208A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CA002539618A CA2539618A1 (en) 2003-09-22 2004-09-14 Method to reduce stacking fault nucleation sites and reduce vf drift in bipolar devices
JP2006528051A JP4723500B2 (en) 2003-09-22 2004-09-14 Method for reducing Vf drift in bipolar devices by reducing stacking fault nucleation sites
EP04784035A EP1665343B1 (en) 2003-09-22 2004-09-14 Method for reducing stacking fault nucleation sites in silicon carbide bipolar components
DE602004025479T DE602004025479D1 (en) 2003-09-22 2004-09-14 Method for reducing stacking fault nucleation sites in bipolar silicon carbide devices
AT04784035T ATE457523T1 (en) 2003-09-22 2004-09-14 METHOD FOR REDUCING STACKING DEFECTS IN BIPOLAR SILICON CARBIDE COMPONENTS

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/605,312 2003-09-22
US10/605,312 US7018554B2 (en) 2003-09-22 2003-09-22 Method to reduce stacking fault nucleation sites and reduce forward voltage drift in bipolar devices

Publications (2)

Publication Number Publication Date
WO2005034208A2 WO2005034208A2 (en) 2005-04-14
WO2005034208A3 true WO2005034208A3 (en) 2005-06-02

Family

ID=34312546

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/030041 WO2005034208A2 (en) 2003-09-22 2004-09-14 METHOD TO REDUCE STACKING FAULT NUCLEATION SITES AND REDUCE Vf DRIFT IN BIPOLAR DEVICES

Country Status (9)

Country Link
US (2) US7018554B2 (en)
EP (1) EP1665343B1 (en)
JP (1) JP4723500B2 (en)
CN (1) CN100470725C (en)
AT (1) ATE457523T1 (en)
CA (1) CA2539618A1 (en)
DE (1) DE602004025479D1 (en)
TW (1) TW200525582A (en)
WO (1) WO2005034208A2 (en)

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Also Published As

Publication number Publication date
DE602004025479D1 (en) 2010-03-25
EP1665343A2 (en) 2006-06-07
ATE457523T1 (en) 2010-02-15
US20050064723A1 (en) 2005-03-24
WO2005034208A2 (en) 2005-04-14
JP4723500B2 (en) 2011-07-13
US7279115B1 (en) 2007-10-09
TW200525582A (en) 2005-08-01
CA2539618A1 (en) 2005-04-14
JP2007506289A (en) 2007-03-15
EP1665343B1 (en) 2010-02-10
CN100470725C (en) 2009-03-18
US7018554B2 (en) 2006-03-28
US20070221614A1 (en) 2007-09-27
CN1856862A (en) 2006-11-01

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