WO2005029588A1 - 窒化物系半導体素子及びその製造方法 - Google Patents
窒化物系半導体素子及びその製造方法 Download PDFInfo
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- WO2005029588A1 WO2005029588A1 PCT/JP2004/013820 JP2004013820W WO2005029588A1 WO 2005029588 A1 WO2005029588 A1 WO 2005029588A1 JP 2004013820 W JP2004013820 W JP 2004013820W WO 2005029588 A1 WO2005029588 A1 WO 2005029588A1
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- nitride semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 302
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 193
- 238000000034 method Methods 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 140
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 133
- 239000010703 silicon Substances 0.000 claims abstract description 133
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 132
- 239000012535 impurity Substances 0.000 claims abstract description 30
- 238000009792 diffusion process Methods 0.000 claims abstract description 10
- 230000000694 effects Effects 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 239000000126 substance Substances 0.000 claims description 17
- 229910052782 aluminium Inorganic materials 0.000 claims description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 13
- 229910052738 indium Inorganic materials 0.000 claims description 11
- 230000005669 field effect Effects 0.000 claims description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- 229910052796 boron Inorganic materials 0.000 claims description 7
- 210000000746 body region Anatomy 0.000 claims description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 6
- 239000000969 carrier Substances 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 194
- 230000004888 barrier function Effects 0.000 description 26
- 229910002601 GaN Inorganic materials 0.000 description 17
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 17
- 229910052733 gallium Inorganic materials 0.000 description 13
- 230000000903 blocking effect Effects 0.000 description 12
- 238000005036 potential barrier Methods 0.000 description 11
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 10
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 10
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 8
- 239000007789 gas Substances 0.000 description 8
- 230000020169 heat generation Effects 0.000 description 6
- 125000005842 heteroatom Chemical group 0.000 description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 5
- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 229910000077 silane Inorganic materials 0.000 description 5
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 5
- 229910021529 ammonia Inorganic materials 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- 239000000956 alloy Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005253 cladding Methods 0.000 description 3
- 239000011777 magnesium Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000006798 recombination Effects 0.000 description 3
- 238000005215 recombination Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910003437 indium oxide Inorganic materials 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000001737 promoting effect Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910001295 No alloy Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000002344 gold compounds Chemical group 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- -1 nitride nitride Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
- H01L21/02507—Alternating layers, e.g. superlattice
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02576—N-type
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02579—P-type
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
Definitions
- Nitride-based semiconductor device and method of manufacturing the same
- the present invention relates to a nitride semiconductor device such as a light emitting diode (LED) and a transistor, and a method for manufacturing the same.
- a nitride semiconductor device such as a light emitting diode (LED) and a transistor
- a substrate for forming a nitride-based semiconductor device is made of sapphire, silicon carbide or silicon.
- the silicon substrate has features that it is easier to cut than a sapphire substrate and a silicon carbide substrate, and that the cost can be reduced. Further, the silicon substrate can have conductivity that cannot be obtained with a sapphire substrate. Therefore, the silicon substrate can be used as a current path. However, a relatively large voltage drop occurs due to a potential barrier between the silicon substrate and the nitride semiconductor, and the driving voltage of the light emitting diode becomes relatively high.
- Patent Document 1 discloses a technique for solving the above-mentioned disadvantages of a silicon substrate.
- an A1N (aluminum nitride) layer serving as a buffer layer an n-type InGaN (gallium indium nitride) layer having the same conductivity type as a silicon substrate, and an n-type GaN (nitride nitride) layer are provided on an n-type silicon substrate.
- a gallium (GaN) layer, an active layer of InGaN, and a p-type GaN layer are sequentially grown epitaxially.
- In and Ga of the InGaN layer and Al of the A1N layer diffuse into the silicon substrate, and an alloy layer composed of Ga, In, A1, and Si, that is, a gold compound region, is formed in the surface region of the silicon substrate. Occurs.
- This alloy layer has the function of lowering the potential barrier of the heterojunction between silicon and A1N. As a result, it is possible to lower the driving voltage when a predetermined current flows through the light emitting diode, to reduce the power loss, and to improve the efficiency.
- the above problem also occurs in a semiconductor element having a structure in which no alloy layer is interposed between an n-type silicon substrate and a buffer layer.
- the above-described problem also occurs in another semiconductor element such as a transistor that allows a current to flow in the thickness direction of the silicon substrate other than the light emitting diode.
- Another problem of the light emitting diode is that it is difficult to easily form an electrode that satisfies both light extraction and electrical connection. That is, in general, a mixture of indium oxide (In 2 O 3) and tin oxide (ZnO 2) is formed on the surface of a semiconductor region having a light emitting function.
- a light-impermeable bonding pad electrode for connecting a wire or the like is provided at approximately the center of the surface of the light-transmitting electrode. Since the light-transmitting electrode is a thin conductive film having a thickness of, for example, about 10 nm, the metal material of the bonding pad electrode diffuses to the light-transmitting electrode or to both the light-transmitting electrode and the semiconductor region, and the light-transmitting electrode and the semiconductor region become A Schottky barrier is formed between the bonding pad electrode and the bonding pad electrode.
- the Schottky barrier has a function of blocking a forward current of the light emitting diode, a current flowing in a portion of the semiconductor region below the bonding pad electrode is suppressed by the Schottky barrier, and conversely, a current in the outer peripheral portion of the semiconductor region is reduced. The current increases. Therefore, the Schottky barrier below the bonding pad electrode has the same function as the well-known current blocking layer, and contributes to the improvement of luminous efficiency.
- the current blocking layer is a layer that limits a current flowing in a region of the active layer facing the bonding pad electrode.
- the current flowing in the region facing the bonding pad electrode in the active layer is a reactive current that does not contribute to the luminous efficiency.
- the forward drive voltage of a light-emitting diode using an n-type silicon substrate is relatively large.
- the forward driving voltage of the light emitting diode is relatively high, the power loss in the silicon substrate and the semiconductor region increases, the heat generation increases, and the temperature in the Schottky barrier region increases.
- the characteristics of the above-described Schottky barrier deteriorate, and the leakage current through the Schottky barrier increases. Then, the current in the outer peripheral portion decreases. As a result, the current blocking function due to the Schottky barrier decreases, and the luminous efficiency also decreases.
- a light emitting diode provided with a well-known current blocking layer made of an insulating material between the bonding pad electrode and the semiconductor region includes a current blocking layer.
- a current blocking layer made of an insulating material between the bonding pad electrode and the semiconductor region.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2002-208729
- a problem to be solved by the present invention is that a nitride semiconductor element using a silicon substrate has a large voltage drop and a high driving voltage.
- the present invention for solving the above-mentioned problems includes a p-type silicon substrate having conductivity, and a group 3 element formed on one main surface of the p-type silicon substrate. an n-type nitride semiconductor region;
- a first electrode connected to the main semiconductor region
- a second electrode connected to the other main surface of the p-type silicon substrate
- the p-type silicon substrate has a group III element diffusion region in which the group III element of the n-type nitride semiconductor region is diffused in a portion adjacent to the n-type nitride semiconductor region.
- the present invention relates to a nitride-based semiconductor device.
- the main part of the semiconductor element means an active part or an active part of the semiconductor element. Also,
- the semiconductor element may have another electrode in addition to the first and second electrodes.
- the main semiconductor region includes at least an active layer and a P-type nitride semiconductor layer.
- the main semiconductor region includes at least a p-type base region and an n- type emitter region.
- the main semiconductor region includes at least a p-type body region and an n-type source region.
- the n-type nitride semiconductor region may be in contact with the P-type silicon substrate in a state where a current path from the n-type nitride semiconductor region to the p-type silicon substrate can be formed. desirable.
- the n-type nitride semiconductor region includes:
- n-type impurity is added to the material represented by
- the semiconductor element further includes an intervening layer disposed between the n-type nitride semiconductor region and the p-type silicon substrate, and the intervening layer can obtain a quantum mechanical tunnel effect. It is desirable to have a thickness and a resistivity higher than that of the n-type nitride semiconductor region.
- the material of the intervening layer is, for example, a chemical formula of AlInGaN, where x and y are 0 to x
- ⁇ 1, 0 ⁇ y ⁇ l a numerical value satisfying 0 ⁇ x + y ⁇ l, which is preferably a nitride semiconductor containing aluminum.
- the semiconductor element further includes a buffer region having a multilayer structure disposed between the n-type nitride semiconductor region and the main semiconductor region, and the buffer region having the multilayer structure includes Al (aluminum). And a plurality of second layers comprising a nitride semiconductor containing A1 in a first ratio and a second semiconductor layer not containing A1 or containing a second ratio smaller than the first ratio. It is preferable that the first layer and the second layer are alternately stacked.
- a plurality of first layers also comprising a nitride semiconductor containing the n-type nitride semiconductor region at a first ratio of AK aluminum; and a second ratio not containing A1 or smaller than the first ratio.
- a plurality of second layers made of a nitride semiconductor including the first layer and the second layer. And a buffer region having a multi-layer structure in which the layers are alternately stacked.
- the first layer of the buffer region of the multilayer structure has a chemical formula of Al M Ga N, wherein:
- M is at least one element selected from In (indium) and B (boron), and X and y satisfy 0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, x + y ⁇ l It is desirable to be made of a material represented by numerical values and have a thickness capable of obtaining a quantum mechanical tunnel effect.
- the second layer of the multi-layer buffer region has a chemical formula of Al M Ga N, wherein
- M is at least one element selected from In (indium) and B (boron), and a and b are 0 ⁇ a ⁇ l, 0 ⁇ b ⁇ l, a + b ⁇ l, a It is desirable to use a material represented by a numerical value satisfying x.
- an anode electrode electrically connected to the p-type nitride semiconductor layer is provided as the first electrode, and a force source electrode is used as the second electrode. It is desirable to provide.
- the first electrode of the light emitting diode is formed on a light-transmitting conductive film electrically connected to the p-type nitride semiconductor layer and on a part of the surface of the conductive film. It is desirable to constitute with the formed metal layer for connection.
- An n-type nitride semiconductor layer may be arranged between the p-type nitride semiconductor layer and the conductive film in the main semiconductor region of the light emitting diode.
- an emitter electrode electrically connected to the n-type emitter region is provided as the first electrode, and a collector electrode is provided as the second electrode. It is preferable to provide a base electrode electrically connected to the p-type base region.
- a source electrode electrically connected to the n-type source region is provided as the first electrode, and a drain electrode is provided as the second electrode. It is preferable to provide an electrode and further provide a gate electrode.
- the group 3 element of the n-type nitride semiconductor region is added to a part of the p-type silicon substrate. It is desirable to diffuse.
- At least one of the step of obtaining the intervening layer, the step of obtaining the n-type nitride semiconductor region, and the step of obtaining the main semiconductor region includes the aluminum of the intervening layer and the n-type nitride. It is desirable to diffuse the group 3 element of the semiconductor layer into a part of the p-type silicon substrate.
- the present invention it is possible to easily achieve a drastic reduction in the driving voltage of the semiconductor element while maintaining good crystallinity of the main semiconductor region. That is, despite the use of the n-type nitride semiconductor region, a p-type silicon substrate of the opposite conductivity type is used as the silicon substrate that comes into contact with the silicon substrate directly or through the intervening layer. . For this reason, the diffusion region of the group III element formed in the portion of the p-type silicon substrate adjacent to the n-type nitride semiconductor region becomes a low-resistance p-type region, and a pn junction is not formed in the p-type silicon substrate. As a result, the driving voltage of the semiconductor device decreases.
- an interface state exists at the heterojunction interface between the n-type nitride semiconductor region and the p-type silicon substrate.
- an intervening layer having a quantum mechanical tunnel effect is provided, an interface state exists between the n-type nitride semiconductor region and the p-type silicon substrate via the intervening layer.
- the interface state is determined by the n-type nitride semiconductor region and the p-type silicon substrate Is an energy level that contributes to electrical conduction between Due to the presence of the interface level, carriers (electrons) in the p-type silicon substrate are satisfactorily injected into the n-type nitride semiconductor region via the interface level.
- a potential barrier of a heterojunction between the p-type silicon substrate and the n-type nitride semiconductor region, or the n-type nitride semiconductor region and the p-type silicon substrate through an intervening layer having a quantum mechanical tunnel effect is reduced, and the driving voltage of the semiconductor element can be greatly reduced.
- the driving voltage is reduced, the power loss of the semiconductor device is reduced.
- the drive voltage can be reduced by a simple method of changing the conventional n-type silicon substrate to a p-type silicon substrate. Therefore, the drive voltage can be reduced without increasing the cost.
- the first electrode is a light-transmitting conductive film electrically connected to the p-type nitride semiconductor layer and a surface of the conductive film.
- a Schottky barrier is generated between the connection metal layer and the semiconductor region as described above, and the Schottky barrier is in the order of the light emitting diodes. It has the function of blocking directional current.
- the function of blocking the forward current of the light emitting diode due to the Schottky barrier is reduced.
- the power loss and heat generation of the light emitting diode according to the embodiment of the present invention are small, the function of blocking the forward current of the light emitting diode due to the Schottky barrier can be suppressed from being reduced, and the luminous efficiency is improved.
- FIG. 1 is a sectional view schematically showing a light emitting diode according to Example 1 of the present invention.
- FIG. 2 is a characteristic diagram showing the relationship between forward voltage and current of the light emitting diode of FIG. 1 and a conventional light emitting diode.
- FIG. 3 is an energy band diagram showing the effect of reducing the driving voltage of the light emitting diode of FIG. 1 in comparison with a conventional light emitting diode.
- FIG. 4 is a sectional view schematically showing a light emitting diode according to Embodiment 2 of the present invention.
- FIG. 5 is a sectional view schematically showing a light emitting diode according to a third embodiment of the present invention.
- FIG. 6 is a sectional view schematically showing a light emitting diode according to Example 4 of the present invention.
- FIG. 7 is a sectional view schematically showing a light emitting diode according to Embodiment 5 of the present invention.
- FIG. 8 is a sectional view schematically showing a transistor according to Example 6 of the present invention.
- FIG. 9 is a sectional view schematically showing a field-effect transistor according to Example 7 of the present invention.
- a light emitting diode as a semiconductor device according to the first embodiment of the present invention shown in FIG. 1 includes a p-type silicon substrate 1, a buffer region 3 as an n-type nitride semiconductor region, and a main part of a light-emitting diode. That is, it has a main semiconductor region 4 for forming an active portion, and first and second electrodes 5 and 6.
- a diffusion region la of the group 3 element of the n-type semiconductor region is generated.
- the main semiconductor region 4 includes an n-type nitride semiconductor layer 13, an active layer 14, and a p-type nitride semiconductor layer 15 epitaxially grown on the buffer region 3.
- the p-type silicon substrate 1 is a characteristic feature of the present invention, and has a conductivity type opposite to that of the n-type buffer region 3 despite being disposed thereon.
- This silicon substrate 1 elemental, for example 5 X 10 18 cm- 3 of Group 3, such as, for example, B (boron) serving as a p-type impurity That Akuseputa impurity - doped at a concentration of about 5 X 10 19 cm- 3 ing. Therefore, the silicon substrate 1 is a conductive substrate having a low resistivity of about 0.0001 ⁇ 'cm-0.01 ⁇ 'cm, and functions as a current path between the first and second electrodes 5, 6. . Further, the silicon substrate 1 has a thickness, for example, 350 nm, which can function as a mechanical support substrate for the buffer region 3 and the main semiconductor region 4 and the like thereon.
- Buffer region 3 as an n-type nitride semiconductor region disposed on p-type silicon substrate 1 Is an n-type nitride semiconductor composed of a group 3 element and nitrogen, for example,
- the buffer region 3 preferably has a material strength selected from AlInGaN (gallium indium aluminum nitride), GaN (gallium nitride), AlInN (indium nitride, aluminum), and AlGaN (gallium aluminum nitride). More preferably, it is made of indium aluminum (AlInGaN). In the above chemical formula, a is from 0.1 to 0.7, and b is from 0.0001 to 0.5.
- the composition of the nuffer region 3 in this practical example 1 is Al In GaN.
- n-type nitride semiconductor containing a group 3 element When an n-type nitride semiconductor containing a group 3 element is epitaxially grown on a p-type silicon substrate 1 to form an n-type buffer region 3, the group 3 element of the n-type buffer region 3 is converted into a p-type silicon substrate.
- the group III element diffusion region la is formed between the interface 2 between the p-type silicon substrate 1 and the n-type buffer region 3 and the position indicated by the dotted line in FIG.
- the group III element diffusion region la is a p-type semiconductor region having a lower resistivity than the portion of the p-type silicon substrate 1 where the group III element diffusion region la is not formed.
- the non-ferroelectric region 3 has a buffer function for favorably transferring the plane orientation of the silicon substrate 1 to the main semiconductor region 4 composed of a nitride semiconductor region formed thereon.
- the buffer region 3 has a thickness of 10 nm or more.
- the thickness of the buffer region 3 be 500 nm or less.
- the thickness of the buffer region 3 of the first embodiment is 30 nm.
- the energy difference between the lowest level of the conduction band of the nitride semiconductor and the highest level of the valence band of silicon is relatively small. For this reason, a well-known type 2 or type 3 heterojunction is formed at the interface 2 between the buffer region 3 made of the n-type nitride semiconductor and the p-type silicon substrate 1.
- the type 2 heterojunction is a heterojunction in the energy band diagram.
- the highest level of the valence band of one of the two semiconductors forming the junction lies between the highest level of the valence band of the other semiconductor and the lowest level of the conduction band, and the lowest level of one of the conduction bands. A junction whose level is above the lowest level of the other conduction band.
- a type 3 heterojunction is a junction in which the highest level of one valence band of two semiconductors forming a heterojunction is higher than the lowest level of the conduction band of the other semiconductor.
- the energy band structure of this hetero junction is shown in FIG. Can be indicated by FIG. 3 (B) shows an energy band structure between the n-type buffer region 3 and the p-type silicon substrate 1 in a thermal equilibrium state.
- Ev indicates the highest level of the valence band
- Ec indicates the lowest level of the conduction band
- Ef indicates the Fermi level.
- Et shown in the forbidden band in FIG. 3B indicates an interface state of a hetero junction between the p-type silicon substrate 1 and the n-type buffer region 3.
- a heterojunction of the above type 2 is formed as shown in FIG. 3 (B)
- a large number of interface states Et exist at the heterojunction interface 2 and the carrier of the valence band of the p-type silicon substrate 1 ( Electrons) are well injected into the conduction band of the buffer region 3 composed of the n-type semiconductor region via the interface state Et.
- the potential barrier at the heterojunction between the p-type silicon substrate 1 and the n-type buffer region 3 is reduced, and the driving voltage can be significantly reduced.
- the main semiconductor region 4 for a light emitting diode having a well-known double heterojunction structure has an n-type nitride semiconductor layer 13, an active layer 14, and a p-type And a nitride semiconductor layer 15.
- the main semiconductor region 4 can also be called a light emitting functional region or a light emitting active region.
- the buffer region 3 made of the n-type nitride semiconductor has the same function as the n-type nitride semiconductor layer 13 of the main semiconductor region 4 so that the n-type nitride semiconductor layer 13 can be omitted. Can be.
- the active layer 14 is omitted and the n-type nitride The semiconductor layer 13 and the p-type nitride semiconductor layer 15 can be brought into direct contact.
- the n-type nitride semiconductor layer 13 of the main semiconductor region 4 has a material strength represented by the following chemical formula ignoring n-type impurities.
- x and y are numerical values satisfying 0 ⁇ ⁇ 1, 0 ⁇ y ⁇ l.
- This n-type nitride semiconductor layer 13 can be called an n-type cladding layer of a light emitting diode, and has a larger band gap than the active layer 14.
- the active layer 14 is preferably made of a nitride semiconductor represented by the following chemical formula.
- x and y are numerical values satisfying 0 ⁇ ⁇ 1, 0 ⁇ y ⁇ l.
- the active layer 14 is formed of gallium indium nitride (InGaN).
- the active layer 14 has a force schematically shown by one layer. In fact, it has a well-known multiple quantum well structure. Needless to say, the active layer 14 can be composed of one layer. Further, in this embodiment, the active layer 14 is not doped with the conductivity type determining impurity, but may be doped with a p-type or n-type impurity.
- the p-type nitride semiconductor layer 15 disposed on the active layer 14 has a material strength represented by the following chemical formula, ignoring p-type impurities.
- the p-type nitride semiconductor layer 15 is formed of 500-nm-thick p-type GaN.
- the p-type nitride semiconductor layer 15 can be called a p-cladding layer, and has a larger band gap than the active layer 14.
- the n-type nitride semiconductor layer 13, the active layer 14 and the p-type nitride semiconductor layer 15 constituting the main semiconductor region 4 are formed on the silicon substrate 1 via the buffer region 3, so that the The crystallinity is relatively good.
- the first electrode 5 as an anode electrode is connected to the center of the p-type nitride semiconductor layer 15.
- the second electrode 6 as a force source electrode is connected to the lower surface of the p-type silicon substrate 1.
- a contact p-type nitride semiconductor layer is additionally provided on the p-type nitride semiconductor layer 15, and the first electrode 5 may be connected here. it can.
- a p-type silicon substrate 1 having a (111) -principal main surface is prepared according to the crystal orientation indicated by the Miller index.
- the silicon substrate 1 is subjected to a well-known hydrogen termination using an HF-based etchant.
- the substrate 1 is charged into a well-known ⁇ MVPE (Organometallic Vapor Phase Epitaxy), that is, a reaction chamber of a metal organic chemical vapor deposition apparatus, and the temperature is raised to, for example, 1170 ° C.
- thermal cleaning is performed at 1170 ° C. for 10 minutes to remove an oxide film on the surface of the substrate 1, and then a predetermined temperature of 1000 ° C. or more, for example, 1000-1100 ° C., and then the OMVPE method
- AlInGaN n-type gallium indium aluminum nitride
- the buffer region 3 is made of n-type gallium indium aluminum nitride (AlInGaN)
- AlInGaN n-type gallium indium aluminum nitride
- TMA trimethylaluminum gas
- TMI trimethylindium gas
- TMG Trimethylgallium gas
- ammonia gas ammonia gas
- SiH silane gas
- Si (silicon) of silane gas (SiH) functions as an n-type impurity.
- an n-type nitride semiconductor layer 13, an active layer 14 and a p-type nitride semiconductor layer 15 are sequentially formed on the buffer region 3 by a well-known epitaxy method to obtain a main semiconductor region 4.
- the temperature of the substrate 1 is set to, for example, 1000 to 1110 ° C., and for example, TMG, silane (SiH), and ammonia are required.
- n-type nitride semiconductor layer 13 of n-type GaN having a thickness of 2 ⁇ m is obtained.
- the n-type nitride semiconductor layer 13 has an n-type impurity concentration of, for example, 3 ⁇ 10 18 cm ⁇ 3 , which is lower than the impurity concentration of the silicon substrate 1.
- the buffer region 3 below has good crystallinity, so that the n-type nitride semiconductor layer 13 of the main semiconductor region 4 has the crystallinity of the buffer region 3. It has good crystallinity inherited from it.
- an active layer 14 having a well-known multiple quantum well structure is formed on the n-type nitride semiconductor layer 13 functioning as an n-type clad layer.
- the active layer 14 having a multi-quantum well structure is shown as a single layer for simplicity of illustration, but it is actually composed of a plurality of barrier layers and a plurality of well layers. The layers are alternately arranged, for example, four times.
- TMG, TMI and ammonia are supplied to the reaction chamber at a predetermined ratio, for example, a barrier layer which also has InGaN force and has a thickness of 13 nm is formed. Is changed to form a well layer having, for example, an InGaN force and having a thickness of, for example, 3 nm.
- the active layer 14 having a multiple quantum well structure can be obtained.
- the active layer 14 has good crystallinity by inheriting the crystallinity of the underlying n-type nitride semiconductor layer 13.
- the active layer 14 can be doped with, for example, a p-type impurity.
- the temperature of the silicon substrate 1 was raised to 1000-1110 ° C., and trimethylgallium gas (TMG), ammonia gas, and biscyclopentagenenyl magnesium gas (hereinafter, Cp Mg Is supplied at a predetermined ratio to form a p-type nitride semiconductor layer 15 made of p-type GaN with a thickness of about 500 nm on the active layer 14.
- TMG trimethylgallium gas
- Cp Mg Is supplied at a predetermined ratio to form a p-type nitride semiconductor layer 15 made of p-type GaN with a thickness of about 500 nm on the active layer 14.
- Magnesium (Mg) is introduced at a concentration of, for example, 3 ⁇ 10 18 cm ⁇ 3 and functions as a p-type impurity.
- the first and second electrodes 5 are formed by a well-known vacuum evaporation method to complete a light emitting diode.
- a characteristic line A in Fig. 2 indicates a current flowing through the light emitting diode according to the first embodiment when the first electrode 5 is applied with a positive forward voltage and the second electrode 6 is applied with a negative forward voltage. Is shown.
- the characteristic line B in FIG. 2 shows the current of the light emitting diode when a forward voltage is applied to the conventional light emitting diode having the n-type silicon substrate as in the case of Patent Document 1 described above.
- the drive voltage required to pass a current of 20 mA to the light emitting diode is 3.36 V for the characteristic line A and 3.98 V for the characteristic line B.
- FIG. 3 (A) shows the energy band state of the heterojunction according to the prior art for comparison
- FIG. 3 (B) shows the energy band state of the heterojunction according to the present invention.
- the heterojunction according to the prior art shown in FIG. 3A includes an n-type silicon substrate (n-Si) and an n-type nitride semiconductor (AlInGaN) directly epitaxially grown thereon.
- the n-type silicon substrate (n-Si) is diffused into the n-type silicon substrate (n-Si) by diffusion of a Group 3 element of an n-type nitride semiconductor (AlInGaN), for example, Ga.
- AlInGaN n-type nitride semiconductor
- a p-type semiconductor region is formed therein and a pn junction is formed in the n-type silicon substrate, thereby creating a potential barrier having a relatively high height A Eb. Therefore, the driving voltage of the semiconductor device including the heterojunction becomes relatively high.
- the hetero junction between the p-type silicon substrate 1 and the n-type buffer region 3 composed of the n-type nitride semiconductor (AlInGaN) according to the embodiment of the present invention shown in FIG.
- a group III element for example, one or more selected from Ga, Al, and In
- the group III element is a p-type impurity with respect to silicon.
- No pn junction is formed in 1.
- the potential barrier at the heterojunction is relatively low.
- a large number of interface states Et exist at interface 2 of the hetero junction.
- This interface level Et is located between the highest level of the valence band of the p-type silicon substrate 1 and the lowest level of the conduction band of the n-type buffer region 3 in the energy band diagram, and at the interface 2 of the heterojunction. It has the function of increasing the generation and recombination of electrons and holes.
- the interface 2 including the interface state Et and the vicinity thereof can be referred to as a region for promoting generation of electrons and holes and recombination.
- the group III element diffusion region la can be referred to as a region for promoting generation of electrons and holes and recombination.
- the light emission is performed while maintaining the crystallinity of the main semiconductor region 4 in good condition.
- Significant reduction in the drive voltage of the photodiode can be easily achieved.
- the driving voltage is reduced, the power loss of the light emitting diode is reduced.
- the driving voltage can be reduced by a simple method. Therefore, the driving voltage can be reduced without increasing the cost.
- FIG. 9 the substantially same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.
- the light emitting diode of FIG. 4 has a modified buffer region 3a in which a buffer region 20 of a multilayer structure is added to the buffer region 3 of FIG. 1, and the other configuration is the same as that of FIG.
- a multilayered buffer region 20 is disposed on the n-type buffer region 3 made of n-type gallium indium aluminum nitride (AlInGaN) formed in the same manner as in FIG. It is constituted by that.
- the multilayered buffer region 20 in FIG. 4 includes a plurality of first layers 21 and a plurality of second layers 22 that are arranged alternately and alternately.
- the plurality of first layers 21 are made of a nitride semiconductor containing A1 (aluminum) in a first ratio.
- the plurality of second layers 22 are made of a nitride semiconductor that does not contain A1 or contains a second proportion smaller than the first proportion.
- the first layer 21 is preferably made of a nitride semiconductor represented by the following chemical formula, ignoring n-type impurities.
- M is at least one element selected from In (indium) and B (boron), and X and y are 0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, x + y ⁇ 1 Is a numerical value that satisfies
- the first layer 21 has a thickness capable of obtaining a quantum mechanical tunnel effect, for example, 11 Onm.
- the first layer 21 of this embodiment is made of n-type A1N and contains Si (silicon) as an n-type impurity.
- the first layer 21 may not include an n-type impurity, or may be an undoped nitride semiconductor.
- the second layer 22 is made of a nitride semiconductor represented by the following chemical formula, ignoring n-type impurities. Is desirable.
- M is at least one element selected from In (indium) and B (boron), and a and b are 0 ⁇ a ⁇ l, 0 ⁇ b ⁇ l, a + b ⁇ l, It is a numerical value that satisfies a x. It is preferable to add silicon (Si) as an n-type impurity of the second layer 22. It is desirable that the second layer 22 be formed of the same nitride semiconductor as that of the n-type buffer region 3. In this embodiment, the second layer 22 is made of n-type GaN. The thickness of the second layer 22 is preferably as large as the thickness of the first layer 21 so as not to cause a quantum mechanical tunnel effect, and is preferably 10 ⁇ m or more. However, the second layer 22 may have a thickness at which a quantum mechanical tunnel effect can be obtained, or may have the same thickness as the first layer 21.
- the buffer region 20 having a multilayer structure of the modified buffer region 3a After forming the lower n-type buffer region 3, for example, 50 ⁇ mol / min of TMA (trimethylaluminum) and silane ( (SiH) at 20 nmol / min and ammonia at 0.14 mol / min.
- TMA trimethylaluminum
- SiH silane
- a first layer 21 of 5 nm A1N force is epitaxially grown. Thereafter, the supply of TMA is stopped, and the supply of silane and ammonia is continued. At the same time, TMG is flowed at a rate of 50 imol / min to epitaxially grow the second layer 22 of GaN having a thickness of 25 nm.
- the step of forming the first and second layers 21 and 22 is repeated 20 times to obtain a buffer region 20 having a multilayer structure. In FIG. 4, only four first and second layers 21 and 22 are shown for ease of illustration.
- the buffer region 3 can be omitted, and the buffer region 20 having a multilayer structure can be brought into direct contact with the p-type silicon substrate 1. That is, a buffer region 20 having a multilayer structure shown in FIG. 4 can be provided instead of the buffer region 3 shown in FIGS. 1 and 6 to 9.
- a buffer region 20 having a multilayer structure shown in FIG. 4 can be provided instead of the buffer region 3 shown in FIGS. 1 and 6 to 9.
- the light-emitting diode of Example 3 shown in FIG. 5 is different from the p-type silicon substrate 1 of FIG.
- the structure is the same as that of FIG. 1 except that an intervening layer 11 made of a nitride semiconductor containing aluminum is arranged between the region 3 and the n-type buffer region 3 is also used as an n-type cladding layer.
- the combination of the intermediate layer 11 and the n-type buffer region 3 is shown as a modified buffer region 3b, and the combination of the active layer 14 and the p-type nitride semiconductor region 15a made of InGaN is shown as a main semiconductor region 4a. ing.
- the intervening layer 11 be made of a nitride semiconductor represented by the following chemical formula.
- x and y are numerical values satisfying 0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, and 0 + x + y ⁇ 1.
- the n-type impurity is not included in the intervening layer 11.
- the intermediate layer 11 may include an n-type impurity.
- the intervening layer 11 is a film having a higher resistivity than the resistivity of the n-type buffer region 3.
- the intervening layer 11 has a thickness of, for example, about 110 nm, preferably about 2-3 nm, at which a quantum mechanical tunnel effect can be obtained. Therefore, the intervening layer 11 can be substantially ignored with respect to the conductivity between the n-type nitride semiconductor region 3 and the p-type silicon substrate 1. Therefore, carriers (electrons) in the p-type silicon substrate 1 are transferred to the n-type nitride semiconductor via the interface state Et existing at the heterojunction interface between the n-type buffer region 3 and the p-type silicon substrate 1. The region is well implanted into the n-type buffer region 3.
- the intervening layer 11 is made of a material smaller than the difference in lattice constant S between the p-type silicon substrate and the lattice constant difference S between the N-type buffer layer 3 or the main semiconductor region 4 and the p-type silicon substrate 1. It is desirable in terms of characteristics that Further, the intermediate layer 11 has a difference in thermal expansion coefficient between the P-type silicon substrate 1 and the N-type buffer substrate 3 or the main semiconductor region 4. It is desirable that the material is smaller than the material.
- the light emitting diode of Example 4 shown in FIG. 6 has a modified first electrode 5a, and the other configuration is the same as that of FIG.
- the first electrode 5a in FIG. 6 is a surface of the main semiconductor region 4, that is, a surface of the p-type nitride semiconductor layer 15.
- connection metal layer 52 which can be called a bonding pad electrode formed at a substantially central portion on the surface of the conductive film 51.
- the light-transmitting conductive film 51 has a thickness of about lOnm and is in ohmic contact with the p-type nitride semiconductor layer 15.
- the connection metal layer 52 is made of a metal such as Ni (nickel), Au (gold), and Al (aluminum), and is formed to a thickness that allows bonding of wires as shown in the figure. Since the connection metal layer 52 is thicker than the conductive film 51, the light generated in the main semiconductor region 4 is not substantially transmitted. Although not shown, the metal of the connection metal layer 52 diffused into the conductive film 51 or a part of the surface of the conductive film 51 and the main semiconductor region 4 at the time of forming the connection metal layer 52 or in a subsequent step. A region exists, and a Schottky barrier is formed between the metal layer 52 and the main semiconductor region 4.
- the conductive film 51 Current flows into region 4. Since the connection metal layer 52 is in Schottky contact with the main semiconductor region 4, the current is suppressed by the Schottky barrier, and the current flows through the Schottky barrier between the connection metal layer 52 and the main semiconductor region 4. It hardly flows. Therefore, the current component flowing from the conductive film 51 to the outer peripheral portion of the main semiconductor region 4 occupies most of the current between the first and second electrodes 5a and 6. Light generated based on the current flowing through the outer peripheral portion of the main semiconductor region 4 is extracted above the light-transmitting conductive film 51 without being disturbed by the light-impermeable connection metal layer 52.
- the Schottky barrier deteriorates as the temperature increases, and the leak current passing through the Schottky barrier increases. Since the light emitting diode of Example 4 in FIG. 6 uses the p-type silicon substrate 1 similarly to the light emitting diode of Example 1 in FIG. 1, the driving voltage in the forward direction is the same as in Example 1. Power loss and heat generation are smaller than those using a conventional n-type silicon substrate. Therefore, the degradation of the Schottky barrier between the connection metal layer 52 and the main semiconductor region 4 due to the heat generated in the silicon substrate 1 and the main semiconductor region 4 is suppressed, and the current passing through the Schottky barrier is reduced.
- the current between the first and second electrodes 5a and 6 is higher than that of a light emitting diode using a conventional n-type silicon substrate.
- the ratio of the current flowing through the outer peripheral portion of the main semiconductor region 4 to the total current becomes large, and the luminous efficiency becomes larger than that of the light emitting diode using the conventional n-type silicon substrate. If the heat generation of the main semiconductor region 4 and the silicon substrate 1 in FIG.
- the Schottky barrier functions in the same manner as in the conventional current blocking layer, so that the current blocking layer is not provided independently. Therefore, a special process for forming the current blocking layer is unnecessary, and the cost of the light emitting diode does not increase.
- the effect based on the p-type silicon substrate 1 can be obtained as in the first embodiment.
- the modified configuration of the first electrode 5a in FIG. 6 can be applied to the light emitting diodes of Examples 2 and 3 shown in FIGS.
- the light-emitting diode of Example 5 shown in FIG. 7 has an n-type auxiliary nitride semiconductor layer 53 added between the first electrode 5a and the main semiconductor region 4 of the light-emitting diode of Example 4 of FIG.
- the rest of the configuration is the same as that of FIG.
- the n-type auxiliary nitride semiconductor layer 53 is desirably made of a material represented by the following chemical formula, ignoring n-type impurities.
- x and y are numerical values satisfying 0 ⁇ ⁇ 1, 0 ⁇ y ⁇ l.
- n-type auxiliary nitride semiconductor layer 53 added in FIG. 7 is in contact with p-type nitride semiconductor layer 15, and the other main surface is in contact with light-transmitting conductive film 51.
- the light-transmitting conductive film 51 is made of ITO, since the ITO has the same characteristics as the n-type semiconductor, the ohmic contact resistance between the conductive film 51 and the n-type auxiliary nitride semiconductor layer 53 becomes extremely low, Here, the power loss is reduced, the forward drive voltage is further reduced, and the luminous efficiency is improved.
- the thickness of the n-type auxiliary nitride semiconductor layer 53 is 1-3011111, more preferably 5-10 nm. Further, the thickness of the n-type auxiliary nitride semiconductor layer 53 is desirably a thickness at which a quantum mechanical tunnel effect can be obtained.
- Example 5 When a forward voltage is applied between the first and second electrodes 5 a and 6 in FIG. 7, a current flows from the conductive film 51 to the p-type nitride semiconductor layer 15 via the n-type auxiliary nitride semiconductor layer 53.
- Example 5 the forward voltage drop between the p-type auxiliary nitride semiconductor layer 15 and the conductive film 51 via the n-type auxiliary nitride semiconductor layer 53 was reduced by the p-type auxiliary nitride shown in FIG. It is smaller than the forward voltage drop between the semiconductor layer 15 and the conductive film 51. Therefore, the forward drive voltage can be reduced, and the luminous efficiency is improved.
- the structure of the first electrode 5a of FIG. 7 and the n-type auxiliary nitride semiconductor layer 53 can be applied to the second and third embodiments of FIGS. 4 and 5.
- the transistor of Example 6 shown in FIG. 8 has the same configuration as that of FIG. 1 except that the main semiconductor region 4 for the light emitting diode of FIG. 1 is replaced by the main semiconductor region 4b for the transistor. It is.
- the n-type nitride semiconductor region 13 made of n-type GaN of the main semiconductor region 4b and the structure below it are the same as those in FIG.
- the main semiconductor region 4b includes an n-type nitride semiconductor region 13 functioning as a collector region, a base region 31 made of a p-type nitride semiconductor epitaxially grown thereon, and a An n- type nitride semiconductor grown by epitaxial growth has an emitter region 32.
- a base electrode 33 is connected to the base region 31, and an emitter electrode 34 as a first electrode is connected to the emitter region 32.
- the second electrode 6 on the lower surface of the p-type silicon substrate 1 functions as a collector electrode.
- the transistor in FIG. 8 is an npn transistor
- the second electrode 6 as a collector electrode is set to the highest potential, and the second electrode 6 is connected from the second electrode 6 side to the emitter electrode 34 side. Apply a current to it. Also in this transistor, the voltage drop at the time of ON between the two electrodes 6 and 34 can be reduced as in FIG.
- the insulated gate field effect transistor of Example 7 shown in FIG. 9 is the same as the light emitting diode of FIG. 1 is replaced by a main semiconductor region 4c for a field-effect transistor, and the other configuration is the same as that of FIG.
- An n-type nitride semiconductor region 13 made of the same n-type GaN as in FIG. 1 is provided in the main semiconductor region 4c in FIG.
- the n-type nitride semiconductor region 13 functions as a drain region.
- a body region 41 made of p-type nitride semiconductor is provided in the n-type nitride semiconductor region 13 by introducing a p-type impurity.
- a source region 42 made of a nitride semiconductor is provided.
- a gate electrode 44 is arranged on a surface of a body region 41 between a source region 42 and an n-type nitride semiconductor region 13 as a drain region via an insulating film 43.
- a source electrode 45 as a first electrode is connected to the source region 42.
- the second electrode 6 on the lower surface of the p-type silicon substrate 1 functions as a drain electrode.
- the voltage drop between the source electrode 45 and the drain electrode 6 at the time of ON driving is small.
- the n-type nitride semiconductor layer 13 is omitted, and the second layer 22 of the light emitting diode of FIG. 6 and FIG.
- the buffer region 3 of FIG. 9 can also be used as a collector region, and the buffer region 3 of FIG. 9 can also be used as a drain region.
- FIG. 4 Fig. 4, Fig. 6, Fig. 7, Fig. 8 and Fig. 9, the intervening layer consisting of A1N etc. having the quantum mechanical tunnel effect similar to Fig. 5 is provided between the buffer region 3 and the p-type silicon substrate 1.
- 11 can be arranged. That is, in FIG. 4, FIG. 6, FIG. 7, FIG. 8, and FIG. 9, an intervening layer made of A1N or the like having a quantum mechanical tunnel effect can be formed between the chain line 11 ′ and the p-type silicon substrate 1.
- the present invention can be applied to a rectifier diode having a pn junction or a Schottky barrier diode having a Schottky barrier electrode. Further, the present invention can be applied to all semiconductor elements in which current flows in the thickness direction of the substrate 1. Industrial applicability
- the present invention is applicable to semiconductor devices such as light emitting diodes, transistors, field effect transistors, and rectifier diodes.
Abstract
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US20060175628A1 (en) | 2006-08-10 |
JP4168284B2 (ja) | 2008-10-22 |
JPWO2005029588A1 (ja) | 2006-11-30 |
TWI240439B (en) | 2005-09-21 |
CN1846310B (zh) | 2011-03-09 |
CN1846310A (zh) | 2006-10-11 |
US7671375B2 (en) | 2010-03-02 |
TW200512959A (en) | 2005-04-01 |
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