WO2005029576A3 - Glass-based soi structures - Google Patents
Glass-based soi structures Download PDFInfo
- Publication number
- WO2005029576A3 WO2005029576A3 PCT/US2004/004746 US2004004746W WO2005029576A3 WO 2005029576 A3 WO2005029576 A3 WO 2005029576A3 US 2004004746 W US2004004746 W US 2004004746W WO 2005029576 A3 WO2005029576 A3 WO 2005029576A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- glass
- ceramic
- semiconductor
- support substrate
- oxide glass
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
Abstract
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE602004030223T DE602004030223D1 (en) | 2003-02-18 | 2004-02-17 | METHOD OF MANUFACTURING GLASS BASED SOI STRUCTURES |
JP2006508760A JP5152819B2 (en) | 2003-02-18 | 2004-02-17 | Glass-based SOI structure |
KR1020107024019A KR101103947B1 (en) | 2003-02-18 | 2004-02-17 | Glass-based SOI structures |
EP04809284A EP1599901B1 (en) | 2003-02-18 | 2004-02-17 | Method of manufacturing glass-based soi structures |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US44817603P | 2003-02-18 | 2003-02-18 | |
US60/448,176 | 2003-02-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2005029576A2 WO2005029576A2 (en) | 2005-03-31 |
WO2005029576A3 true WO2005029576A3 (en) | 2005-08-25 |
Family
ID=34375175
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2004/004746 WO2005029576A2 (en) | 2003-02-18 | 2004-02-17 | Glass-based soi structures |
Country Status (9)
Country | Link |
---|---|
US (5) | US7176528B2 (en) |
EP (4) | EP1599901B1 (en) |
JP (3) | JP5152819B2 (en) |
KR (5) | KR100997597B1 (en) |
CN (1) | CN100373586C (en) |
DE (1) | DE602004030223D1 (en) |
SG (1) | SG154331A1 (en) |
TW (1) | TWI323485B (en) |
WO (1) | WO2005029576A2 (en) |
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