WO2005022381A3 - Integrated mechanism for suspension and deallocation of computational threads of execution in a processor - Google Patents

Integrated mechanism for suspension and deallocation of computational threads of execution in a processor Download PDF

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Publication number
WO2005022381A3
WO2005022381A3 PCT/US2004/028108 US2004028108W WO2005022381A3 WO 2005022381 A3 WO2005022381 A3 WO 2005022381A3 US 2004028108 W US2004028108 W US 2004028108W WO 2005022381 A3 WO2005022381 A3 WO 2005022381A3
Authority
WO
WIPO (PCT)
Prior art keywords
operand
microprocessor
instruction
qualifier
yield
Prior art date
Application number
PCT/US2004/028108
Other languages
French (fr)
Other versions
WO2005022381A2 (en
Inventor
Kevin Kissel
Original Assignee
Mips Tech Inc
Kevin Kissel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/684,348 external-priority patent/US20050050305A1/en
Priority claimed from US10/684,350 external-priority patent/US7376954B2/en
Application filed by Mips Tech Inc, Kevin Kissel filed Critical Mips Tech Inc
Priority to CN2004800248529A priority Critical patent/CN1846194B/en
Priority to EP04786607A priority patent/EP1660993B1/en
Priority to JP2006524929A priority patent/JP4818919B2/en
Priority to DE602004017879T priority patent/DE602004017879D1/en
Publication of WO2005022381A2 publication Critical patent/WO2005022381A2/en
Publication of WO2005022381A3 publication Critical patent/WO2005022381A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/3009—Thread control instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/443—Optimisation
    • G06F8/4441—Reducing the execution time required by the program code
    • G06F8/4442—Reducing the number of cache misses; Data prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication

Abstract

A yield instruction for execution in a multithreaded microprocessor is disclosed. The yield instruction includes an operand. If the operand is zero the microprocessor terminates the program thread including the yield instruction. If the operand is -1 the microprocessor unconditionally reschedules the program thread. If the operand is a positive integer the microprocessor views the operand as a bit vector specifying one or more yield qualifier inputs, such as interrupt signals, and conditionally reschedules the thread based on the qualifier inputs and bit vector values. The microprocessor also includes a mask register that specifies a bit vector of the qualifier inputs. If the operand specifies a qualifier input not also specified in the mask register, an exception to the instruction is raised. The instruction returns a value specifying the values of the qualifier inputs qualified by the mask register value.
PCT/US2004/028108 2003-08-28 2004-08-27 Integrated mechanism for suspension and deallocation of computational threads of execution in a processor WO2005022381A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2004800248529A CN1846194B (en) 2003-08-28 2004-08-27 Method and device for executing Parallel programs thread
EP04786607A EP1660993B1 (en) 2003-08-28 2004-08-27 Integrated mechanism for suspension and deallocation of computational threads of execution in a processor
JP2006524929A JP4818919B2 (en) 2003-08-28 2004-08-27 Integrated mechanism for suspending and deallocating computational threads of execution within a processor
DE602004017879T DE602004017879D1 (en) 2003-08-28 2004-08-27 INTEGRATED MECHANISM FOR SUSPENDING AND FINAL PROCESSOR

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US49918003P 2003-08-28 2003-08-28
US60/499,180 2003-08-28
US50235903P 2003-09-12 2003-09-12
US50235803P 2003-09-12 2003-09-12
US60/502,358 2003-09-12
US60/502,359 2003-09-12
US10/684,348 US20050050305A1 (en) 2003-08-28 2003-10-10 Integrated mechanism for suspension and deallocation of computational threads of execution in a processor
US10/684,350 US7376954B2 (en) 2003-08-28 2003-10-10 Mechanisms for assuring quality of service for programs executing on a multithreaded processor
US10/684,350 2003-10-10
US10/684,348 2003-10-10

Publications (2)

Publication Number Publication Date
WO2005022381A2 WO2005022381A2 (en) 2005-03-10
WO2005022381A3 true WO2005022381A3 (en) 2005-06-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/028108 WO2005022381A2 (en) 2003-08-28 2004-08-27 Integrated mechanism for suspension and deallocation of computational threads of execution in a processor

Country Status (5)

Country Link
US (6) US7694304B2 (en)
EP (3) EP1660998A1 (en)
JP (3) JP4818919B2 (en)
DE (1) DE602004017879D1 (en)
WO (1) WO2005022381A2 (en)

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